Files
kaizen/external/capstone/MCInst.c
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

332 lines
7.4 KiB
C

/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#if defined(CAPSTONE_HAS_OSXKERNEL)
#include <Availability.h>
#include <libkern/libkern.h>
#else
#include <stdio.h>
#include <stdlib.h>
#endif
#include <string.h>
#include <assert.h>
#include "MCInstrDesc.h"
#include "MCInst.h"
#include "utils.h"
#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
void MCInst_Init(MCInst *inst, cs_arch arch)
{
memset(inst, 0, sizeof(MCInst));
// unnecessary to initialize in loop . its expensive and inst->size should be honored
inst->Operands[0].Kind = kInvalid;
inst->Operands[0].ImmVal = 0;
inst->Opcode = 0;
inst->OpcodePub = 0;
inst->size = 0;
inst->has_imm = false;
inst->op1_size = 0;
inst->ac_idx = 0;
inst->popcode_adjust = 0;
inst->assembly[0] = '\0';
inst->wasm_data.type = WASM_OP_INVALID;
inst->xAcquireRelease = 0;
for (int i = 0; i < MAX_MC_OPS; ++i)
inst->tied_op_idx[i] = -1;
inst->isAliasInstr = false;
inst->fillDetailOps = false;
memset(&inst->hppa_ext, 0, sizeof(inst->hppa_ext));
// Set default assembly dialect.
switch (arch) {
default:
break;
case CS_ARCH_SYSTEMZ:
inst->MAI.assemblerDialect = SYSTEMZASMDIALECT_AD_HLASM;
break;
}
}
void MCInst_clear(MCInst *inst)
{
inst->size = 0;
}
// does not free @Op
void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
{
CS_ASSERT_RET(index < MAX_MC_OPS);
int i;
for(i = inst->size; i > index; i--)
//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
inst->Operands[i] = inst->Operands[i-1];
inst->Operands[index] = *Op;
inst->size++;
}
void MCInst_setOpcode(MCInst *inst, unsigned Op)
{
inst->Opcode = Op;
}
void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
{
inst->OpcodePub = Op;
}
unsigned MCInst_getOpcode(const MCInst *inst)
{
return inst->Opcode;
}
unsigned MCInst_getOpcodePub(const MCInst *inst)
{
return inst->OpcodePub;
}
MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
{
assert(i < MAX_MC_OPS);
return &inst->Operands[i];
}
unsigned MCInst_getNumOperands(const MCInst *inst)
{
return inst->size;
}
// This addOperand2 function doesn't free Op
void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
{
CS_ASSERT_RET(inst->size < MAX_MC_OPS);
inst->Operands[inst->size] = *Op;
inst->size++;
}
bool MCOperand_isValid(const MCOperand *op)
{
return op->Kind != kInvalid;
}
bool MCOperand_isReg(const MCOperand *op)
{
return op->Kind == kRegister || op->MachineOperandType == kRegister;
}
bool MCOperand_isImm(const MCOperand *op)
{
return op->Kind == kImmediate || op->MachineOperandType == kImmediate;
}
bool MCOperand_isFPImm(const MCOperand *op)
{
return op->Kind == kFPImmediate;
}
bool MCOperand_isDFPImm(const MCOperand *op)
{
return op->Kind == kDFPImmediate;
}
bool MCOperand_isExpr(const MCOperand *op)
{
return op->Kind == kExpr;
}
bool MCOperand_isInst(const MCOperand *op)
{
return op->Kind == kInst;
}
/// getReg - Returns the register number.
unsigned MCOperand_getReg(const MCOperand *op)
{
return op->RegVal;
}
/// setReg - Set the register number.
void MCOperand_setReg(MCOperand *op, unsigned Reg)
{
op->RegVal = Reg;
}
int64_t MCOperand_getImm(const MCOperand *op)
{
return op->ImmVal;
}
int64_t MCOperand_getExpr(const MCOperand *op)
{
return op->ImmVal;
}
void MCOperand_setImm(MCOperand *op, int64_t Val)
{
op->ImmVal = Val;
}
double MCOperand_getFPImm(const MCOperand *op)
{
return op->FPImmVal;
}
void MCOperand_setFPImm(MCOperand *op, double Val)
{
op->FPImmVal = Val;
}
MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
{
MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
op->MachineOperandType = kRegister;
op->Kind = kRegister;
op->RegVal = Reg;
return op;
}
void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
{
MCOperand *op = &(mcInst->Operands[mcInst->size]);
mcInst->size++;
op->MachineOperandType = kRegister;
op->Kind = kRegister;
op->RegVal = Reg;
}
MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
{
MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
op->MachineOperandType = kImmediate;
op->Kind = kImmediate;
op->ImmVal = Val;
return op;
}
void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
{
assert(mcInst->size < MAX_MC_OPS);
MCOperand *op = &(mcInst->Operands[mcInst->size]);
mcInst->size++;
op->MachineOperandType = kImmediate;
op->Kind = kImmediate;
op->ImmVal = Val;
}
/// Check if any operand of the MCInstrDesc is predicable
bool MCInst_isPredicable(const MCInstrDesc *MIDesc)
{
const MCOperandInfo *OpInfo = MIDesc->OpInfo;
unsigned NumOps = MIDesc->NumOperands;
for (unsigned i = 0; i < NumOps; ++i) {
if (MCOperandInfo_isPredicate(&OpInfo[i])) {
return true;
}
}
return false;
}
/// Checks if tied operands exist in the instruction and sets
/// - The writeback flag in detail
/// - Saves the indices of the tied destination operands.
void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size)
{
const MCInstrDesc *InstDesc = NULL;
const MCOperandInfo *OpInfo = NULL;
unsigned short NumOps = 0;
InstDesc = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size);
OpInfo = InstDesc->OpInfo;
NumOps = InstDesc->NumOperands;
for (unsigned i = 0; i < NumOps; ++i) {
if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
int idx = MCOperandInfo_getOperandConstraint(
InstDesc, i,
MCOI_TIED_TO);
if (idx == -1)
continue;
if (i >= MAX_MC_OPS) {
assert(0 &&
"Maximum number of MC operands reached.");
}
MI->tied_op_idx[i] = idx;
if (MI->flat_insn->detail)
MI->flat_insn->detail->writeback = true;
}
}
}
/// Check if operand with OpNum is tied by another operand
/// (operand is tying destination).
bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum)
{
assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
for (int i = 0; i < MAX_MC_OPS; ++i) {
if (MI->tied_op_idx[i] == OpNum)
return true;
}
return false;
}
/// Check if operand with OpNum is tying another operand
/// (operand is tying src).
bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum)
{
assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
return MI->tied_op_idx[OpNum] != -1;
}
/// Returns the value of the @MCInst operand at index @OpNum.
uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
{
assert(OpNum < MAX_MC_OPS);
MCOperand *op = MCInst_getOperand(MI, OpNum);
if (MCOperand_isReg(op))
return MCOperand_getReg(op);
else if (MCOperand_isImm(op))
return MCOperand_getImm(op);
else
assert(0 && "Operand type not handled in this getter.");
return MCOperand_getImm(op);
}
void MCInst_setIsAlias(MCInst *MI, bool Flag) {
assert(MI);
MI->isAliasInstr = Flag;
MI->flat_insn->is_alias = Flag;
}
/// @brief Copies the relevant members of a temporary MCInst to
/// the main MCInst. This is used if TryDecode was run on a temporary MCInst.
/// @param MI The main MCInst
/// @param TmpMI The temporary MCInst.
void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
MI->size = TmpMI->size;
MI->Opcode = TmpMI->Opcode;
assert(MI->size < MAX_MC_OPS);
memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
}
/// @brief Sets the softfail/illegal flag in the cs_insn.
/// Setting it indicates the instruction can be decoded, but is invalid
/// due to not allowed operands or an illegal context.
///
/// @param MI The MCInst holding the cs_insn currently decoded.
void MCInst_setSoftFail(MCInst *MI) {
assert(MI && MI->flat_insn);
MI->flat_insn->illegal = true;
}