00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
332 lines
7.4 KiB
C
332 lines
7.4 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#if defined(CAPSTONE_HAS_OSXKERNEL)
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#include <Availability.h>
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#include <libkern/libkern.h>
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#else
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#include <stdio.h>
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#include <stdlib.h>
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#endif
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#include <string.h>
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#include <assert.h>
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#include "MCInstrDesc.h"
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#include "MCInst.h"
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#include "utils.h"
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#define MCINST_CACHE (ARR_SIZE(mcInst->Operands) - 1)
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void MCInst_Init(MCInst *inst, cs_arch arch)
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{
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memset(inst, 0, sizeof(MCInst));
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// unnecessary to initialize in loop . its expensive and inst->size should be honored
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inst->Operands[0].Kind = kInvalid;
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inst->Operands[0].ImmVal = 0;
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inst->Opcode = 0;
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inst->OpcodePub = 0;
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inst->size = 0;
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inst->has_imm = false;
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inst->op1_size = 0;
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inst->ac_idx = 0;
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inst->popcode_adjust = 0;
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inst->assembly[0] = '\0';
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inst->wasm_data.type = WASM_OP_INVALID;
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inst->xAcquireRelease = 0;
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for (int i = 0; i < MAX_MC_OPS; ++i)
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inst->tied_op_idx[i] = -1;
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inst->isAliasInstr = false;
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inst->fillDetailOps = false;
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memset(&inst->hppa_ext, 0, sizeof(inst->hppa_ext));
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// Set default assembly dialect.
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switch (arch) {
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default:
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break;
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case CS_ARCH_SYSTEMZ:
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inst->MAI.assemblerDialect = SYSTEMZASMDIALECT_AD_HLASM;
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break;
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}
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}
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void MCInst_clear(MCInst *inst)
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{
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inst->size = 0;
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}
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// does not free @Op
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void MCInst_insert0(MCInst *inst, int index, MCOperand *Op)
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{
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CS_ASSERT_RET(index < MAX_MC_OPS);
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int i;
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for(i = inst->size; i > index; i--)
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//memcpy(&(inst->Operands[i]), &(inst->Operands[i-1]), sizeof(MCOperand));
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inst->Operands[i] = inst->Operands[i-1];
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inst->Operands[index] = *Op;
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inst->size++;
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}
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void MCInst_setOpcode(MCInst *inst, unsigned Op)
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{
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inst->Opcode = Op;
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}
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void MCInst_setOpcodePub(MCInst *inst, unsigned Op)
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{
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inst->OpcodePub = Op;
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}
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unsigned MCInst_getOpcode(const MCInst *inst)
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{
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return inst->Opcode;
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}
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unsigned MCInst_getOpcodePub(const MCInst *inst)
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{
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return inst->OpcodePub;
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}
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MCOperand *MCInst_getOperand(MCInst *inst, unsigned i)
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{
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assert(i < MAX_MC_OPS);
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return &inst->Operands[i];
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}
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unsigned MCInst_getNumOperands(const MCInst *inst)
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{
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return inst->size;
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}
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// This addOperand2 function doesn't free Op
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void MCInst_addOperand2(MCInst *inst, MCOperand *Op)
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{
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CS_ASSERT_RET(inst->size < MAX_MC_OPS);
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inst->Operands[inst->size] = *Op;
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inst->size++;
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}
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bool MCOperand_isValid(const MCOperand *op)
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{
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return op->Kind != kInvalid;
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}
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bool MCOperand_isReg(const MCOperand *op)
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{
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return op->Kind == kRegister || op->MachineOperandType == kRegister;
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}
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bool MCOperand_isImm(const MCOperand *op)
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{
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return op->Kind == kImmediate || op->MachineOperandType == kImmediate;
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}
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bool MCOperand_isFPImm(const MCOperand *op)
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{
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return op->Kind == kFPImmediate;
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}
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bool MCOperand_isDFPImm(const MCOperand *op)
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{
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return op->Kind == kDFPImmediate;
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}
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bool MCOperand_isExpr(const MCOperand *op)
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{
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return op->Kind == kExpr;
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}
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bool MCOperand_isInst(const MCOperand *op)
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{
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return op->Kind == kInst;
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}
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/// getReg - Returns the register number.
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unsigned MCOperand_getReg(const MCOperand *op)
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{
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return op->RegVal;
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}
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/// setReg - Set the register number.
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void MCOperand_setReg(MCOperand *op, unsigned Reg)
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{
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op->RegVal = Reg;
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}
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int64_t MCOperand_getImm(const MCOperand *op)
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{
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return op->ImmVal;
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}
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int64_t MCOperand_getExpr(const MCOperand *op)
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{
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return op->ImmVal;
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}
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void MCOperand_setImm(MCOperand *op, int64_t Val)
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{
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op->ImmVal = Val;
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}
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double MCOperand_getFPImm(const MCOperand *op)
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{
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return op->FPImmVal;
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}
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void MCOperand_setFPImm(MCOperand *op, double Val)
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{
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op->FPImmVal = Val;
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}
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MCOperand *MCOperand_CreateReg1(MCInst *mcInst, unsigned Reg)
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{
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MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
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op->MachineOperandType = kRegister;
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op->Kind = kRegister;
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op->RegVal = Reg;
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return op;
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}
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void MCOperand_CreateReg0(MCInst *mcInst, unsigned Reg)
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{
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MCOperand *op = &(mcInst->Operands[mcInst->size]);
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mcInst->size++;
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op->MachineOperandType = kRegister;
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op->Kind = kRegister;
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op->RegVal = Reg;
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}
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MCOperand *MCOperand_CreateImm1(MCInst *mcInst, int64_t Val)
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{
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MCOperand *op = &(mcInst->Operands[MCINST_CACHE]);
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op->MachineOperandType = kImmediate;
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op->Kind = kImmediate;
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op->ImmVal = Val;
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return op;
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}
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void MCOperand_CreateImm0(MCInst *mcInst, int64_t Val)
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{
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assert(mcInst->size < MAX_MC_OPS);
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MCOperand *op = &(mcInst->Operands[mcInst->size]);
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mcInst->size++;
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op->MachineOperandType = kImmediate;
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op->Kind = kImmediate;
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op->ImmVal = Val;
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}
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/// Check if any operand of the MCInstrDesc is predicable
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bool MCInst_isPredicable(const MCInstrDesc *MIDesc)
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{
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const MCOperandInfo *OpInfo = MIDesc->OpInfo;
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unsigned NumOps = MIDesc->NumOperands;
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for (unsigned i = 0; i < NumOps; ++i) {
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if (MCOperandInfo_isPredicate(&OpInfo[i])) {
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return true;
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}
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}
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return false;
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}
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/// Checks if tied operands exist in the instruction and sets
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/// - The writeback flag in detail
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/// - Saves the indices of the tied destination operands.
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void MCInst_handleWriteback(MCInst *MI, const MCInstrDesc *InstDescTable, unsigned tbl_size)
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{
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const MCInstrDesc *InstDesc = NULL;
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const MCOperandInfo *OpInfo = NULL;
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unsigned short NumOps = 0;
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InstDesc = MCInstrDesc_get(MCInst_getOpcode(MI), InstDescTable, tbl_size);
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OpInfo = InstDesc->OpInfo;
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NumOps = InstDesc->NumOperands;
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for (unsigned i = 0; i < NumOps; ++i) {
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if (MCOperandInfo_isTiedToOp(&OpInfo[i])) {
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int idx = MCOperandInfo_getOperandConstraint(
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InstDesc, i,
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MCOI_TIED_TO);
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if (idx == -1)
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continue;
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if (i >= MAX_MC_OPS) {
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assert(0 &&
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"Maximum number of MC operands reached.");
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}
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MI->tied_op_idx[i] = idx;
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if (MI->flat_insn->detail)
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MI->flat_insn->detail->writeback = true;
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}
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}
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}
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/// Check if operand with OpNum is tied by another operand
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/// (operand is tying destination).
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bool MCInst_opIsTied(const MCInst *MI, unsigned OpNum)
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{
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assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
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for (int i = 0; i < MAX_MC_OPS; ++i) {
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if (MI->tied_op_idx[i] == OpNum)
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return true;
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}
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return false;
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}
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/// Check if operand with OpNum is tying another operand
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/// (operand is tying src).
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bool MCInst_opIsTying(const MCInst *MI, unsigned OpNum)
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{
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assert(OpNum < MAX_MC_OPS && "Maximum number of MC operands exceeded.");
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return MI->tied_op_idx[OpNum] != -1;
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}
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/// Returns the value of the @MCInst operand at index @OpNum.
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uint64_t MCInst_getOpVal(MCInst *MI, unsigned OpNum)
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{
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assert(OpNum < MAX_MC_OPS);
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MCOperand *op = MCInst_getOperand(MI, OpNum);
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if (MCOperand_isReg(op))
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return MCOperand_getReg(op);
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else if (MCOperand_isImm(op))
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return MCOperand_getImm(op);
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else
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assert(0 && "Operand type not handled in this getter.");
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return MCOperand_getImm(op);
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}
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void MCInst_setIsAlias(MCInst *MI, bool Flag) {
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assert(MI);
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MI->isAliasInstr = Flag;
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MI->flat_insn->is_alias = Flag;
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}
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/// @brief Copies the relevant members of a temporary MCInst to
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/// the main MCInst. This is used if TryDecode was run on a temporary MCInst.
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/// @param MI The main MCInst
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/// @param TmpMI The temporary MCInst.
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void MCInst_updateWithTmpMI(MCInst *MI, MCInst *TmpMI) {
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MI->size = TmpMI->size;
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MI->Opcode = TmpMI->Opcode;
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assert(MI->size < MAX_MC_OPS);
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memcpy(MI->Operands, TmpMI->Operands, sizeof(MI->Operands[0]) * MI->size);
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}
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/// @brief Sets the softfail/illegal flag in the cs_insn.
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/// Setting it indicates the instruction can be decoded, but is invalid
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/// due to not allowed operands or an illegal context.
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///
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/// @param MI The MCInst holding the cs_insn currently decoded.
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void MCInst_setSoftFail(MCInst *MI) {
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assert(MI && MI->flat_insn);
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MI->flat_insn->illegal = true;
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}
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