00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
306 lines
9.4 KiB
C
306 lines
9.4 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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/* Rot127 <unisono@quyllur.org>, 2022-2023 */
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#ifndef CS_MAPPING_H
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#define CS_MAPPING_H
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#if defined(CAPSTONE_HAS_OSXKERNEL)
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#include <libkern/libkern.h>
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#else
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#include "include/capstone/capstone.h"
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#include <stddef.h>
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#endif
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#include "cs_priv.h"
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#include <assert.h>
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#include <string.h>
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// map instruction to its characteristics
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typedef struct insn_map {
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unsigned short id; // The LLVM instruction id
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unsigned short mapid; // The Capstone instruction id
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#ifndef CAPSTONE_DIET
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uint16_t regs_use[MAX_IMPL_R_REGS]; ///< list of implicit registers used by
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///< this instruction
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uint16_t regs_mod[MAX_IMPL_W_REGS]; ///< list of implicit registers modified
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///< by this instruction
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unsigned char groups
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[MAX_NUM_GROUPS]; ///< list of group this instruction belong to
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bool branch; // branch instruction?
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bool indirect_branch; // indirect branch instruction?
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union {
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ppc_suppl_info ppc;
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loongarch_suppl_info loongarch;
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aarch64_suppl_info aarch64;
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systemz_suppl_info systemz;
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arm_suppl_info arm;
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xtensa_suppl_info xtensa;
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sparc_suppl_info sparc;
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} suppl_info; // Supplementary information for each instruction.
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#endif
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} insn_map;
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// look for @id in @m, given its size in @max. first time call will update
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// @cache. return 0 if not found
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unsigned short insn_find(const insn_map *m, unsigned int max, unsigned int id,
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unsigned short **cache);
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unsigned int find_cs_id(unsigned MC_Opcode, const insn_map *imap,
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unsigned imap_size);
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#define MAX_NO_DATA_TYPES 16
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///< A LLVM<->CS Mapping entry of an MCOperand.
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typedef struct {
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uint8_t /* cs_op_type */ type; ///< Operand type (e.g.: reg, imm, mem)
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uint8_t /* cs_ac_type */ access; ///< The access type (read, write)
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uint8_t /* cs_data_type */
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dtypes[MAX_NO_DATA_TYPES]; ///< List of op types. Terminated by
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///< CS_DATA_TYPE_LAST
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} mapping_op;
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#define MAX_NO_INSN_MAP_OPS 16
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///< MCOperands of an instruction.
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typedef struct {
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mapping_op
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ops[MAX_NO_INSN_MAP_OPS]; ///< NULL terminated array of insn_op.
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} map_insn_ops;
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/// Only usable by `auto-sync` archs!
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const cs_op_type mapping_get_op_type(MCInst *MI, unsigned OpNum,
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const map_insn_ops *insn_ops_map,
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size_t map_size);
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/// Only usable by `auto-sync` archs!
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const cs_ac_type mapping_get_op_access(MCInst *MI, unsigned OpNum,
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const map_insn_ops *insn_ops_map,
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size_t map_size);
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/// Macro for easier access of operand types from the map.
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/// Assumes the istruction operands map is called "insn_operands"
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/// Only usable by `auto-sync` archs!
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#ifndef CAPSTONE_DIET
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#define map_get_op_type(MI, OpNum) \
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mapping_get_op_type(MI, OpNum, (const map_insn_ops *)insn_operands, \
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sizeof(insn_operands) / sizeof(insn_operands[0]))
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#else
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#define map_get_op_type(MI, OpNum) \
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CS_OP_INVALID
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#endif
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/// Macro for easier access of operand access flags from the map.
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/// Assumes the istruction operands map is called "insn_operands"
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/// Only usable by `auto-sync` archs!
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#ifndef CAPSTONE_DIET
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#define map_get_op_access(MI, OpNum) \
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mapping_get_op_access(MI, OpNum, (const map_insn_ops *)insn_operands, \
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sizeof(insn_operands) / \
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sizeof(insn_operands[0]))
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#else
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#define map_get_op_access(MI, OpNum) \
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CS_AC_INVALID
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#endif
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///< Map for ids to their string
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typedef struct name_map {
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unsigned int id;
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const char *name;
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} name_map;
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// map a name to its ID
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// return 0 if not found
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int name2id(const name_map *map, int max, const char *name);
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// map ID to a name
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// return NULL if not found
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const char *id2name(const name_map *map, int max, const unsigned int id);
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void map_add_implicit_write(MCInst *MI, uint32_t Reg);
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void map_add_implicit_read(MCInst *MI, uint32_t Reg);
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void map_remove_implicit_write(MCInst *MI, uint32_t Reg);
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void map_implicit_reads(MCInst *MI, const insn_map *imap);
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void map_implicit_writes(MCInst *MI, const insn_map *imap);
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void add_group(MCInst *MI, unsigned /* arch_group */ group);
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void map_groups(MCInst *MI, const insn_map *imap);
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void map_cs_id(MCInst *MI, const insn_map *imap, unsigned int imap_size);
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const void *map_get_suppl_info(MCInst *MI, const insn_map *imap);
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#define DECL_get_detail_op(arch, ARCH) \
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cs_##arch##_op *ARCH##_get_detail_op(MCInst *MI, int offset);
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DECL_get_detail_op(arm, ARM);
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DECL_get_detail_op(ppc, PPC);
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DECL_get_detail_op(tricore, TriCore);
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DECL_get_detail_op(aarch64, AArch64);
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DECL_get_detail_op(alpha, Alpha);
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DECL_get_detail_op(hppa, HPPA);
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DECL_get_detail_op(loongarch, LoongArch);
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DECL_get_detail_op(mips, Mips);
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DECL_get_detail_op(riscv, RISCV);
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DECL_get_detail_op(systemz, SystemZ);
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DECL_get_detail_op(xtensa, Xtensa);
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DECL_get_detail_op(bpf, BPF);
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DECL_get_detail_op(arc, ARC);
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DECL_get_detail_op(sparc, Sparc);
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/// Increments the detail->arch.op_count by one.
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#define DEFINE_inc_detail_op_count(arch, ARCH) \
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static inline void ARCH##_inc_op_count(MCInst *MI) \
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{ \
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MI->flat_insn->detail->arch.op_count++; \
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}
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/// Decrements the detail->arch.op_count by one.
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#define DEFINE_dec_detail_op_count(arch, ARCH) \
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static inline void ARCH##_dec_op_count(MCInst *MI) \
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{ \
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MI->flat_insn->detail->arch.op_count--; \
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}
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DEFINE_inc_detail_op_count(arm, ARM);
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DEFINE_dec_detail_op_count(arm, ARM);
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DEFINE_inc_detail_op_count(ppc, PPC);
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DEFINE_dec_detail_op_count(ppc, PPC);
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DEFINE_inc_detail_op_count(tricore, TriCore);
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DEFINE_dec_detail_op_count(tricore, TriCore);
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DEFINE_inc_detail_op_count(aarch64, AArch64);
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DEFINE_dec_detail_op_count(aarch64, AArch64);
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DEFINE_inc_detail_op_count(alpha, Alpha);
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DEFINE_dec_detail_op_count(alpha, Alpha);
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DEFINE_inc_detail_op_count(hppa, HPPA);
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DEFINE_dec_detail_op_count(hppa, HPPA);
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DEFINE_inc_detail_op_count(loongarch, LoongArch);
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DEFINE_dec_detail_op_count(loongarch, LoongArch);
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DEFINE_inc_detail_op_count(mips, Mips);
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DEFINE_dec_detail_op_count(mips, Mips);
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DEFINE_inc_detail_op_count(riscv, RISCV);
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DEFINE_dec_detail_op_count(riscv, RISCV);
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DEFINE_inc_detail_op_count(systemz, SystemZ);
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DEFINE_dec_detail_op_count(systemz, SystemZ);
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DEFINE_inc_detail_op_count(xtensa, Xtensa);
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DEFINE_dec_detail_op_count(xtensa, Xtensa);
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DEFINE_inc_detail_op_count(bpf, BPF);
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DEFINE_dec_detail_op_count(bpf, BPF);
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DEFINE_inc_detail_op_count(arc, ARC);
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DEFINE_dec_detail_op_count(arc, ARC);
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DEFINE_inc_detail_op_count(sparc, Sparc);
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DEFINE_dec_detail_op_count(sparc, Sparc);
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/// Returns true if a memory operand is currently edited.
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static inline bool doing_mem(const MCInst *MI)
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{
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return MI->csh->doing_mem;
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}
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/// Sets the doing_mem flag to @status.
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static inline void set_doing_mem(const MCInst *MI, bool status)
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{
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MI->csh->doing_mem = status;
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}
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/// Returns detail->arch
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#define DEFINE_get_arch_detail(arch, ARCH) \
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static inline cs_##arch *ARCH##_get_detail(const MCInst *MI) \
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{ \
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assert(MI && MI->flat_insn && MI->flat_insn->detail); \
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return &MI->flat_insn->detail->arch; \
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}
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DEFINE_get_arch_detail(arm, ARM);
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DEFINE_get_arch_detail(ppc, PPC);
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DEFINE_get_arch_detail(tricore, TriCore);
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DEFINE_get_arch_detail(aarch64, AArch64);
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DEFINE_get_arch_detail(alpha, Alpha);
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DEFINE_get_arch_detail(hppa, HPPA);
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DEFINE_get_arch_detail(loongarch, LoongArch);
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DEFINE_get_arch_detail(mips, Mips);
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DEFINE_get_arch_detail(riscv, RISCV);
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DEFINE_get_arch_detail(arc, ARC);
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DEFINE_get_arch_detail(systemz, SystemZ);
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DEFINE_get_arch_detail(xtensa, Xtensa);
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DEFINE_get_arch_detail(bpf, BPF);
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DEFINE_get_arch_detail(sparc, Sparc);
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#define DEFINE_check_safe_inc(Arch, ARCH) \
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static inline void Arch##_check_safe_inc(const MCInst *MI) { \
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assert(Arch##_get_detail(MI)->op_count + 1 < NUM_##ARCH##_OPS); \
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}
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DEFINE_check_safe_inc(ARM, ARM);
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DEFINE_check_safe_inc(PPC, PPC);
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DEFINE_check_safe_inc(TriCore, TRICORE);
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DEFINE_check_safe_inc(AArch64, AARCH64);
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DEFINE_check_safe_inc(Alpha, ALPHA);
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DEFINE_check_safe_inc(HPPA, HPPA);
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DEFINE_check_safe_inc(LoongArch, LOONGARCH);
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DEFINE_check_safe_inc(RISCV, RISCV);
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DEFINE_check_safe_inc(SystemZ, SYSTEMZ);
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DEFINE_check_safe_inc(Mips, MIPS);
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DEFINE_check_safe_inc(BPF, BPF);
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DEFINE_check_safe_inc(ARC, ARC);
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DEFINE_check_safe_inc(Sparc, SPARC);
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static inline bool detail_is_set(const MCInst *MI)
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{
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assert(MI && MI->flat_insn);
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return MI->flat_insn->detail != NULL && MI->csh->detail_opt & CS_OPT_ON;
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}
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static inline cs_detail *get_detail(const MCInst *MI)
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{
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assert(MI && MI->flat_insn);
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return MI->flat_insn->detail;
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}
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/// Returns if the given instruction is an alias instruction.
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#define RETURN_IF_INSN_IS_ALIAS(MI) \
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do { \
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if (MI->isAliasInstr) \
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return; \
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} while(0)
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void map_set_fill_detail_ops(MCInst *MI, bool Val);
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static inline bool map_fill_detail_ops(MCInst *MI) {
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assert(MI);
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return MI->fillDetailOps;
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}
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void map_set_is_alias_insn(MCInst *MI, bool Val, uint64_t Alias);
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bool map_use_alias_details(const MCInst *MI);
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void map_set_alias_id(MCInst *MI, const SStream *O, const name_map *alias_mnem_id_map, int map_size);
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/// Mapping from Capstone enumeration identifiers and their values.
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///
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/// This map MUST BE sorted to allow binary searches.
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/// Please always ensure the map is sorted after you added a value.
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///
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/// You can sort the map with Python.
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/// Copy the map into a file and run:
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///
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/// ```python
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/// with open("/tmp/file_with_map_entries") as f:
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/// text = f.readlines()
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///
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/// text.sort()
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/// print(''.join(text))
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/// ```
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typedef struct {
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const char *str; ///< The name of the enumeration identifier
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uint64_t val; ///< The value of the identifier
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} cs_enum_id_map;
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uint64_t enum_map_bin_search(const cs_enum_id_map *map, size_t map_len,
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const char *id, bool *found);
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#endif // CS_MAPPING_H
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