iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
102 lines
2.6 KiB
C
102 lines
2.6 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- ARMBaseInfo.cpp - ARM Base encoding information------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides basic encoding and assembly information for ARM.
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//
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//===----------------------------------------------------------------------===//
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#include <capstone/platform.h>
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#include "ARMBaseInfo.h"
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#include "../../utils.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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// CS namespace begin: ARMSysReg
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// lookup system register using 12-bit SYSm value.
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// Note: the search is uniqued using M1 mask
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const char *get_pred_mask(ARM_PredBlockMask pred_mask)
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{
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switch (pred_mask) {
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default:
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CS_ASSERT_RET_VAL(0 && "pred_mask not handled.", NULL);
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case ARM_T:
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return "T";
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case ARM_TT:
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return "TT";
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case ARM_TE:
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return "TE";
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case ARM_TTT:
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return "TTT";
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case ARM_TTE:
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return "TTE";
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case ARM_TEE:
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return "TEE";
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case ARM_TET:
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return "TET";
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case ARM_TTTT:
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return "TTTT";
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case ARM_TTTE:
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return "TTTE";
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case ARM_TTEE:
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return "TTEE";
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case ARM_TTET:
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return "TTET";
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case ARM_TEEE:
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return "TEEE";
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case ARM_TEET:
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return "TEET";
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case ARM_TETT:
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return "TETT";
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case ARM_TETE:
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return "TETE";
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}
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}
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#define GET_MCLASSSYSREG_IMPL
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#include "ARMGenSystemRegister.inc"
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const ARMSysReg_MClassSysReg *
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ARMSysReg_lookupMClassSysRegBy12bitSYSmValue(unsigned SYSm)
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{
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return ARMSysReg_lookupMClassSysRegByM1Encoding12(SYSm);
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}
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// returns APSR with _<bits> qualifier.
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// Note: ARMv7-M deprecates using MSR APSR without a _<bits> qualifier
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const ARMSysReg_MClassSysReg *
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ARMSysReg_lookupMClassSysRegAPSRNonDeprecated(unsigned SYSm)
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{
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return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 9) |
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(SYSm & 0xFF));
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}
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// lookup system registers using 8-bit SYSm value
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const ARMSysReg_MClassSysReg *
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ARMSysReg_lookupMClassSysRegBy8bitSYSmValue(unsigned SYSm)
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{
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return ARMSysReg_lookupMClassSysRegByM2M3Encoding8((1 << 8) |
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(SYSm & 0xFF));
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}
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