iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
6497 lines
160 KiB
C
6497 lines
160 KiB
C
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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#include <capstone/platform.h>
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#include "../../cs_priv.h"
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/// getMnemonic - This method is automatically generated by tablegen
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/// from the instruction set description.
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static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O) {
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#ifndef CAPSTONE_DIET
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static const char AsmStrs[] = {
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/* 0 */ "jiscr0\t\0"
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/* 8 */ "jiscr1\t\0"
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/* 16 */ "tail36\t\0"
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/* 24 */ "call36\t\0"
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/* 32 */ "xvreplve0.b\t\0"
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/* 45 */ "xvadda.b\t\0"
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/* 55 */ "x86sra.b\t\0"
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/* 65 */ "xvsra.b\t\0"
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/* 74 */ "amadd_db.b\t\0"
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/* 86 */ "amswap_db.b\t\0"
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/* 99 */ "amcas_db.b\t\0"
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/* 111 */ "x86sub.b\t\0"
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/* 121 */ "xvmsub.b\t\0"
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/* 131 */ "xvssub.b\t\0"
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/* 141 */ "xvsub.b\t\0"
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/* 150 */ "x86sbc.b\t\0"
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/* 160 */ "x86adc.b\t\0"
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/* 170 */ "x86dec.b\t\0"
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/* 180 */ "x86inc.b\t\0"
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/* 190 */ "vext2xv.d.b\t\0"
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/* 203 */ "x86add.b\t\0"
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/* 213 */ "amadd.b\t\0"
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/* 222 */ "xvmadd.b\t\0"
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/* 232 */ "xvsadd.b\t\0"
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/* 242 */ "xvadd.b\t\0"
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/* 251 */ "ld.b\t\0"
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/* 257 */ "x86and.b\t\0"
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/* 267 */ "xvpackod.b\t\0"
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/* 279 */ "xvpickod.b\t\0"
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/* 291 */ "xvmod.b\t\0"
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/* 300 */ "iocsrrd.b\t\0"
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/* 311 */ "xvabsd.b\t\0"
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/* 321 */ "ldle.b\t\0"
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/* 329 */ "xvsle.b\t\0"
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/* 338 */ "stle.b\t\0"
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/* 346 */ "xvreplve.b\t\0"
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/* 358 */ "xvshuf.b\t\0"
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/* 368 */ "xvneg.b\t\0"
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/* 377 */ "xvavg.b\t\0"
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/* 386 */ "xvsubwod.h.b\t\0"
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/* 400 */ "xvmaddwod.h.b\t\0"
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/* 415 */ "xvaddwod.h.b\t\0"
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/* 429 */ "xvmulwod.h.b\t\0"
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/* 443 */ "xvexth.h.b\t\0"
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/* 455 */ "xvsllwil.h.b\t\0"
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/* 469 */ "xvsubwev.h.b\t\0"
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/* 483 */ "xvmaddwev.h.b\t\0"
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/* 498 */ "xvaddwev.h.b\t\0"
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/* 512 */ "xvmulwev.h.b\t\0"
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/* 526 */ "vext2xv.h.b\t\0"
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/* 539 */ "xvhsubw.h.b\t\0"
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/* 552 */ "xvhaddw.h.b\t\0"
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/* 565 */ "xvmuh.b\t\0"
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/* 574 */ "xvilvh.b\t\0"
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/* 584 */ "xvshuf4i.b\t\0"
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/* 596 */ "x86srai.b\t\0"
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/* 607 */ "xvsrai.b\t\0"
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/* 617 */ "xvandi.b\t\0"
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/* 627 */ "xvslei.b\t\0"
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/* 637 */ "xvrepl128vei.b\t\0"
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/* 653 */ "vreplvei.b\t\0"
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/* 665 */ "x86rcli.b\t\0"
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/* 676 */ "xvbitseli.b\t\0"
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/* 689 */ "x86slli.b\t\0"
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/* 700 */ "xvslli.b\t\0"
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/* 710 */ "xvrepli.b\t\0"
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/* 721 */ "x86srli.b\t\0"
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/* 732 */ "xvsrli.b\t\0"
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/* 742 */ "x86rotli.b\t\0"
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/* 754 */ "xvmini.b\t\0"
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/* 764 */ "xvfrstpi.b\t\0"
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/* 776 */ "xvseqi.b\t\0"
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/* 786 */ "xvsrari.b\t\0"
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/* 797 */ "x86rcri.b\t\0"
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/* 808 */ "xvbitclri.b\t\0"
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/* 821 */ "xvsrlri.b\t\0"
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/* 832 */ "xvnori.b\t\0"
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/* 842 */ "xvori.b\t\0"
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/* 851 */ "xvxori.b\t\0"
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/* 861 */ "x86rotri.b\t\0"
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/* 873 */ "xvrotri.b\t\0"
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/* 884 */ "xvbitseti.b\t\0"
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/* 897 */ "xvslti.b\t\0"
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/* 907 */ "xvbitrevi.b\t\0"
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/* 920 */ "xvmaxi.b\t\0"
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/* 930 */ "x86rcl.b\t\0"
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/* 940 */ "x86sll.b\t\0"
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/* 950 */ "xvsll.b\t\0"
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/* 959 */ "xvldrepl.b\t\0"
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/* 971 */ "x86srl.b\t\0"
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/* 981 */ "xvsrl.b\t\0"
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/* 990 */ "x86rotl.b\t\0"
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/* 1001 */ "x86mul.b\t\0"
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/* 1011 */ "xvmul.b\t\0"
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/* 1020 */ "xvilvl.b\t\0"
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/* 1030 */ "xvstelm.b\t\0"
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/* 1041 */ "xvmin.b\t\0"
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/* 1050 */ "xvclo.b\t\0"
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/* 1059 */ "amswap.b\t\0"
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/* 1069 */ "xvfrstp.b\t\0"
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/* 1080 */ "xvseq.b\t\0"
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/* 1089 */ "xvsrar.b\t\0"
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/* 1099 */ "x86rcr.b\t\0"
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/* 1109 */ "vpickve2gr.b\t\0"
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/* 1123 */ "xvavgr.b\t\0"
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/* 1133 */ "xvbitclr.b\t\0"
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/* 1145 */ "xvsrlr.b\t\0"
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/* 1155 */ "x86or.b\t\0"
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/* 1164 */ "x86xor.b\t\0"
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/* 1174 */ "x86rotr.b\t\0"
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/* 1185 */ "xvrotr.b\t\0"
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/* 1195 */ "xvreplgr2vr.b\t\0"
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/* 1210 */ "vinsgr2vr.b\t\0"
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/* 1223 */ "iocsrwr.b\t\0"
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/* 1234 */ "amcas.b\t\0"
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/* 1243 */ "xvextrins.b\t\0"
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/* 1256 */ "xvsat.b\t\0"
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/* 1265 */ "xvbitset.b\t\0"
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/* 1277 */ "ldgt.b\t\0"
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/* 1285 */ "stgt.b\t\0"
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/* 1293 */ "xvslt.b\t\0"
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/* 1302 */ "xvpcnt.b\t\0"
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/* 1312 */ "st.b\t\0"
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/* 1318 */ "xvmaddwod.h.bu.b\t\0"
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/* 1336 */ "xvaddwod.h.bu.b\t\0"
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/* 1353 */ "xvmulwod.h.bu.b\t\0"
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/* 1370 */ "xvmaddwev.h.bu.b\t\0"
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/* 1388 */ "xvaddwev.h.bu.b\t\0"
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/* 1405 */ "xvmulwev.h.bu.b\t\0"
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/* 1422 */ "xvpackev.b\t\0"
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/* 1434 */ "xvpickev.b\t\0"
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/* 1446 */ "xvbitrev.b\t\0"
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/* 1458 */ "xvdiv.b\t\0"
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/* 1467 */ "xvsigncov.b\t\0"
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/* 1480 */ "ext.w.b\t\0"
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/* 1489 */ "vext2xv.w.b\t\0"
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/* 1502 */ "xvmax.b\t\0"
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/* 1511 */ "ldx.b\t\0"
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/* 1518 */ "stx.b\t\0"
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/* 1525 */ "xvmskgez.b\t\0"
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/* 1537 */ "xvsetallnez.b\t\0"
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/* 1552 */ "xvclz.b\t\0"
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/* 1561 */ "xvmsknz.b\t\0"
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/* 1572 */ "xvsetanyeqz.b\t\0"
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/* 1587 */ "xvmskltz.b\t\0"
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/* 1599 */ "bitrev.4b\t\0"
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/* 1610 */ "bitrev.8b\t\0"
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/* 1621 */ "invtlb\t\0"
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/* 1629 */ "xvreplve0.d\t\0"
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/* 1642 */ "xvinsve0.d\t\0"
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/* 1654 */ "xvadda.d\t\0"
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/* 1664 */ "xvfmina.d\t\0"
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/* 1675 */ "x86sra.d\t\0"
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/* 1685 */ "xvsra.d\t\0"
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/* 1694 */ "xvfmaxa.d\t\0"
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/* 1705 */ "amadd_db.d\t\0"
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/* 1717 */ "amand_db.d\t\0"
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/* 1729 */ "ammin_db.d\t\0"
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/* 1741 */ "amswap_db.d\t\0"
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/* 1754 */ "amor_db.d\t\0"
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/* 1765 */ "amxor_db.d\t\0"
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/* 1777 */ "amcas_db.d\t\0"
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/* 1789 */ "ammax_db.d\t\0"
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/* 1801 */ "fscaleb.d\t\0"
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/* 1812 */ "xvflogb.d\t\0"
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/* 1823 */ "x86sub.d\t\0"
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/* 1833 */ "xvfsub.d\t\0"
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/* 1843 */ "xvfmsub.d\t\0"
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/* 1854 */ "xvfnmsub.d\t\0"
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/* 1866 */ "xvmsub.d\t\0"
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/* 1876 */ "xvssub.d\t\0"
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/* 1886 */ "xvsub.d\t\0"
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/* 1895 */ "revb.d\t\0"
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/* 1903 */ "x86sbc.d\t\0"
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/* 1913 */ "x86adc.d\t\0"
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/* 1923 */ "x86dec.d\t\0"
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/* 1933 */ "x86inc.d\t\0"
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/* 1943 */ "sc.d\t\0"
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/* 1949 */ "x86add.d\t\0"
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/* 1959 */ "xvfadd.d\t\0"
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/* 1969 */ "amadd.d\t\0"
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/* 1978 */ "xvfmadd.d\t\0"
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/* 1989 */ "xvfnmadd.d\t\0"
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/* 2001 */ "xvmadd.d\t\0"
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/* 2011 */ "xvsadd.d\t\0"
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/* 2021 */ "xvadd.d\t\0"
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/* 2030 */ "fcvt.ld.d\t\0"
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/* 2041 */ "fld.d\t\0"
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/* 2048 */ "x86and.d\t\0"
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/* 2058 */ "amand.d\t\0"
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/* 2067 */ "xvpackod.d\t\0"
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/* 2079 */ "xvpickod.d\t\0"
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/* 2091 */ "xvmod.d\t\0"
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/* 2100 */ "iocsrrd.d\t\0"
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/* 2111 */ "xvabsd.d\t\0"
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/* 2121 */ "fcvt.ud.d\t\0"
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/* 2132 */ "xvfcmp.cle.d\t\0"
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/* 2146 */ "fldle.d\t\0"
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/* 2155 */ "xvfcmp.sle.d\t\0"
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/* 2169 */ "xvsle.d\t\0"
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/* 2178 */ "asrtle.d\t\0"
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/* 2188 */ "fstle.d\t\0"
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/* 2197 */ "xvfcmp.cule.d\t\0"
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/* 2212 */ "xvfcmp.sule.d\t\0"
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/* 2227 */ "rdtime.d\t\0"
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/* 2237 */ "xvfcmp.cne.d\t\0"
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/* 2251 */ "xvfrintrne.d\t\0"
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/* 2265 */ "xvfcmp.sne.d\t\0"
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/* 2279 */ "xvfcmp.cune.d\t\0"
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/* 2294 */ "xvfcmp.sune.d\t\0"
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/* 2309 */ "xvfrecipe.d\t\0"
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/* 2322 */ "xvfrsqrte.d\t\0"
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/* 2335 */ "xvpickve.d\t\0"
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/* 2347 */ "xvreplve.d\t\0"
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/* 2359 */ "xvfcmp.caf.d\t\0"
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/* 2373 */ "xvfcmp.saf.d\t\0"
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/* 2387 */ "xvshuf.d\t\0"
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/* 2397 */ "fneg.d\t\0"
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/* 2405 */ "xvneg.d\t\0"
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/* 2414 */ "xvavg.d\t\0"
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/* 2423 */ "mulh.d\t\0"
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/* 2431 */ "xvmuh.d\t\0"
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/* 2440 */ "revh.d\t\0"
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/* 2448 */ "xvilvh.d\t\0"
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/* 2458 */ "addu12i.d\t\0"
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/* 2469 */ "lu32i.d\t\0"
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/* 2478 */ "lu52i.d\t\0"
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/* 2487 */ "xvshuf4i.d\t\0"
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/* 2499 */ "addu16i.d\t\0"
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/* 2510 */ "x86srai.d\t\0"
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/* 2521 */ "xvsrai.d\t\0"
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/* 2531 */ "addi.d\t\0"
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/* 2539 */ "xvslei.d\t\0"
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/* 2549 */ "xvrepl128vei.d\t\0"
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/* 2565 */ "vreplvei.d\t\0"
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/* 2577 */ "x86rcli.d\t\0"
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/* 2588 */ "xvhseli.d\t\0"
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/* 2599 */ "x86slli.d\t\0"
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/* 2610 */ "xvslli.d\t\0"
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/* 2620 */ "xvrepli.d\t\0"
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/* 2631 */ "x86srli.d\t\0"
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/* 2642 */ "xvsrli.d\t\0"
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/* 2652 */ "x86rotli.d\t\0"
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/* 2664 */ "xvpermi.d\t\0"
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/* 2675 */ "xvmini.d\t\0"
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/* 2685 */ "xvseqi.d\t\0"
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/* 2695 */ "xvsrari.d\t\0"
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/* 2706 */ "x86rcri.d\t\0"
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/* 2717 */ "xvbitclri.d\t\0"
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/* 2730 */ "xvsrlri.d\t\0"
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/* 2741 */ "x86rotri.d\t\0"
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/* 2753 */ "xvrotri.d\t\0"
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/* 2764 */ "xvbitseti.d\t\0"
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/* 2777 */ "xvslti.d\t\0"
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|
/* 2787 */ "xvbitrevi.d\t\0"
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|
/* 2800 */ "xvmaxi.d\t\0"
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|
/* 2810 */ "bytepick.d\t\0"
|
|
/* 2822 */ "bstrpick.d\t\0"
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|
/* 2834 */ "xvftintrne.l.d\t\0"
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|
/* 2850 */ "xvftintrm.l.d\t\0"
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|
/* 2865 */ "xvftintrp.l.d\t\0"
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|
/* 2880 */ "xvftint.l.d\t\0"
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|
/* 2893 */ "xvftintrz.l.d\t\0"
|
|
/* 2908 */ "x86rcl.d\t\0"
|
|
/* 2918 */ "ldl.d\t\0"
|
|
/* 2925 */ "screl.d\t\0"
|
|
/* 2934 */ "x86sll.d\t\0"
|
|
/* 2944 */ "xvsll.d\t\0"
|
|
/* 2953 */ "xvldrepl.d\t\0"
|
|
/* 2965 */ "x86srl.d\t\0"
|
|
/* 2975 */ "xvsrl.d\t\0"
|
|
/* 2984 */ "alsl.d\t\0"
|
|
/* 2992 */ "x86rotl.d\t\0"
|
|
/* 3003 */ "stl.d\t\0"
|
|
/* 3010 */ "x86mul.d\t\0"
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|
/* 3020 */ "xvfmul.d\t\0"
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|
/* 3030 */ "xvmul.d\t\0"
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|
/* 3039 */ "xvilvl.d\t\0"
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|
/* 3049 */ "xvstelm.d\t\0"
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|
/* 3060 */ "xvfrintrm.d\t\0"
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|
/* 3073 */ "fcopysign.d\t\0"
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|
/* 3086 */ "xvfmin.d\t\0"
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|
/* 3096 */ "ammin.d\t\0"
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|
/* 3105 */ "xvmin.d\t\0"
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|
/* 3114 */ "xvfcmp.cun.d\t\0"
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|
/* 3128 */ "xvfcmp.sun.d\t\0"
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|
/* 3142 */ "xvclo.d\t\0"
|
|
/* 3151 */ "cto.d\t\0"
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|
/* 3158 */ "amswap.d\t\0"
|
|
/* 3168 */ "xvfrecip.d\t\0"
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|
/* 3180 */ "xvfrintrp.d\t\0"
|
|
/* 3193 */ "xvsubwod.q.d\t\0"
|
|
/* 3207 */ "xvmaddwod.q.d\t\0"
|
|
/* 3222 */ "xvaddwod.q.d\t\0"
|
|
/* 3236 */ "xvmulwod.q.d\t\0"
|
|
/* 3250 */ "xvexth.q.d\t\0"
|
|
/* 3262 */ "xvextl.q.d\t\0"
|
|
/* 3274 */ "xvsubwev.q.d\t\0"
|
|
/* 3288 */ "xvmaddwev.q.d\t\0"
|
|
/* 3303 */ "xvaddwev.q.d\t\0"
|
|
/* 3317 */ "xvmulwev.q.d\t\0"
|
|
/* 3331 */ "xvhsubw.q.d\t\0"
|
|
/* 3344 */ "xvhaddw.q.d\t\0"
|
|
/* 3357 */ "llacq.d\t\0"
|
|
/* 3366 */ "xvfcmp.ceq.d\t\0"
|
|
/* 3380 */ "xvfcmp.seq.d\t\0"
|
|
/* 3394 */ "xvseq.d\t\0"
|
|
/* 3403 */ "xvfcmp.cueq.d\t\0"
|
|
/* 3418 */ "xvfcmp.sueq.d\t\0"
|
|
/* 3433 */ "xvsrar.d\t\0"
|
|
/* 3443 */ "x86rcr.d\t\0"
|
|
/* 3453 */ "ldr.d\t\0"
|
|
/* 3460 */ "movgr2fr.d\t\0"
|
|
/* 3472 */ "xvpickve2gr.d\t\0"
|
|
/* 3487 */ "movfr2gr.d\t\0"
|
|
/* 3499 */ "xvavgr.d\t\0"
|
|
/* 3509 */ "xvbitclr.d\t\0"
|
|
/* 3521 */ "xvsrlr.d\t\0"
|
|
/* 3531 */ "x86or.d\t\0"
|
|
/* 3540 */ "xvfcmp.cor.d\t\0"
|
|
/* 3554 */ "amor.d\t\0"
|
|
/* 3562 */ "xvfcmp.sor.d\t\0"
|
|
/* 3576 */ "x86xor.d\t\0"
|
|
/* 3586 */ "amxor.d\t\0"
|
|
/* 3595 */ "x86rotr.d\t\0"
|
|
/* 3606 */ "xvrotr.d\t\0"
|
|
/* 3616 */ "ldptr.d\t\0"
|
|
/* 3625 */ "stptr.d\t\0"
|
|
/* 3634 */ "str.d\t\0"
|
|
/* 3641 */ "xvreplgr2vr.d\t\0"
|
|
/* 3656 */ "xvinsgr2vr.d\t\0"
|
|
/* 3670 */ "iocsrwr.d\t\0"
|
|
/* 3681 */ "xvfcvt.s.d\t\0"
|
|
/* 3693 */ "amcas.d\t\0"
|
|
/* 3702 */ "fabs.d\t\0"
|
|
/* 3710 */ "bstrins.d\t\0"
|
|
/* 3721 */ "xvextrins.d\t\0"
|
|
/* 3734 */ "xvfclass.d\t\0"
|
|
/* 3746 */ "xvsat.d\t\0"
|
|
/* 3755 */ "xvbitset.d\t\0"
|
|
/* 3767 */ "fldgt.d\t\0"
|
|
/* 3776 */ "asrtgt.d\t\0"
|
|
/* 3786 */ "fstgt.d\t\0"
|
|
/* 3795 */ "xvfcmp.clt.d\t\0"
|
|
/* 3809 */ "xvfcmp.slt.d\t\0"
|
|
/* 3823 */ "xvslt.d\t\0"
|
|
/* 3832 */ "xvfcmp.cult.d\t\0"
|
|
/* 3847 */ "xvfcmp.sult.d\t\0"
|
|
/* 3862 */ "xvpcnt.d\t\0"
|
|
/* 3872 */ "xvfrint.d\t\0"
|
|
/* 3883 */ "xvfsqrt.d\t\0"
|
|
/* 3894 */ "xvfrsqrt.d\t\0"
|
|
/* 3906 */ "fst.d\t\0"
|
|
/* 3913 */ "xvmaddwod.q.du.d\t\0"
|
|
/* 3931 */ "xvaddwod.q.du.d\t\0"
|
|
/* 3948 */ "xvmulwod.q.du.d\t\0"
|
|
/* 3965 */ "xvmaddwev.q.du.d\t\0"
|
|
/* 3983 */ "xvaddwev.q.du.d\t\0"
|
|
/* 4000 */ "xvmulwev.q.du.d\t\0"
|
|
/* 4017 */ "xvftint.lu.d\t\0"
|
|
/* 4031 */ "xvftintrz.lu.d\t\0"
|
|
/* 4047 */ "xvssrani.wu.d\t\0"
|
|
/* 4062 */ "xvssrlni.wu.d\t\0"
|
|
/* 4077 */ "xvssrarni.wu.d\t\0"
|
|
/* 4093 */ "xvssrlrni.wu.d\t\0"
|
|
/* 4109 */ "xvssran.wu.d\t\0"
|
|
/* 4123 */ "xvssrln.wu.d\t\0"
|
|
/* 4137 */ "xvssrarn.wu.d\t\0"
|
|
/* 4152 */ "xvssrlrn.wu.d\t\0"
|
|
/* 4167 */ "xvpackev.d\t\0"
|
|
/* 4179 */ "xvpickev.d\t\0"
|
|
/* 4191 */ "xvbitrev.d\t\0"
|
|
/* 4203 */ "xvfdiv.d\t\0"
|
|
/* 4213 */ "xvdiv.d\t\0"
|
|
/* 4222 */ "xvsigncov.d\t\0"
|
|
/* 4235 */ "fmov.d\t\0"
|
|
/* 4243 */ "armmov.d\t\0"
|
|
/* 4253 */ "xvftintrne.w.d\t\0"
|
|
/* 4269 */ "xvssrani.w.d\t\0"
|
|
/* 4283 */ "xvsrani.w.d\t\0"
|
|
/* 4296 */ "xvssrlni.w.d\t\0"
|
|
/* 4310 */ "xvsrlni.w.d\t\0"
|
|
/* 4323 */ "xvssrarni.w.d\t\0"
|
|
/* 4338 */ "xvsrarni.w.d\t\0"
|
|
/* 4352 */ "xvssrlrni.w.d\t\0"
|
|
/* 4367 */ "xvsrlrni.w.d\t\0"
|
|
/* 4381 */ "xvftintrm.w.d\t\0"
|
|
/* 4396 */ "xvssran.w.d\t\0"
|
|
/* 4409 */ "xvsran.w.d\t\0"
|
|
/* 4421 */ "xvssrln.w.d\t\0"
|
|
/* 4434 */ "xvsrln.w.d\t\0"
|
|
/* 4446 */ "xvssrarn.w.d\t\0"
|
|
/* 4460 */ "xvsrarn.w.d\t\0"
|
|
/* 4473 */ "xvssrlrn.w.d\t\0"
|
|
/* 4487 */ "xvsrlrn.w.d\t\0"
|
|
/* 4500 */ "xvftintrp.w.d\t\0"
|
|
/* 4515 */ "xvftint.w.d\t\0"
|
|
/* 4528 */ "xvftintrz.w.d\t\0"
|
|
/* 4543 */ "xvfmax.d\t\0"
|
|
/* 4553 */ "ammax.d\t\0"
|
|
/* 4562 */ "xvmax.d\t\0"
|
|
/* 4571 */ "fldx.d\t\0"
|
|
/* 4579 */ "fstx.d\t\0"
|
|
/* 4587 */ "xvsetallnez.d\t\0"
|
|
/* 4602 */ "xvclz.d\t\0"
|
|
/* 4611 */ "xvsetanyeqz.d\t\0"
|
|
/* 4626 */ "xvfrintrz.d\t\0"
|
|
/* 4639 */ "ctz.d\t\0"
|
|
/* 4646 */ "xvmskltz.d\t\0"
|
|
/* 4658 */ "la.tls.gd\t\0"
|
|
/* 4669 */ "fcvt.d.ld\t\0"
|
|
/* 4680 */ "la.tls.ld\t\0"
|
|
/* 4691 */ "preld\t\0"
|
|
/* 4698 */ "xvld\t\0"
|
|
/* 4704 */ "and\t\0"
|
|
/* 4709 */ "tlbrd\t\0"
|
|
/* 4716 */ "gcsrrd\t\0"
|
|
/* 4724 */ "bge\t\0"
|
|
/* 4729 */ "la.tls.ie\t\0"
|
|
/* 4740 */ "la.tls.le\t\0"
|
|
/* 4751 */ "idle\t\0"
|
|
/* 4757 */ "bne\t\0"
|
|
/* 4762 */ "setx86loopne\t\0"
|
|
/* 4776 */ "setx86loope\t\0"
|
|
/* 4789 */ "ldpte\t\0"
|
|
/* 4796 */ "armmove\t\0"
|
|
/* 4805 */ "movfr2cf\t\0"
|
|
/* 4815 */ "movgr2cf\t\0"
|
|
/* 4825 */ "x86mfflag\t\0"
|
|
/* 4836 */ "armmfflag\t\0"
|
|
/* 4847 */ "x86mtflag\t\0"
|
|
/* 4858 */ "armmtflag\t\0"
|
|
/* 4869 */ "x86settag\t\0"
|
|
/* 4880 */ "cpucfg\t\0"
|
|
/* 4888 */ "gcsrxchg\t\0"
|
|
/* 4898 */ "xvreplve0.h\t\0"
|
|
/* 4911 */ "xvadda.h\t\0"
|
|
/* 4921 */ "x86sra.h\t\0"
|
|
/* 4931 */ "xvsra.h\t\0"
|
|
/* 4940 */ "xvssrani.b.h\t\0"
|
|
/* 4954 */ "xvsrani.b.h\t\0"
|
|
/* 4967 */ "xvssrlni.b.h\t\0"
|
|
/* 4981 */ "xvsrlni.b.h\t\0"
|
|
/* 4994 */ "xvssrarni.b.h\t\0"
|
|
/* 5009 */ "xvsrarni.b.h\t\0"
|
|
/* 5023 */ "xvssrlrni.b.h\t\0"
|
|
/* 5038 */ "xvsrlrni.b.h\t\0"
|
|
/* 5052 */ "xvssran.b.h\t\0"
|
|
/* 5065 */ "xvsran.b.h\t\0"
|
|
/* 5077 */ "xvssrln.b.h\t\0"
|
|
/* 5090 */ "xvsrln.b.h\t\0"
|
|
/* 5102 */ "xvssrarn.b.h\t\0"
|
|
/* 5116 */ "xvsrarn.b.h\t\0"
|
|
/* 5129 */ "xvssrlrn.b.h\t\0"
|
|
/* 5143 */ "xvsrlrn.b.h\t\0"
|
|
/* 5156 */ "amadd_db.h\t\0"
|
|
/* 5168 */ "amswap_db.h\t\0"
|
|
/* 5181 */ "amcas_db.h\t\0"
|
|
/* 5193 */ "x86sub.h\t\0"
|
|
/* 5203 */ "xvmsub.h\t\0"
|
|
/* 5213 */ "xvssub.h\t\0"
|
|
/* 5223 */ "xvsub.h\t\0"
|
|
/* 5232 */ "x86sbc.h\t\0"
|
|
/* 5242 */ "x86adc.h\t\0"
|
|
/* 5252 */ "x86dec.h\t\0"
|
|
/* 5262 */ "x86inc.h\t\0"
|
|
/* 5272 */ "vext2xv.d.h\t\0"
|
|
/* 5285 */ "x86add.h\t\0"
|
|
/* 5295 */ "amadd.h\t\0"
|
|
/* 5304 */ "xvmadd.h\t\0"
|
|
/* 5314 */ "xvsadd.h\t\0"
|
|
/* 5324 */ "xvadd.h\t\0"
|
|
/* 5333 */ "ld.h\t\0"
|
|
/* 5339 */ "x86and.h\t\0"
|
|
/* 5349 */ "xvpackod.h\t\0"
|
|
/* 5361 */ "xvpickod.h\t\0"
|
|
/* 5373 */ "xvmod.h\t\0"
|
|
/* 5382 */ "iocsrrd.h\t\0"
|
|
/* 5393 */ "xvabsd.h\t\0"
|
|
/* 5403 */ "ldle.h\t\0"
|
|
/* 5411 */ "xvsle.h\t\0"
|
|
/* 5420 */ "stle.h\t\0"
|
|
/* 5428 */ "xvreplve.h\t\0"
|
|
/* 5440 */ "xvshuf.h\t\0"
|
|
/* 5450 */ "xvneg.h\t\0"
|
|
/* 5459 */ "xvavg.h\t\0"
|
|
/* 5468 */ "xvmuh.h\t\0"
|
|
/* 5477 */ "xvilvh.h\t\0"
|
|
/* 5487 */ "xvshuf4i.h\t\0"
|
|
/* 5499 */ "x86srai.h\t\0"
|
|
/* 5510 */ "xvsrai.h\t\0"
|
|
/* 5520 */ "xvslei.h\t\0"
|
|
/* 5530 */ "xvrepl128vei.h\t\0"
|
|
/* 5546 */ "vreplvei.h\t\0"
|
|
/* 5558 */ "x86rcli.h\t\0"
|
|
/* 5569 */ "x86slli.h\t\0"
|
|
/* 5580 */ "xvslli.h\t\0"
|
|
/* 5590 */ "xvrepli.h\t\0"
|
|
/* 5601 */ "x86srli.h\t\0"
|
|
/* 5612 */ "xvsrli.h\t\0"
|
|
/* 5622 */ "x86rotli.h\t\0"
|
|
/* 5634 */ "xvmini.h\t\0"
|
|
/* 5644 */ "xvfrstpi.h\t\0"
|
|
/* 5656 */ "xvseqi.h\t\0"
|
|
/* 5666 */ "xvsrari.h\t\0"
|
|
/* 5677 */ "x86rcri.h\t\0"
|
|
/* 5688 */ "xvbitclri.h\t\0"
|
|
/* 5701 */ "xvsrlri.h\t\0"
|
|
/* 5712 */ "x86rotri.h\t\0"
|
|
/* 5724 */ "xvrotri.h\t\0"
|
|
/* 5735 */ "xvbitseti.h\t\0"
|
|
/* 5748 */ "xvslti.h\t\0"
|
|
/* 5758 */ "xvbitrevi.h\t\0"
|
|
/* 5771 */ "xvmaxi.h\t\0"
|
|
/* 5781 */ "x86rcl.h\t\0"
|
|
/* 5791 */ "x86sll.h\t\0"
|
|
/* 5801 */ "xvsll.h\t\0"
|
|
/* 5810 */ "xvldrepl.h\t\0"
|
|
/* 5822 */ "x86srl.h\t\0"
|
|
/* 5832 */ "xvsrl.h\t\0"
|
|
/* 5841 */ "x86rotl.h\t\0"
|
|
/* 5852 */ "x86mul.h\t\0"
|
|
/* 5862 */ "xvmul.h\t\0"
|
|
/* 5871 */ "xvilvl.h\t\0"
|
|
/* 5881 */ "xvstelm.h\t\0"
|
|
/* 5892 */ "xvmin.h\t\0"
|
|
/* 5901 */ "xvclo.h\t\0"
|
|
/* 5910 */ "amswap.h\t\0"
|
|
/* 5920 */ "xvfrstp.h\t\0"
|
|
/* 5931 */ "xvseq.h\t\0"
|
|
/* 5940 */ "xvsrar.h\t\0"
|
|
/* 5950 */ "x86rcr.h\t\0"
|
|
/* 5960 */ "vpickve2gr.h\t\0"
|
|
/* 5974 */ "xvavgr.h\t\0"
|
|
/* 5984 */ "xvbitclr.h\t\0"
|
|
/* 5996 */ "xvsrlr.h\t\0"
|
|
/* 6006 */ "x86or.h\t\0"
|
|
/* 6015 */ "x86xor.h\t\0"
|
|
/* 6025 */ "x86rotr.h\t\0"
|
|
/* 6036 */ "xvrotr.h\t\0"
|
|
/* 6046 */ "xvreplgr2vr.h\t\0"
|
|
/* 6061 */ "vinsgr2vr.h\t\0"
|
|
/* 6074 */ "iocsrwr.h\t\0"
|
|
/* 6085 */ "xvfcvth.s.h\t\0"
|
|
/* 6098 */ "xvfcvtl.s.h\t\0"
|
|
/* 6111 */ "amcas.h\t\0"
|
|
/* 6120 */ "xvextrins.h\t\0"
|
|
/* 6133 */ "xvsat.h\t\0"
|
|
/* 6142 */ "xvbitset.h\t\0"
|
|
/* 6154 */ "ldgt.h\t\0"
|
|
/* 6162 */ "stgt.h\t\0"
|
|
/* 6170 */ "xvslt.h\t\0"
|
|
/* 6179 */ "xvpcnt.h\t\0"
|
|
/* 6189 */ "st.h\t\0"
|
|
/* 6195 */ "xvssrani.bu.h\t\0"
|
|
/* 6210 */ "xvssrlni.bu.h\t\0"
|
|
/* 6225 */ "xvssrarni.bu.h\t\0"
|
|
/* 6241 */ "xvssrlrni.bu.h\t\0"
|
|
/* 6257 */ "xvssran.bu.h\t\0"
|
|
/* 6271 */ "xvssrln.bu.h\t\0"
|
|
/* 6285 */ "xvssrarn.bu.h\t\0"
|
|
/* 6300 */ "xvssrlrn.bu.h\t\0"
|
|
/* 6315 */ "xvmaddwod.w.hu.h\t\0"
|
|
/* 6333 */ "xvaddwod.w.hu.h\t\0"
|
|
/* 6350 */ "xvmulwod.w.hu.h\t\0"
|
|
/* 6367 */ "xvmaddwev.w.hu.h\t\0"
|
|
/* 6385 */ "xvaddwev.w.hu.h\t\0"
|
|
/* 6402 */ "xvmulwev.w.hu.h\t\0"
|
|
/* 6419 */ "xvpackev.h\t\0"
|
|
/* 6431 */ "xvpickev.h\t\0"
|
|
/* 6443 */ "xvbitrev.h\t\0"
|
|
/* 6455 */ "xvdiv.h\t\0"
|
|
/* 6464 */ "xvsigncov.h\t\0"
|
|
/* 6477 */ "xvsubwod.w.h\t\0"
|
|
/* 6491 */ "xvmaddwod.w.h\t\0"
|
|
/* 6506 */ "xvaddwod.w.h\t\0"
|
|
/* 6520 */ "xvmulwod.w.h\t\0"
|
|
/* 6534 */ "xvexth.w.h\t\0"
|
|
/* 6546 */ "xvsllwil.w.h\t\0"
|
|
/* 6560 */ "ext.w.h\t\0"
|
|
/* 6569 */ "xvsubwev.w.h\t\0"
|
|
/* 6583 */ "xvmaddwev.w.h\t\0"
|
|
/* 6598 */ "xvaddwev.w.h\t\0"
|
|
/* 6612 */ "xvmulwev.w.h\t\0"
|
|
/* 6626 */ "vext2xv.w.h\t\0"
|
|
/* 6639 */ "xvhsubw.w.h\t\0"
|
|
/* 6652 */ "xvhaddw.w.h\t\0"
|
|
/* 6665 */ "xvmax.h\t\0"
|
|
/* 6674 */ "ldx.h\t\0"
|
|
/* 6681 */ "stx.h\t\0"
|
|
/* 6688 */ "xvsetallnez.h\t\0"
|
|
/* 6703 */ "xvclz.h\t\0"
|
|
/* 6712 */ "xvsetanyeqz.h\t\0"
|
|
/* 6727 */ "xvmskltz.h\t\0"
|
|
/* 6739 */ "revb.2h\t\0"
|
|
/* 6748 */ "revb.4h\t\0"
|
|
/* 6757 */ "tlbsrch\t\0"
|
|
/* 6766 */ "gtlbflush\t\0"
|
|
/* 6777 */ "pcalau12i\t\0"
|
|
/* 6788 */ "pcaddu12i\t\0"
|
|
/* 6799 */ "pcaddu18i\t\0"
|
|
/* 6810 */ "pcaddi\t\0"
|
|
/* 6818 */ "xvldi\t\0"
|
|
/* 6825 */ "andi\t\0"
|
|
/* 6831 */ "xori\t\0"
|
|
/* 6837 */ "slti\t\0"
|
|
/* 6843 */ "sltui\t\0"
|
|
/* 6850 */ "setx86j\t\0"
|
|
/* 6859 */ "setarmj\t\0"
|
|
/* 6868 */ "break\t\0"
|
|
/* 6875 */ "xvffint.d.l\t\0"
|
|
/* 6888 */ "xvffint.s.l\t\0"
|
|
/* 6901 */ "bl\t\0"
|
|
/* 6905 */ "dbcl\t\0"
|
|
/* 6911 */ "hvcl\t\0"
|
|
/* 6917 */ "la.pcrel\t\0"
|
|
/* 6927 */ "fsel\t\0"
|
|
/* 6933 */ "syscall\t\0"
|
|
/* 6942 */ "tlbfill\t\0"
|
|
/* 6951 */ "jirl\t\0"
|
|
/* 6957 */ "x86clrtm\t\0"
|
|
/* 6967 */ "x86settm\t\0"
|
|
/* 6977 */ "andn\t\0"
|
|
/* 6983 */ "orn\t\0"
|
|
/* 6988 */ "ertn\t\0"
|
|
/* 6994 */ "cacop\t\0"
|
|
/* 7001 */ "x86dectop\t\0"
|
|
/* 7012 */ "x86inctop\t\0"
|
|
/* 7023 */ "x86mftop\t\0"
|
|
/* 7033 */ "x86mttop\t\0"
|
|
/* 7043 */ "xvreplve0.q\t\0"
|
|
/* 7056 */ "xvsub.q\t\0"
|
|
/* 7065 */ "sc.q\t\0"
|
|
/* 7071 */ "xvssrani.d.q\t\0"
|
|
/* 7085 */ "xvsrani.d.q\t\0"
|
|
/* 7098 */ "xvssrlni.d.q\t\0"
|
|
/* 7112 */ "xvsrlni.d.q\t\0"
|
|
/* 7125 */ "xvssrarni.d.q\t\0"
|
|
/* 7140 */ "xvsrarni.d.q\t\0"
|
|
/* 7154 */ "xvssrlrni.d.q\t\0"
|
|
/* 7169 */ "xvsrlrni.d.q\t\0"
|
|
/* 7183 */ "xvadd.q\t\0"
|
|
/* 7192 */ "xvpermi.q\t\0"
|
|
/* 7203 */ "xvssrani.du.q\t\0"
|
|
/* 7218 */ "xvssrlni.du.q\t\0"
|
|
/* 7233 */ "xvssrarni.du.q\t\0"
|
|
/* 7249 */ "xvssrlrni.du.q\t\0"
|
|
/* 7265 */ "beq\t\0"
|
|
/* 7270 */ "dbar\t\0"
|
|
/* 7276 */ "ibar\t\0"
|
|
/* 7282 */ "movgr2scr\t\0"
|
|
/* 7293 */ "movcf2fr\t\0"
|
|
/* 7303 */ "movcf2gr\t\0"
|
|
/* 7313 */ "movscr2gr\t\0"
|
|
/* 7324 */ "movfcsr2gr\t\0"
|
|
/* 7336 */ "lddir\t\0"
|
|
/* 7343 */ "tlbclr\t\0"
|
|
/* 7351 */ "nor\t\0"
|
|
/* 7356 */ "xor\t\0"
|
|
/* 7361 */ "movgr2fcsr\t\0"
|
|
/* 7373 */ "tlbwr\t\0"
|
|
/* 7380 */ "gcsrwr\t\0"
|
|
/* 7388 */ "xvfmina.s\t\0"
|
|
/* 7399 */ "xvfmaxa.s\t\0"
|
|
/* 7410 */ "fscaleb.s\t\0"
|
|
/* 7421 */ "xvflogb.s\t\0"
|
|
/* 7432 */ "xvfsub.s\t\0"
|
|
/* 7442 */ "xvfmsub.s\t\0"
|
|
/* 7453 */ "xvfnmsub.s\t\0"
|
|
/* 7465 */ "xvfcvth.d.s\t\0"
|
|
/* 7478 */ "xvfcvtl.d.s\t\0"
|
|
/* 7491 */ "fcvt.d.s\t\0"
|
|
/* 7501 */ "xvfadd.s\t\0"
|
|
/* 7511 */ "xvfmadd.s\t\0"
|
|
/* 7522 */ "xvfnmadd.s\t\0"
|
|
/* 7534 */ "fld.s\t\0"
|
|
/* 7541 */ "xvfcmp.cle.s\t\0"
|
|
/* 7555 */ "fldle.s\t\0"
|
|
/* 7564 */ "xvfcmp.sle.s\t\0"
|
|
/* 7578 */ "fstle.s\t\0"
|
|
/* 7587 */ "xvfcmp.cule.s\t\0"
|
|
/* 7602 */ "xvfcmp.sule.s\t\0"
|
|
/* 7617 */ "xvfcmp.cne.s\t\0"
|
|
/* 7631 */ "xvfrintrne.s\t\0"
|
|
/* 7645 */ "xvfcmp.sne.s\t\0"
|
|
/* 7659 */ "xvfcmp.cune.s\t\0"
|
|
/* 7674 */ "xvfcmp.sune.s\t\0"
|
|
/* 7689 */ "xvfrecipe.s\t\0"
|
|
/* 7702 */ "xvfrsqrte.s\t\0"
|
|
/* 7715 */ "xvfcmp.caf.s\t\0"
|
|
/* 7729 */ "xvfcmp.saf.s\t\0"
|
|
/* 7743 */ "fneg.s\t\0"
|
|
/* 7751 */ "xvfcvt.h.s\t\0"
|
|
/* 7763 */ "ftintrne.l.s\t\0"
|
|
/* 7777 */ "xvftintrneh.l.s\t\0"
|
|
/* 7794 */ "xvftintrmh.l.s\t\0"
|
|
/* 7810 */ "xvftintrph.l.s\t\0"
|
|
/* 7826 */ "xvftinth.l.s\t\0"
|
|
/* 7840 */ "xvftintrzh.l.s\t\0"
|
|
/* 7856 */ "xvftintrnel.l.s\t\0"
|
|
/* 7873 */ "xvftintrml.l.s\t\0"
|
|
/* 7889 */ "xvftintrpl.l.s\t\0"
|
|
/* 7905 */ "xvftintl.l.s\t\0"
|
|
/* 7919 */ "xvftintrzl.l.s\t\0"
|
|
/* 7935 */ "ftintrm.l.s\t\0"
|
|
/* 7948 */ "ftintrp.l.s\t\0"
|
|
/* 7961 */ "ftint.l.s\t\0"
|
|
/* 7972 */ "ftintrz.l.s\t\0"
|
|
/* 7985 */ "xvfmul.s\t\0"
|
|
/* 7995 */ "xvfrintrm.s\t\0"
|
|
/* 8008 */ "fcopysign.s\t\0"
|
|
/* 8021 */ "xvfmin.s\t\0"
|
|
/* 8031 */ "xvfcmp.cun.s\t\0"
|
|
/* 8045 */ "xvfcmp.sun.s\t\0"
|
|
/* 8059 */ "xvfrecip.s\t\0"
|
|
/* 8071 */ "xvfrintrp.s\t\0"
|
|
/* 8084 */ "xvfcmp.ceq.s\t\0"
|
|
/* 8098 */ "xvfcmp.seq.s\t\0"
|
|
/* 8112 */ "xvfcmp.cueq.s\t\0"
|
|
/* 8127 */ "xvfcmp.sueq.s\t\0"
|
|
/* 8142 */ "movfrh2gr.s\t\0"
|
|
/* 8155 */ "movfr2gr.s\t\0"
|
|
/* 8167 */ "xvfcmp.cor.s\t\0"
|
|
/* 8181 */ "xvfcmp.sor.s\t\0"
|
|
/* 8195 */ "fabs.s\t\0"
|
|
/* 8203 */ "xvfclass.s\t\0"
|
|
/* 8215 */ "fldgt.s\t\0"
|
|
/* 8224 */ "fstgt.s\t\0"
|
|
/* 8233 */ "xvfcmp.clt.s\t\0"
|
|
/* 8247 */ "xvfcmp.slt.s\t\0"
|
|
/* 8261 */ "xvfcmp.cult.s\t\0"
|
|
/* 8276 */ "xvfcmp.sult.s\t\0"
|
|
/* 8291 */ "xvfrint.s\t\0"
|
|
/* 8302 */ "xvfsqrt.s\t\0"
|
|
/* 8313 */ "xvfrsqrt.s\t\0"
|
|
/* 8325 */ "fst.s\t\0"
|
|
/* 8332 */ "xvftint.wu.s\t\0"
|
|
/* 8346 */ "xvftintrz.wu.s\t\0"
|
|
/* 8362 */ "xvfdiv.s\t\0"
|
|
/* 8372 */ "fmov.s\t\0"
|
|
/* 8380 */ "xvftintrne.w.s\t\0"
|
|
/* 8396 */ "xvftintrm.w.s\t\0"
|
|
/* 8411 */ "xvftintrp.w.s\t\0"
|
|
/* 8426 */ "xvftint.w.s\t\0"
|
|
/* 8439 */ "xvftintrz.w.s\t\0"
|
|
/* 8454 */ "xvfmax.s\t\0"
|
|
/* 8464 */ "fldx.s\t\0"
|
|
/* 8472 */ "fstx.s\t\0"
|
|
/* 8480 */ "xvfrintrz.s\t\0"
|
|
/* 8493 */ "la.abs\t\0"
|
|
/* 8501 */ "blt\t\0"
|
|
/* 8506 */ "slt\t\0"
|
|
/* 8511 */ "la.got\t\0"
|
|
/* 8519 */ "xvst\t\0"
|
|
/* 8525 */ "xvssub.bu\t\0"
|
|
/* 8536 */ "xvsadd.bu\t\0"
|
|
/* 8547 */ "ld.bu\t\0"
|
|
/* 8554 */ "xvmod.bu\t\0"
|
|
/* 8564 */ "xvabsd.bu\t\0"
|
|
/* 8575 */ "xvsle.bu\t\0"
|
|
/* 8585 */ "xvavg.bu\t\0"
|
|
/* 8595 */ "xvsubwod.h.bu\t\0"
|
|
/* 8610 */ "xvmaddwod.h.bu\t\0"
|
|
/* 8626 */ "xvaddwod.h.bu\t\0"
|
|
/* 8641 */ "xvmulwod.h.bu\t\0"
|
|
/* 8656 */ "xvsubwev.h.bu\t\0"
|
|
/* 8671 */ "xvmaddwev.h.bu\t\0"
|
|
/* 8687 */ "xvaddwev.h.bu\t\0"
|
|
/* 8702 */ "xvmulwev.h.bu\t\0"
|
|
/* 8717 */ "xvmuh.bu\t\0"
|
|
/* 8727 */ "xvsubi.bu\t\0"
|
|
/* 8738 */ "xvaddi.bu\t\0"
|
|
/* 8749 */ "xvslei.bu\t\0"
|
|
/* 8760 */ "xvmini.bu\t\0"
|
|
/* 8771 */ "xvslti.bu\t\0"
|
|
/* 8782 */ "xvmaxi.bu\t\0"
|
|
/* 8793 */ "x86mul.bu\t\0"
|
|
/* 8804 */ "xvmin.bu\t\0"
|
|
/* 8814 */ "vpickve2gr.bu\t\0"
|
|
/* 8829 */ "xvavgr.bu\t\0"
|
|
/* 8840 */ "xvsat.bu\t\0"
|
|
/* 8850 */ "xvslt.bu\t\0"
|
|
/* 8860 */ "vext2xv.du.bu\t\0"
|
|
/* 8875 */ "xvexth.hu.bu\t\0"
|
|
/* 8889 */ "xvsllwil.hu.bu\t\0"
|
|
/* 8905 */ "vext2xv.hu.bu\t\0"
|
|
/* 8920 */ "xvhsubw.hu.bu\t\0"
|
|
/* 8935 */ "xvhaddw.hu.bu\t\0"
|
|
/* 8950 */ "vext2xv.wu.bu\t\0"
|
|
/* 8965 */ "xvdiv.bu\t\0"
|
|
/* 8975 */ "xvmax.bu\t\0"
|
|
/* 8985 */ "ldx.bu\t\0"
|
|
/* 8993 */ "ammin_db.du\t\0"
|
|
/* 9006 */ "ammax_db.du\t\0"
|
|
/* 9019 */ "x86sub.du\t\0"
|
|
/* 9030 */ "xvssub.du\t\0"
|
|
/* 9041 */ "x86add.du\t\0"
|
|
/* 9052 */ "xvsadd.du\t\0"
|
|
/* 9063 */ "xvmod.du\t\0"
|
|
/* 9073 */ "xvabsd.du\t\0"
|
|
/* 9084 */ "xvsle.du\t\0"
|
|
/* 9094 */ "xvavg.du\t\0"
|
|
/* 9104 */ "mulh.du\t\0"
|
|
/* 9113 */ "xvmuh.du\t\0"
|
|
/* 9123 */ "xvsubi.du\t\0"
|
|
/* 9134 */ "xvaddi.du\t\0"
|
|
/* 9145 */ "xvslei.du\t\0"
|
|
/* 9156 */ "xvmini.du\t\0"
|
|
/* 9167 */ "xvslti.du\t\0"
|
|
/* 9178 */ "xvmaxi.du\t\0"
|
|
/* 9189 */ "x86mul.du\t\0"
|
|
/* 9200 */ "ammin.du\t\0"
|
|
/* 9210 */ "xvmin.du\t\0"
|
|
/* 9220 */ "xvsubwod.q.du\t\0"
|
|
/* 9235 */ "xvmaddwod.q.du\t\0"
|
|
/* 9251 */ "xvaddwod.q.du\t\0"
|
|
/* 9266 */ "xvmulwod.q.du\t\0"
|
|
/* 9281 */ "xvsubwev.q.du\t\0"
|
|
/* 9296 */ "xvmaddwev.q.du\t\0"
|
|
/* 9312 */ "xvaddwev.q.du\t\0"
|
|
/* 9327 */ "xvmulwev.q.du\t\0"
|
|
/* 9342 */ "xvpickve2gr.du\t\0"
|
|
/* 9358 */ "xvavgr.du\t\0"
|
|
/* 9369 */ "xvsat.du\t\0"
|
|
/* 9379 */ "xvslt.du\t\0"
|
|
/* 9389 */ "xvexth.qu.du\t\0"
|
|
/* 9403 */ "xvextl.qu.du\t\0"
|
|
/* 9417 */ "xvhsubw.qu.du\t\0"
|
|
/* 9432 */ "xvhaddw.qu.du\t\0"
|
|
/* 9447 */ "xvdiv.du\t\0"
|
|
/* 9457 */ "ammax.du\t\0"
|
|
/* 9467 */ "xvmax.du\t\0"
|
|
/* 9477 */ "bgeu\t\0"
|
|
/* 9483 */ "xvssub.hu\t\0"
|
|
/* 9494 */ "xvsadd.hu\t\0"
|
|
/* 9505 */ "ld.hu\t\0"
|
|
/* 9512 */ "xvmod.hu\t\0"
|
|
/* 9522 */ "xvabsd.hu\t\0"
|
|
/* 9533 */ "xvsle.hu\t\0"
|
|
/* 9543 */ "xvavg.hu\t\0"
|
|
/* 9553 */ "xvmuh.hu\t\0"
|
|
/* 9563 */ "xvsubi.hu\t\0"
|
|
/* 9574 */ "xvaddi.hu\t\0"
|
|
/* 9585 */ "xvslei.hu\t\0"
|
|
/* 9596 */ "xvmini.hu\t\0"
|
|
/* 9607 */ "xvslti.hu\t\0"
|
|
/* 9618 */ "xvmaxi.hu\t\0"
|
|
/* 9629 */ "x86mul.hu\t\0"
|
|
/* 9640 */ "xvmin.hu\t\0"
|
|
/* 9650 */ "vpickve2gr.hu\t\0"
|
|
/* 9665 */ "xvavgr.hu\t\0"
|
|
/* 9676 */ "xvsat.hu\t\0"
|
|
/* 9686 */ "xvslt.hu\t\0"
|
|
/* 9696 */ "vext2xv.du.hu\t\0"
|
|
/* 9711 */ "xvexth.wu.hu\t\0"
|
|
/* 9725 */ "xvsllwil.wu.hu\t\0"
|
|
/* 9741 */ "vext2xv.wu.hu\t\0"
|
|
/* 9756 */ "xvhsubw.wu.hu\t\0"
|
|
/* 9771 */ "xvhaddw.wu.hu\t\0"
|
|
/* 9786 */ "xvdiv.hu\t\0"
|
|
/* 9796 */ "xvsubwod.w.hu\t\0"
|
|
/* 9811 */ "xvmaddwod.w.hu\t\0"
|
|
/* 9827 */ "xvaddwod.w.hu\t\0"
|
|
/* 9842 */ "xvmulwod.w.hu\t\0"
|
|
/* 9857 */ "xvsubwev.w.hu\t\0"
|
|
/* 9872 */ "xvmaddwev.w.hu\t\0"
|
|
/* 9888 */ "xvaddwev.w.hu\t\0"
|
|
/* 9903 */ "xvmulwev.w.hu\t\0"
|
|
/* 9918 */ "xvmax.hu\t\0"
|
|
/* 9928 */ "ldx.hu\t\0"
|
|
/* 9936 */ "xvffint.d.lu\t\0"
|
|
/* 9950 */ "bltu\t\0"
|
|
/* 9956 */ "sltu\t\0"
|
|
/* 9962 */ "ammin_db.wu\t\0"
|
|
/* 9975 */ "ammax_db.wu\t\0"
|
|
/* 9988 */ "x86sub.wu\t\0"
|
|
/* 9999 */ "xvssub.wu\t\0"
|
|
/* 10010 */ "xvsubwod.d.wu\t\0"
|
|
/* 10025 */ "xvmaddwod.d.wu\t\0"
|
|
/* 10041 */ "xvaddwod.d.wu\t\0"
|
|
/* 10056 */ "xvmulwod.d.wu\t\0"
|
|
/* 10071 */ "xvsubwev.d.wu\t\0"
|
|
/* 10086 */ "xvmaddwev.d.wu\t\0"
|
|
/* 10102 */ "xvaddwev.d.wu\t\0"
|
|
/* 10117 */ "xvmulwev.d.wu\t\0"
|
|
/* 10132 */ "mulw.d.wu\t\0"
|
|
/* 10143 */ "x86add.wu\t\0"
|
|
/* 10154 */ "xvsadd.wu\t\0"
|
|
/* 10165 */ "ld.wu\t\0"
|
|
/* 10172 */ "xvmod.wu\t\0"
|
|
/* 10182 */ "xvabsd.wu\t\0"
|
|
/* 10193 */ "xvsle.wu\t\0"
|
|
/* 10203 */ "xvavg.wu\t\0"
|
|
/* 10213 */ "mulh.wu\t\0"
|
|
/* 10222 */ "xvmuh.wu\t\0"
|
|
/* 10232 */ "xvsubi.wu\t\0"
|
|
/* 10243 */ "xvaddi.wu\t\0"
|
|
/* 10254 */ "xvslei.wu\t\0"
|
|
/* 10265 */ "xvmini.wu\t\0"
|
|
/* 10276 */ "xvslti.wu\t\0"
|
|
/* 10287 */ "xvmaxi.wu\t\0"
|
|
/* 10298 */ "alsl.wu\t\0"
|
|
/* 10307 */ "x86mul.wu\t\0"
|
|
/* 10318 */ "ammin.wu\t\0"
|
|
/* 10328 */ "xvmin.wu\t\0"
|
|
/* 10338 */ "xvpickve2gr.wu\t\0"
|
|
/* 10354 */ "xvavgr.wu\t\0"
|
|
/* 10365 */ "xvffint.s.wu\t\0"
|
|
/* 10379 */ "xvsat.wu\t\0"
|
|
/* 10389 */ "xvslt.wu\t\0"
|
|
/* 10399 */ "xvexth.du.wu\t\0"
|
|
/* 10413 */ "xvsllwil.du.wu\t\0"
|
|
/* 10429 */ "vext2xv.du.wu\t\0"
|
|
/* 10444 */ "xvhsubw.du.wu\t\0"
|
|
/* 10459 */ "xvhaddw.du.wu\t\0"
|
|
/* 10474 */ "xvdiv.wu\t\0"
|
|
/* 10484 */ "ammax.wu\t\0"
|
|
/* 10494 */ "xvmax.wu\t\0"
|
|
/* 10504 */ "ldx.wu\t\0"
|
|
/* 10512 */ "xvand.v\t\0"
|
|
/* 10521 */ "xvbitsel.v\t\0"
|
|
/* 10533 */ "xvbsll.v\t\0"
|
|
/* 10543 */ "xvbsrl.v\t\0"
|
|
/* 10553 */ "xvandn.v\t\0"
|
|
/* 10563 */ "xvorn.v\t\0"
|
|
/* 10572 */ "xvnor.v\t\0"
|
|
/* 10581 */ "xvor.v\t\0"
|
|
/* 10589 */ "xvxor.v\t\0"
|
|
/* 10598 */ "xvsetnez.v\t\0"
|
|
/* 10610 */ "xvseteqz.v\t\0"
|
|
/* 10622 */ "xvreplve0.w\t\0"
|
|
/* 10635 */ "xvinsve0.w\t\0"
|
|
/* 10647 */ "xvadda.w\t\0"
|
|
/* 10657 */ "x86sra.w\t\0"
|
|
/* 10667 */ "armsra.w\t\0"
|
|
/* 10677 */ "xvsra.w\t\0"
|
|
/* 10686 */ "crcc.w.b.w\t\0"
|
|
/* 10698 */ "crc.w.b.w\t\0"
|
|
/* 10709 */ "amadd_db.w\t\0"
|
|
/* 10721 */ "amand_db.w\t\0"
|
|
/* 10733 */ "ammin_db.w\t\0"
|
|
/* 10745 */ "amswap_db.w\t\0"
|
|
/* 10758 */ "amor_db.w\t\0"
|
|
/* 10769 */ "amxor_db.w\t\0"
|
|
/* 10781 */ "amcas_db.w\t\0"
|
|
/* 10793 */ "ammax_db.w\t\0"
|
|
/* 10805 */ "x86sub.w\t\0"
|
|
/* 10815 */ "armsub.w\t\0"
|
|
/* 10825 */ "xvmsub.w\t\0"
|
|
/* 10835 */ "xvssub.w\t\0"
|
|
/* 10845 */ "xvsub.w\t\0"
|
|
/* 10854 */ "x86sbc.w\t\0"
|
|
/* 10864 */ "armsbc.w\t\0"
|
|
/* 10874 */ "x86adc.w\t\0"
|
|
/* 10884 */ "armadc.w\t\0"
|
|
/* 10894 */ "x86dec.w\t\0"
|
|
/* 10904 */ "x86inc.w\t\0"
|
|
/* 10914 */ "sc.w\t\0"
|
|
/* 10920 */ "xvsubwod.d.w\t\0"
|
|
/* 10934 */ "xvmaddwod.d.w\t\0"
|
|
/* 10949 */ "xvaddwod.d.w\t\0"
|
|
/* 10963 */ "xvmulwod.d.w\t\0"
|
|
/* 10977 */ "xvffinth.d.w\t\0"
|
|
/* 10991 */ "xvexth.d.w\t\0"
|
|
/* 11003 */ "xvsllwil.d.w\t\0"
|
|
/* 11017 */ "xvffintl.d.w\t\0"
|
|
/* 11031 */ "ffint.d.w\t\0"
|
|
/* 11042 */ "xvsubwev.d.w\t\0"
|
|
/* 11056 */ "xvmaddwev.d.w\t\0"
|
|
/* 11071 */ "xvaddwev.d.w\t\0"
|
|
/* 11085 */ "xvmulwev.d.w\t\0"
|
|
/* 11099 */ "vext2xv.d.w\t\0"
|
|
/* 11112 */ "crcc.w.d.w\t\0"
|
|
/* 11124 */ "crc.w.d.w\t\0"
|
|
/* 11135 */ "xvhsubw.d.w\t\0"
|
|
/* 11148 */ "xvhaddw.d.w\t\0"
|
|
/* 11161 */ "mulw.d.w\t\0"
|
|
/* 11171 */ "x86add.w\t\0"
|
|
/* 11181 */ "amadd.w\t\0"
|
|
/* 11190 */ "armadd.w\t\0"
|
|
/* 11200 */ "xvmadd.w\t\0"
|
|
/* 11210 */ "xvsadd.w\t\0"
|
|
/* 11220 */ "xvadd.w\t\0"
|
|
/* 11229 */ "ld.w\t\0"
|
|
/* 11235 */ "x86and.w\t\0"
|
|
/* 11245 */ "amand.w\t\0"
|
|
/* 11254 */ "armand.w\t\0"
|
|
/* 11264 */ "xvpackod.w\t\0"
|
|
/* 11276 */ "xvpickod.w\t\0"
|
|
/* 11288 */ "xvmod.w\t\0"
|
|
/* 11297 */ "iocsrrd.w\t\0"
|
|
/* 11308 */ "xvabsd.w\t\0"
|
|
/* 11318 */ "ldle.w\t\0"
|
|
/* 11326 */ "xvsle.w\t\0"
|
|
/* 11335 */ "stle.w\t\0"
|
|
/* 11343 */ "xvpickve.w\t\0"
|
|
/* 11355 */ "xvreplve.w\t\0"
|
|
/* 11367 */ "xvshuf.w\t\0"
|
|
/* 11377 */ "xvneg.w\t\0"
|
|
/* 11386 */ "xvavg.w\t\0"
|
|
/* 11395 */ "xvssrani.h.w\t\0"
|
|
/* 11409 */ "xvsrani.h.w\t\0"
|
|
/* 11422 */ "xvssrlni.h.w\t\0"
|
|
/* 11436 */ "xvsrlni.h.w\t\0"
|
|
/* 11449 */ "xvssrarni.h.w\t\0"
|
|
/* 11464 */ "xvsrarni.h.w\t\0"
|
|
/* 11478 */ "xvssrlrni.h.w\t\0"
|
|
/* 11493 */ "xvsrlrni.h.w\t\0"
|
|
/* 11507 */ "xvssran.h.w\t\0"
|
|
/* 11520 */ "xvsran.h.w\t\0"
|
|
/* 11532 */ "xvssrln.h.w\t\0"
|
|
/* 11545 */ "xvsrln.h.w\t\0"
|
|
/* 11557 */ "xvssrarn.h.w\t\0"
|
|
/* 11571 */ "xvsrarn.h.w\t\0"
|
|
/* 11584 */ "xvssrlrn.h.w\t\0"
|
|
/* 11598 */ "xvsrlrn.h.w\t\0"
|
|
/* 11611 */ "crcc.w.h.w\t\0"
|
|
/* 11623 */ "crc.w.h.w\t\0"
|
|
/* 11634 */ "rdtimeh.w\t\0"
|
|
/* 11645 */ "mulh.w\t\0"
|
|
/* 11653 */ "movgr2frh.w\t\0"
|
|
/* 11666 */ "xvmuh.w\t\0"
|
|
/* 11675 */ "xvilvh.w\t\0"
|
|
/* 11685 */ "addu12i.w\t\0"
|
|
/* 11696 */ "lu12i.w\t\0"
|
|
/* 11705 */ "xvshuf4i.w\t\0"
|
|
/* 11717 */ "x86srai.w\t\0"
|
|
/* 11728 */ "armsrai.w\t\0"
|
|
/* 11739 */ "xvsrai.w\t\0"
|
|
/* 11749 */ "addi.w\t\0"
|
|
/* 11757 */ "xvslei.w\t\0"
|
|
/* 11767 */ "xvrepl128vei.w\t\0"
|
|
/* 11783 */ "vreplvei.w\t\0"
|
|
/* 11795 */ "x86rcli.w\t\0"
|
|
/* 11806 */ "x86slli.w\t\0"
|
|
/* 11817 */ "armslli.w\t\0"
|
|
/* 11828 */ "xvslli.w\t\0"
|
|
/* 11838 */ "xvrepli.w\t\0"
|
|
/* 11849 */ "x86srli.w\t\0"
|
|
/* 11860 */ "armsrli.w\t\0"
|
|
/* 11871 */ "xvsrli.w\t\0"
|
|
/* 11881 */ "x86rotli.w\t\0"
|
|
/* 11893 */ "xvpermi.w\t\0"
|
|
/* 11904 */ "xvmini.w\t\0"
|
|
/* 11914 */ "xvseqi.w\t\0"
|
|
/* 11924 */ "xvsrari.w\t\0"
|
|
/* 11935 */ "x86rcri.w\t\0"
|
|
/* 11946 */ "xvbitclri.w\t\0"
|
|
/* 11959 */ "xvsrlri.w\t\0"
|
|
/* 11970 */ "x86rotri.w\t\0"
|
|
/* 11982 */ "armrotri.w\t\0"
|
|
/* 11994 */ "xvrotri.w\t\0"
|
|
/* 12005 */ "xvbitseti.w\t\0"
|
|
/* 12018 */ "xvslti.w\t\0"
|
|
/* 12028 */ "xvbitrevi.w\t\0"
|
|
/* 12041 */ "xvmaxi.w\t\0"
|
|
/* 12051 */ "bytepick.w\t\0"
|
|
/* 12063 */ "bstrpick.w\t\0"
|
|
/* 12075 */ "x86rcl.w\t\0"
|
|
/* 12085 */ "ldl.w\t\0"
|
|
/* 12092 */ "rdtimel.w\t\0"
|
|
/* 12103 */ "screl.w\t\0"
|
|
/* 12112 */ "x86sll.w\t\0"
|
|
/* 12122 */ "armsll.w\t\0"
|
|
/* 12132 */ "xvsll.w\t\0"
|
|
/* 12141 */ "xvldrepl.w\t\0"
|
|
/* 12153 */ "x86srl.w\t\0"
|
|
/* 12163 */ "armsrl.w\t\0"
|
|
/* 12173 */ "xvsrl.w\t\0"
|
|
/* 12182 */ "alsl.w\t\0"
|
|
/* 12190 */ "x86rotl.w\t\0"
|
|
/* 12201 */ "stl.w\t\0"
|
|
/* 12208 */ "x86mul.w\t\0"
|
|
/* 12218 */ "xvmul.w\t\0"
|
|
/* 12227 */ "xvilvl.w\t\0"
|
|
/* 12237 */ "xvstelm.w\t\0"
|
|
/* 12248 */ "xvperm.w\t\0"
|
|
/* 12258 */ "ammin.w\t\0"
|
|
/* 12267 */ "xvmin.w\t\0"
|
|
/* 12276 */ "xvclo.w\t\0"
|
|
/* 12285 */ "cto.w\t\0"
|
|
/* 12292 */ "amswap.w\t\0"
|
|
/* 12302 */ "llacq.w\t\0"
|
|
/* 12311 */ "xvseq.w\t\0"
|
|
/* 12320 */ "xvsrar.w\t\0"
|
|
/* 12330 */ "x86rcr.w\t\0"
|
|
/* 12340 */ "ldr.w\t\0"
|
|
/* 12347 */ "movgr2fr.w\t\0"
|
|
/* 12359 */ "xvpickve2gr.w\t\0"
|
|
/* 12374 */ "xvavgr.w\t\0"
|
|
/* 12384 */ "xvbitclr.w\t\0"
|
|
/* 12396 */ "xvsrlr.w\t\0"
|
|
/* 12406 */ "x86or.w\t\0"
|
|
/* 12415 */ "amor.w\t\0"
|
|
/* 12423 */ "armor.w\t\0"
|
|
/* 12432 */ "x86xor.w\t\0"
|
|
/* 12442 */ "amxor.w\t\0"
|
|
/* 12451 */ "armxor.w\t\0"
|
|
/* 12461 */ "x86rotr.w\t\0"
|
|
/* 12472 */ "armrotr.w\t\0"
|
|
/* 12483 */ "xvrotr.w\t\0"
|
|
/* 12493 */ "ldptr.w\t\0"
|
|
/* 12502 */ "stptr.w\t\0"
|
|
/* 12511 */ "str.w\t\0"
|
|
/* 12518 */ "xvreplgr2vr.w\t\0"
|
|
/* 12533 */ "xvinsgr2vr.w\t\0"
|
|
/* 12547 */ "iocsrwr.w\t\0"
|
|
/* 12558 */ "xvffint.s.w\t\0"
|
|
/* 12571 */ "amcas.w\t\0"
|
|
/* 12580 */ "bstrins.w\t\0"
|
|
/* 12591 */ "xvextrins.w\t\0"
|
|
/* 12604 */ "xvsat.w\t\0"
|
|
/* 12613 */ "xvbitset.w\t\0"
|
|
/* 12625 */ "ldgt.w\t\0"
|
|
/* 12633 */ "stgt.w\t\0"
|
|
/* 12641 */ "xvslt.w\t\0"
|
|
/* 12650 */ "xvpcnt.w\t\0"
|
|
/* 12660 */ "armnot.w\t\0"
|
|
/* 12670 */ "st.w\t\0"
|
|
/* 12676 */ "xvssrani.hu.w\t\0"
|
|
/* 12691 */ "xvssrlni.hu.w\t\0"
|
|
/* 12706 */ "xvssrarni.hu.w\t\0"
|
|
/* 12722 */ "xvssrlrni.hu.w\t\0"
|
|
/* 12738 */ "xvssran.hu.w\t\0"
|
|
/* 12752 */ "xvssrln.hu.w\t\0"
|
|
/* 12766 */ "xvssrarn.hu.w\t\0"
|
|
/* 12781 */ "xvssrlrn.hu.w\t\0"
|
|
/* 12796 */ "xvmaddwod.d.wu.w\t\0"
|
|
/* 12814 */ "xvaddwod.d.wu.w\t\0"
|
|
/* 12831 */ "xvmulwod.d.wu.w\t\0"
|
|
/* 12848 */ "xvmaddwev.d.wu.w\t\0"
|
|
/* 12866 */ "xvaddwev.d.wu.w\t\0"
|
|
/* 12883 */ "xvmulwev.d.wu.w\t\0"
|
|
/* 12900 */ "xvpackev.w\t\0"
|
|
/* 12912 */ "xvpickev.w\t\0"
|
|
/* 12924 */ "xvbitrev.w\t\0"
|
|
/* 12936 */ "xvdiv.w\t\0"
|
|
/* 12945 */ "xvsigncov.w\t\0"
|
|
/* 12958 */ "armmov.w\t\0"
|
|
/* 12968 */ "crcc.w.w.w\t\0"
|
|
/* 12980 */ "crc.w.w.w\t\0"
|
|
/* 12991 */ "ammax.w\t\0"
|
|
/* 13000 */ "xvmax.w\t\0"
|
|
/* 13009 */ "ldx.w\t\0"
|
|
/* 13016 */ "armrrx.w\t\0"
|
|
/* 13026 */ "stx.w\t\0"
|
|
/* 13033 */ "xvsetallnez.w\t\0"
|
|
/* 13048 */ "xvclz.w\t\0"
|
|
/* 13057 */ "xvsetanyeqz.w\t\0"
|
|
/* 13072 */ "ctz.w\t\0"
|
|
/* 13079 */ "xvmskltz.w\t\0"
|
|
/* 13091 */ "revb.2w\t\0"
|
|
/* 13100 */ "revh.2w\t\0"
|
|
/* 13109 */ "preldx\t\0"
|
|
/* 13117 */ "xvldx\t\0"
|
|
/* 13124 */ "xvstx\t\0"
|
|
/* 13131 */ "bnez\t\0"
|
|
/* 13137 */ "bcnez\t\0"
|
|
/* 13144 */ "masknez\t\0"
|
|
/* 13153 */ "beqz\t\0"
|
|
/* 13159 */ "bceqz\t\0"
|
|
/* 13166 */ "maskeqz\t\0"
|
|
/* 13175 */ "# XRay Function Patchable RET.\0"
|
|
/* 13206 */ "# XRay Typed Event Log.\0"
|
|
/* 13230 */ "# XRay Custom Event Log.\0"
|
|
/* 13255 */ "# XRay Function Enter.\0"
|
|
/* 13278 */ "# XRay Tail Call Exit.\0"
|
|
/* 13301 */ "# XRay Function Exit.\0"
|
|
/* 13323 */ "LIFETIME_END\0"
|
|
/* 13336 */ "PSEUDO_PROBE\0"
|
|
/* 13349 */ "BUNDLE\0"
|
|
/* 13356 */ "DBG_VALUE\0"
|
|
/* 13366 */ "DBG_INSTR_REF\0"
|
|
/* 13380 */ "DBG_PHI\0"
|
|
/* 13388 */ "DBG_LABEL\0"
|
|
/* 13398 */ "LIFETIME_START\0"
|
|
/* 13413 */ "DBG_VALUE_LIST\0"
|
|
/* 13428 */ "# FEntry call\0"
|
|
};
|
|
#endif // CAPSTONE_DIET
|
|
|
|
static const uint16_t OpInfo0[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
13357U, // DBG_VALUE
|
|
13414U, // DBG_VALUE_LIST
|
|
13367U, // DBG_INSTR_REF
|
|
13381U, // DBG_PHI
|
|
13389U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
13350U, // BUNDLE
|
|
13399U, // LIFETIME_START
|
|
13324U, // LIFETIME_END
|
|
13337U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
13429U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
13256U, // PATCHABLE_FUNCTION_ENTER
|
|
13176U, // PATCHABLE_RET
|
|
13302U, // PATCHABLE_FUNCTION_EXIT
|
|
13279U, // PATCHABLE_TAIL_CALL
|
|
13231U, // PATCHABLE_EVENT_CALL
|
|
13207U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // MEMBARRIER
|
|
0U, // JUMP_TABLE_DEBUG_INFO
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_CONSTANT_POOL
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_CONSTANT_FOLD_BARRIER
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_ATOMICRMW_UINC_WRAP
|
|
0U, // G_ATOMICRMW_UDEC_WRAP
|
|
0U, // G_FENCE
|
|
0U, // G_PREFETCH
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_INTRINSIC_CONVERGENT
|
|
0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FEXP10
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FLDEXP
|
|
0U, // G_FFREXP
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_GET_FPENV
|
|
0U, // G_SET_FPENV
|
|
0U, // G_RESET_FPENV
|
|
0U, // G_GET_FPMODE
|
|
0U, // G_SET_FPMODE
|
|
0U, // G_RESET_FPMODE
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STACKSAVE
|
|
0U, // G_STACKRESTORE
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_STRICT_FLDEXP
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_FMAXIMUM
|
|
0U, // G_VECREDUCE_FMINIMUM
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
7U, // ADJCALLSTACKDOWN
|
|
7U, // ADJCALLSTACKUP
|
|
7U, // PseudoAtomicLoadAdd32
|
|
7U, // PseudoAtomicLoadAnd32
|
|
7U, // PseudoAtomicLoadNand32
|
|
7U, // PseudoAtomicLoadNand64
|
|
7U, // PseudoAtomicLoadOr32
|
|
7U, // PseudoAtomicLoadSub32
|
|
7U, // PseudoAtomicLoadXor32
|
|
7U, // PseudoAtomicStoreD
|
|
7U, // PseudoAtomicStoreW
|
|
7U, // PseudoAtomicSwap32
|
|
7U, // PseudoBR
|
|
7U, // PseudoBRIND
|
|
7U, // PseudoB_TAIL
|
|
7U, // PseudoCALL
|
|
16409U, // PseudoCALL36
|
|
7U, // PseudoCALLIndirect
|
|
7U, // PseudoCALL_LARGE
|
|
7U, // PseudoCALL_MEDIUM
|
|
7U, // PseudoCmpXchg32
|
|
7U, // PseudoCmpXchg64
|
|
7U, // PseudoCopyCFR
|
|
7U, // PseudoJIRL_CALL
|
|
7U, // PseudoJIRL_TAIL
|
|
24878U, // PseudoLA_ABS
|
|
24878U, // PseudoLA_ABS_LARGE
|
|
24896U, // PseudoLA_GOT
|
|
24896U, // PseudoLA_GOT_LARGE
|
|
23302U, // PseudoLA_PCREL
|
|
23302U, // PseudoLA_PCREL_LARGE
|
|
21043U, // PseudoLA_TLS_GD
|
|
21043U, // PseudoLA_TLS_GD_LARGE
|
|
21114U, // PseudoLA_TLS_IE
|
|
21114U, // PseudoLA_TLS_IE_LARGE
|
|
21065U, // PseudoLA_TLS_LD
|
|
21065U, // PseudoLA_TLS_LD_LARGE
|
|
21125U, // PseudoLA_TLS_LE
|
|
7U, // PseudoLD_CFR
|
|
18967U, // PseudoLI_D
|
|
28185U, // PseudoLI_W
|
|
7U, // PseudoMaskedAtomicLoadAdd32
|
|
7U, // PseudoMaskedAtomicLoadMax32
|
|
7U, // PseudoMaskedAtomicLoadMin32
|
|
7U, // PseudoMaskedAtomicLoadNand32
|
|
7U, // PseudoMaskedAtomicLoadSub32
|
|
7U, // PseudoMaskedAtomicLoadUMax32
|
|
7U, // PseudoMaskedAtomicLoadUMin32
|
|
7U, // PseudoMaskedAtomicSwap32
|
|
7U, // PseudoMaskedCmpXchg32
|
|
7U, // PseudoRET
|
|
7U, // PseudoST_CFR
|
|
7U, // PseudoTAIL
|
|
16401U, // PseudoTAIL36
|
|
7U, // PseudoTAILIndirect
|
|
7U, // PseudoTAIL_LARGE
|
|
7U, // PseudoTAIL_MEDIUM
|
|
7U, // PseudoUNIMP
|
|
7U, // PseudoVBNZ
|
|
7U, // PseudoVBNZ_B
|
|
7U, // PseudoVBNZ_D
|
|
7U, // PseudoVBNZ_H
|
|
7U, // PseudoVBNZ_W
|
|
7U, // PseudoVBZ
|
|
7U, // PseudoVBZ_B
|
|
7U, // PseudoVBZ_D
|
|
7U, // PseudoVBZ_H
|
|
7U, // PseudoVBZ_W
|
|
17096U, // PseudoVREPLI_B
|
|
19006U, // PseudoVREPLI_D
|
|
21976U, // PseudoVREPLI_H
|
|
28224U, // PseudoVREPLI_W
|
|
7U, // PseudoXVBNZ
|
|
7U, // PseudoXVBNZ_B
|
|
7U, // PseudoXVBNZ_D
|
|
7U, // PseudoXVBNZ_H
|
|
7U, // PseudoXVBNZ_W
|
|
7U, // PseudoXVBZ
|
|
7U, // PseudoXVBZ_B
|
|
7U, // PseudoXVBZ_D
|
|
7U, // PseudoXVBZ_H
|
|
7U, // PseudoXVBZ_W
|
|
7U, // PseudoXVINSGR2VR_B
|
|
7U, // PseudoXVINSGR2VR_H
|
|
17095U, // PseudoXVREPLI_B
|
|
19005U, // PseudoXVREPLI_D
|
|
21975U, // PseudoXVREPLI_H
|
|
28223U, // PseudoXVREPLI_W
|
|
7U, // RDFCSR
|
|
7U, // WRFCSR
|
|
16548U, // ADC_B
|
|
18301U, // ADC_D
|
|
21630U, // ADC_H
|
|
27262U, // ADC_W
|
|
18916U, // ADDI_D
|
|
28134U, // ADDI_W
|
|
18843U, // ADDU12I_D
|
|
28070U, // ADDU12I_W
|
|
18884U, // ADDU16I_D
|
|
18337U, // ADD_D
|
|
27559U, // ADD_W
|
|
19369U, // ALSL_D
|
|
28567U, // ALSL_W
|
|
26683U, // ALSL_WU
|
|
16598U, // AMADD_B
|
|
18354U, // AMADD_D
|
|
21680U, // AMADD_H
|
|
27566U, // AMADD_W
|
|
16459U, // AMADD__DB_B
|
|
18090U, // AMADD__DB_D
|
|
21541U, // AMADD__DB_H
|
|
27094U, // AMADD__DB_W
|
|
18443U, // AMAND_D
|
|
27630U, // AMAND_W
|
|
18102U, // AMAND__DB_D
|
|
27106U, // AMAND__DB_W
|
|
17619U, // AMCAS_B
|
|
20078U, // AMCAS_D
|
|
22496U, // AMCAS_H
|
|
28956U, // AMCAS_W
|
|
16484U, // AMCAS__DB_B
|
|
18162U, // AMCAS__DB_D
|
|
21566U, // AMCAS__DB_H
|
|
27166U, // AMCAS__DB_W
|
|
20938U, // AMMAX_D
|
|
25842U, // AMMAX_DU
|
|
29376U, // AMMAX_W
|
|
26869U, // AMMAX_WU
|
|
18174U, // AMMAX__DB_D
|
|
25391U, // AMMAX__DB_DU
|
|
27178U, // AMMAX__DB_W
|
|
26360U, // AMMAX__DB_WU
|
|
19481U, // AMMIN_D
|
|
25585U, // AMMIN_DU
|
|
28643U, // AMMIN_W
|
|
26703U, // AMMIN_WU
|
|
18114U, // AMMIN__DB_D
|
|
25378U, // AMMIN__DB_DU
|
|
27118U, // AMMIN__DB_W
|
|
26347U, // AMMIN__DB_WU
|
|
19939U, // AMOR_D
|
|
28800U, // AMOR_W
|
|
18139U, // AMOR__DB_D
|
|
27143U, // AMOR__DB_W
|
|
17444U, // AMSWAP_B
|
|
19543U, // AMSWAP_D
|
|
22295U, // AMSWAP_H
|
|
28677U, // AMSWAP_W
|
|
16471U, // AMSWAP__DB_B
|
|
18126U, // AMSWAP__DB_D
|
|
21553U, // AMSWAP__DB_H
|
|
27130U, // AMSWAP__DB_W
|
|
19971U, // AMXOR_D
|
|
28827U, // AMXOR_W
|
|
18150U, // AMXOR__DB_D
|
|
27154U, // AMXOR__DB_W
|
|
21089U, // AND
|
|
23210U, // ANDI
|
|
23362U, // ANDN
|
|
27269U, // ARMADC_W
|
|
27575U, // ARMADD_W
|
|
27639U, // ARMAND_W
|
|
21221U, // ARMMFFLAG
|
|
21181U, // ARMMOVE
|
|
20628U, // ARMMOV_D
|
|
29343U, // ARMMOV_W
|
|
21243U, // ARMMTFLAG
|
|
29045U, // ARMNOT_W
|
|
28808U, // ARMOR_W
|
|
28367U, // ARMROTRI_W
|
|
28857U, // ARMROTR_W
|
|
29401U, // ARMRRX_W
|
|
27249U, // ARMSBC_W
|
|
28202U, // ARMSLLI_W
|
|
28507U, // ARMSLL_W
|
|
28113U, // ARMSRAI_W
|
|
27052U, // ARMSRA_W
|
|
28245U, // ARMSRLI_W
|
|
28548U, // ARMSRL_W
|
|
27200U, // ARMSUB_W
|
|
28836U, // ARMXOR_W
|
|
20161U, // ASRTGT_D
|
|
18563U, // ASRTLE_D
|
|
16427U, // B
|
|
29544U, // BCEQZ
|
|
29522U, // BCNEZ
|
|
23650U, // BEQ
|
|
29538U, // BEQZ
|
|
21109U, // BGE
|
|
25862U, // BGEU
|
|
17984U, // BITREV_4B
|
|
17995U, // BITREV_8B
|
|
20578U, // BITREV_D
|
|
29311U, // BITREV_W
|
|
23286U, // BL
|
|
24886U, // BLT
|
|
26335U, // BLTU
|
|
21142U, // BNE
|
|
29516U, // BNEZ
|
|
23253U, // BREAK
|
|
36479U, // BSTRINS_D
|
|
45349U, // BSTRINS_W
|
|
19207U, // BSTRPICK_D
|
|
28448U, // BSTRPICK_W
|
|
19195U, // BYTEPICK_D
|
|
28436U, // BYTEPICK_W
|
|
23379U, // CACOP
|
|
19529U, // CLO_D
|
|
28663U, // CLO_W
|
|
20989U, // CLZ_D
|
|
29435U, // CLZ_W
|
|
21265U, // CPUCFG
|
|
27071U, // CRCC_W_B_W
|
|
27497U, // CRCC_W_D_W
|
|
27996U, // CRCC_W_H_W
|
|
29353U, // CRCC_W_W_W
|
|
27083U, // CRC_W_B_W
|
|
27509U, // CRC_W_D_W
|
|
28008U, // CRC_W_H_W
|
|
29365U, // CRC_W_W_W
|
|
21102U, // CSRRD
|
|
40150U, // CSRWR
|
|
37658U, // CSRXCHG
|
|
19536U, // CTO_D
|
|
28670U, // CTO_W
|
|
21024U, // CTZ_D
|
|
29457U, // CTZ_W
|
|
23655U, // DBAR
|
|
23290U, // DBCL
|
|
20591U, // DIV_D
|
|
25834U, // DIV_DU
|
|
29323U, // DIV_W
|
|
26861U, // DIV_WU
|
|
6989U, // ERTN
|
|
17865U, // EXT_W_B
|
|
22945U, // EXT_W_H
|
|
20087U, // FABS_D
|
|
24580U, // FABS_S
|
|
18346U, // FADD_D
|
|
23888U, // FADD_S
|
|
20121U, // FCLASS_D
|
|
24590U, // FCLASS_S
|
|
18746U, // FCMP_CAF_D
|
|
24102U, // FCMP_CAF_S
|
|
19753U, // FCMP_CEQ_D
|
|
24471U, // FCMP_CEQ_S
|
|
18519U, // FCMP_CLE_D
|
|
23928U, // FCMP_CLE_S
|
|
20182U, // FCMP_CLT_D
|
|
24620U, // FCMP_CLT_S
|
|
18624U, // FCMP_CNE_D
|
|
24004U, // FCMP_CNE_S
|
|
19927U, // FCMP_COR_D
|
|
24554U, // FCMP_COR_S
|
|
19790U, // FCMP_CUEQ_D
|
|
24499U, // FCMP_CUEQ_S
|
|
18584U, // FCMP_CULE_D
|
|
23974U, // FCMP_CULE_S
|
|
20219U, // FCMP_CULT_D
|
|
24648U, // FCMP_CULT_S
|
|
18666U, // FCMP_CUNE_D
|
|
24046U, // FCMP_CUNE_S
|
|
19501U, // FCMP_CUN_D
|
|
24418U, // FCMP_CUN_S
|
|
18760U, // FCMP_SAF_D
|
|
24116U, // FCMP_SAF_S
|
|
19767U, // FCMP_SEQ_D
|
|
24485U, // FCMP_SEQ_S
|
|
18542U, // FCMP_SLE_D
|
|
23951U, // FCMP_SLE_S
|
|
20196U, // FCMP_SLT_D
|
|
24634U, // FCMP_SLT_S
|
|
18652U, // FCMP_SNE_D
|
|
24032U, // FCMP_SNE_S
|
|
19949U, // FCMP_SOR_D
|
|
24568U, // FCMP_SOR_S
|
|
19805U, // FCMP_SUEQ_D
|
|
24514U, // FCMP_SUEQ_S
|
|
18599U, // FCMP_SULE_D
|
|
23989U, // FCMP_SULE_S
|
|
20234U, // FCMP_SULT_D
|
|
24663U, // FCMP_SULT_S
|
|
18681U, // FCMP_SUNE_D
|
|
24061U, // FCMP_SUNE_S
|
|
19515U, // FCMP_SUN_D
|
|
24432U, // FCMP_SUN_S
|
|
19458U, // FCOPYSIGN_D
|
|
24393U, // FCOPYSIGN_S
|
|
21054U, // FCVT_D_LD
|
|
23876U, // FCVT_D_S
|
|
18415U, // FCVT_LD_D
|
|
20068U, // FCVT_S_D
|
|
18506U, // FCVT_UD_D
|
|
20590U, // FDIV_D
|
|
24749U, // FDIV_S
|
|
23262U, // FFINT_D_L
|
|
27416U, // FFINT_D_W
|
|
23275U, // FFINT_S_L
|
|
28945U, // FFINT_S_W
|
|
20152U, // FLDGT_D
|
|
24600U, // FLDGT_S
|
|
18531U, // FLDLE_D
|
|
23940U, // FLDLE_S
|
|
20956U, // FLDX_D
|
|
24849U, // FLDX_S
|
|
18426U, // FLD_D
|
|
23919U, // FLD_S
|
|
18199U, // FLOGB_D
|
|
23808U, // FLOGB_S
|
|
18365U, // FMADD_D
|
|
23898U, // FMADD_S
|
|
18081U, // FMAXA_D
|
|
23786U, // FMAXA_S
|
|
20930U, // FMAX_D
|
|
24841U, // FMAX_S
|
|
18051U, // FMINA_D
|
|
23775U, // FMINA_S
|
|
19473U, // FMIN_D
|
|
24408U, // FMIN_S
|
|
20620U, // FMOV_D
|
|
24757U, // FMOV_S
|
|
18230U, // FMSUB_D
|
|
23829U, // FMSUB_S
|
|
19407U, // FMUL_D
|
|
24372U, // FMUL_S
|
|
18782U, // FNEG_D
|
|
24128U, // FNEG_S
|
|
18376U, // FNMADD_D
|
|
23909U, // FNMADD_S
|
|
18241U, // FNMSUB_D
|
|
23840U, // FNMSUB_S
|
|
18696U, // FRECIPE_D
|
|
24076U, // FRECIPE_S
|
|
19555U, // FRECIP_D
|
|
24446U, // FRECIP_S
|
|
20259U, // FRINT_D
|
|
24678U, // FRINT_S
|
|
18709U, // FRSQRTE_D
|
|
24089U, // FRSQRTE_S
|
|
20281U, // FRSQRT_D
|
|
24700U, // FRSQRT_S
|
|
18186U, // FSCALEB_D
|
|
23795U, // FSCALEB_S
|
|
23312U, // FSEL_xD
|
|
23312U, // FSEL_xS
|
|
20270U, // FSQRT_D
|
|
24689U, // FSQRT_S
|
|
20171U, // FSTGT_D
|
|
24609U, // FSTGT_S
|
|
18573U, // FSTLE_D
|
|
23963U, // FSTLE_S
|
|
20964U, // FSTX_D
|
|
24857U, // FSTX_S
|
|
20291U, // FST_D
|
|
24710U, // FST_S
|
|
18220U, // FSUB_D
|
|
23819U, // FSUB_S
|
|
19237U, // FTINTRM_L_D
|
|
24320U, // FTINTRM_L_S
|
|
20768U, // FTINTRM_W_D
|
|
24783U, // FTINTRM_W_S
|
|
19221U, // FTINTRNE_L_D
|
|
24148U, // FTINTRNE_L_S
|
|
20640U, // FTINTRNE_W_D
|
|
24767U, // FTINTRNE_W_S
|
|
19252U, // FTINTRP_L_D
|
|
24333U, // FTINTRP_L_S
|
|
20887U, // FTINTRP_W_D
|
|
24798U, // FTINTRP_W_S
|
|
19280U, // FTINTRZ_L_D
|
|
24357U, // FTINTRZ_L_S
|
|
20915U, // FTINTRZ_W_D
|
|
24826U, // FTINTRZ_W_S
|
|
19267U, // FTINT_L_D
|
|
24346U, // FTINT_L_S
|
|
20902U, // FTINT_W_D
|
|
24813U, // FTINT_W_S
|
|
21101U, // GCSRRD
|
|
40149U, // GCSRWR
|
|
37657U, // GCSRXCHG
|
|
6767U, // GTLBFLUSH
|
|
23296U, // HVCL
|
|
23661U, // IBAR
|
|
21136U, // IDLE
|
|
50774U, // INVTLB
|
|
16685U, // IOCSRRD_B
|
|
18485U, // IOCSRRD_D
|
|
21767U, // IOCSRRD_H
|
|
27682U, // IOCSRRD_W
|
|
17608U, // IOCSRWR_B
|
|
20055U, // IOCSRWR_D
|
|
22459U, // IOCSRWR_H
|
|
28932U, // IOCSRWR_W
|
|
23336U, // JIRL
|
|
16385U, // JISCR0
|
|
16393U, // JISCR1
|
|
23721U, // LDDIR
|
|
17662U, // LDGT_B
|
|
20153U, // LDGT_D
|
|
22539U, // LDGT_H
|
|
29010U, // LDGT_W
|
|
16706U, // LDLE_B
|
|
18532U, // LDLE_D
|
|
21788U, // LDLE_H
|
|
27703U, // LDLE_W
|
|
19303U, // LDL_D
|
|
28470U, // LDL_W
|
|
21174U, // LDPTE
|
|
20001U, // LDPTR_D
|
|
28878U, // LDPTR_W
|
|
19838U, // LDR_D
|
|
28725U, // LDR_W
|
|
17896U, // LDX_B
|
|
25370U, // LDX_BU
|
|
20957U, // LDX_D
|
|
23059U, // LDX_H
|
|
26313U, // LDX_HU
|
|
29394U, // LDX_W
|
|
26889U, // LDX_WU
|
|
16636U, // LD_B
|
|
24932U, // LD_BU
|
|
18420U, // LD_D
|
|
21718U, // LD_H
|
|
25890U, // LD_HU
|
|
27614U, // LD_W
|
|
26550U, // LD_WU
|
|
19742U, // LLACQ_D
|
|
28687U, // LLACQ_W
|
|
19323U, // LL_D
|
|
28501U, // LL_W
|
|
28081U, // LU12I_W
|
|
35238U, // LU32I_D
|
|
18863U, // LU52I_D
|
|
29551U, // MASKEQZ
|
|
29529U, // MASKNEZ
|
|
18478U, // MOD_D
|
|
25450U, // MOD_DU
|
|
27675U, // MOD_W
|
|
26559U, // MOD_WU
|
|
23678U, // MOVCF2FR_xS
|
|
23688U, // MOVCF2GR
|
|
23709U, // MOVFCSR2GR
|
|
21190U, // MOVFR2CF_xS
|
|
19872U, // MOVFR2GR_D
|
|
24540U, // MOVFR2GR_S
|
|
24540U, // MOVFR2GR_S_64
|
|
24527U, // MOVFRH2GR_S
|
|
21200U, // MOVGR2CF
|
|
23746U, // MOVGR2FCSR
|
|
44422U, // MOVGR2FRH_W
|
|
19845U, // MOVGR2FR_D
|
|
28732U, // MOVGR2FR_W
|
|
28732U, // MOVGR2FR_W_64
|
|
23667U, // MOVGR2SCR
|
|
23698U, // MOVSCR2GR
|
|
18808U, // MULH_D
|
|
25489U, // MULH_DU
|
|
28030U, // MULH_W
|
|
26598U, // MULH_WU
|
|
27546U, // MULW_D_W
|
|
26517U, // MULW_D_WU
|
|
19398U, // MUL_D
|
|
28596U, // MUL_W
|
|
23736U, // NOR
|
|
23737U, // OR
|
|
23217U, // ORI
|
|
23368U, // ORN
|
|
23195U, // PCADDI
|
|
23173U, // PCADDU12I
|
|
23184U, // PCADDU18I
|
|
23162U, // PCALAU12I
|
|
21076U, // PRELD
|
|
29494U, // PRELDX
|
|
17185U, // RCRI_B
|
|
19094U, // RCRI_D
|
|
22065U, // RCRI_H
|
|
28323U, // RCRI_W
|
|
17487U, // RCR_B
|
|
19831U, // RCR_D
|
|
22338U, // RCR_H
|
|
28718U, // RCR_W
|
|
28019U, // RDTIMEH_W
|
|
28477U, // RDTIMEL_W
|
|
18612U, // RDTIME_D
|
|
23124U, // REVB_2H
|
|
29476U, // REVB_2W
|
|
23133U, // REVB_4H
|
|
18280U, // REVB_D
|
|
29485U, // REVH_2W
|
|
18825U, // REVH_D
|
|
17249U, // ROTRI_B
|
|
19129U, // ROTRI_D
|
|
22100U, // ROTRI_H
|
|
28358U, // ROTRI_W
|
|
17562U, // ROTR_B
|
|
19983U, // ROTR_D
|
|
22413U, // ROTR_H
|
|
28849U, // ROTR_W
|
|
16538U, // SBC_B
|
|
18291U, // SBC_D
|
|
21620U, // SBC_H
|
|
27242U, // SBC_W
|
|
35694U, // SCREL_D
|
|
44872U, // SCREL_W
|
|
34712U, // SC_D
|
|
39834U, // SC_Q
|
|
43683U, // SC_W
|
|
23244U, // SETARMJ
|
|
23235U, // SETX86J
|
|
21161U, // SETX86LOOPE
|
|
21147U, // SETX86LOOPNE
|
|
24102U, // SET_CFR_FALSE
|
|
24499U, // SET_CFR_TRUE
|
|
18987U, // SLLI_D
|
|
28194U, // SLLI_W
|
|
19322U, // SLL_D
|
|
28500U, // SLL_W
|
|
24891U, // SLT
|
|
23222U, // SLTI
|
|
26341U, // SLTU
|
|
23228U, // SLTUI
|
|
18898U, // SRAI_D
|
|
28105U, // SRAI_W
|
|
18063U, // SRA_D
|
|
27045U, // SRA_W
|
|
19019U, // SRLI_D
|
|
28237U, // SRLI_W
|
|
19353U, // SRL_D
|
|
28541U, // SRL_W
|
|
17670U, // STGT_B
|
|
20172U, // STGT_D
|
|
22547U, // STGT_H
|
|
29018U, // STGT_W
|
|
16723U, // STLE_B
|
|
18574U, // STLE_D
|
|
21805U, // STLE_H
|
|
27720U, // STLE_W
|
|
19388U, // STL_D
|
|
28586U, // STL_W
|
|
20010U, // STPTR_D
|
|
28887U, // STPTR_W
|
|
20019U, // STR_D
|
|
28896U, // STR_W
|
|
17903U, // STX_B
|
|
20965U, // STX_D
|
|
23066U, // STX_H
|
|
29411U, // STX_W
|
|
17697U, // ST_B
|
|
20292U, // ST_D
|
|
22574U, // ST_H
|
|
29055U, // ST_W
|
|
18211U, // SUB_D
|
|
27193U, // SUB_W
|
|
23318U, // SYSCALL
|
|
7344U, // TLBCLR
|
|
6943U, // TLBFILL
|
|
6768U, // TLBFLUSH
|
|
4710U, // TLBRD
|
|
6758U, // TLBSRCH
|
|
7374U, // TLBWR
|
|
16697U, // VABSD_B
|
|
24950U, // VABSD_BU
|
|
18497U, // VABSD_D
|
|
25459U, // VABSD_DU
|
|
21779U, // VABSD_H
|
|
25908U, // VABSD_HU
|
|
27694U, // VABSD_W
|
|
26568U, // VABSD_WU
|
|
16431U, // VADDA_B
|
|
18040U, // VADDA_D
|
|
21297U, // VADDA_H
|
|
27033U, // VADDA_W
|
|
25124U, // VADDI_BU
|
|
25520U, // VADDI_DU
|
|
25960U, // VADDI_HU
|
|
26629U, // VADDI_WU
|
|
27457U, // VADDWEV_D_W
|
|
26488U, // VADDWEV_D_WU
|
|
29252U, // VADDWEV_D_WU_W
|
|
16884U, // VADDWEV_H_B
|
|
25073U, // VADDWEV_H_BU
|
|
17774U, // VADDWEV_H_BU_B
|
|
19689U, // VADDWEV_Q_D
|
|
25698U, // VADDWEV_Q_DU
|
|
20369U, // VADDWEV_Q_DU_D
|
|
22984U, // VADDWEV_W_H
|
|
26274U, // VADDWEV_W_HU
|
|
22771U, // VADDWEV_W_HU_H
|
|
27335U, // VADDWOD_D_W
|
|
26427U, // VADDWOD_D_WU
|
|
29200U, // VADDWOD_D_WU_W
|
|
16801U, // VADDWOD_H_B
|
|
25012U, // VADDWOD_H_BU
|
|
17722U, // VADDWOD_H_BU_B
|
|
19608U, // VADDWOD_Q_D
|
|
25637U, // VADDWOD_Q_DU
|
|
20317U, // VADDWOD_Q_DU_D
|
|
22892U, // VADDWOD_W_H
|
|
26213U, // VADDWOD_W_HU
|
|
22719U, // VADDWOD_W_HU_H
|
|
16628U, // VADD_B
|
|
18407U, // VADD_D
|
|
21710U, // VADD_H
|
|
23569U, // VADD_Q
|
|
27606U, // VADD_W
|
|
17003U, // VANDI_B
|
|
26939U, // VANDN_V
|
|
26898U, // VAND_V
|
|
17509U, // VAVGR_B
|
|
25215U, // VAVGR_BU
|
|
19885U, // VAVGR_D
|
|
25744U, // VAVGR_DU
|
|
22360U, // VAVGR_H
|
|
26051U, // VAVGR_HU
|
|
28760U, // VAVGR_W
|
|
26740U, // VAVGR_WU
|
|
16763U, // VAVG_B
|
|
24971U, // VAVG_BU
|
|
18800U, // VAVG_D
|
|
25480U, // VAVG_DU
|
|
21845U, // VAVG_H
|
|
25929U, // VAVG_HU
|
|
27772U, // VAVG_W
|
|
26589U, // VAVG_WU
|
|
17194U, // VBITCLRI_B
|
|
19103U, // VBITCLRI_D
|
|
22074U, // VBITCLRI_H
|
|
28332U, // VBITCLRI_W
|
|
17519U, // VBITCLR_B
|
|
19895U, // VBITCLR_D
|
|
22370U, // VBITCLR_H
|
|
28770U, // VBITCLR_W
|
|
17293U, // VBITREVI_B
|
|
19173U, // VBITREVI_D
|
|
22144U, // VBITREVI_H
|
|
28414U, // VBITREVI_W
|
|
17832U, // VBITREV_B
|
|
20577U, // VBITREV_D
|
|
22829U, // VBITREV_H
|
|
29310U, // VBITREV_W
|
|
33446U, // VBITSELI_B
|
|
26907U, // VBITSEL_V
|
|
17270U, // VBITSETI_B
|
|
19150U, // VBITSETI_D
|
|
22121U, // VBITSETI_H
|
|
28391U, // VBITSETI_W
|
|
17651U, // VBITSET_B
|
|
20141U, // VBITSET_D
|
|
22528U, // VBITSET_H
|
|
28999U, // VBITSET_W
|
|
26919U, // VBSLL_V
|
|
26929U, // VBSRL_V
|
|
17436U, // VCLO_B
|
|
19528U, // VCLO_D
|
|
22287U, // VCLO_H
|
|
28662U, // VCLO_W
|
|
17938U, // VCLZ_B
|
|
20988U, // VCLZ_D
|
|
23089U, // VCLZ_H
|
|
29434U, // VCLZ_W
|
|
17844U, // VDIV_B
|
|
25351U, // VDIV_BU
|
|
20599U, // VDIV_D
|
|
25833U, // VDIV_DU
|
|
22841U, // VDIV_H
|
|
26172U, // VDIV_HU
|
|
29322U, // VDIV_W
|
|
26860U, // VDIV_WU
|
|
25245U, // VEXT2XV_DU_BU
|
|
26081U, // VEXT2XV_DU_HU
|
|
26814U, // VEXT2XV_DU_WU
|
|
16575U, // VEXT2XV_D_B
|
|
21657U, // VEXT2XV_D_H
|
|
27484U, // VEXT2XV_D_W
|
|
25290U, // VEXT2XV_HU_BU
|
|
16911U, // VEXT2XV_H_B
|
|
25335U, // VEXT2XV_WU_BU
|
|
26126U, // VEXT2XV_WU_HU
|
|
17874U, // VEXT2XV_W_B
|
|
23011U, // VEXT2XV_W_H
|
|
26785U, // VEXTH_DU_WU
|
|
27377U, // VEXTH_D_W
|
|
25261U, // VEXTH_HU_BU
|
|
16829U, // VEXTH_H_B
|
|
25775U, // VEXTH_QU_DU
|
|
19636U, // VEXTH_Q_D
|
|
26097U, // VEXTH_WU_HU
|
|
22920U, // VEXTH_W_H
|
|
25789U, // VEXTL_QU_DU
|
|
19648U, // VEXTL_Q_D
|
|
34013U, // VEXTRINS_B
|
|
36491U, // VEXTRINS_D
|
|
38890U, // VEXTRINS_H
|
|
45361U, // VEXTRINS_W
|
|
18345U, // VFADD_D
|
|
23887U, // VFADD_S
|
|
20120U, // VFCLASS_D
|
|
24589U, // VFCLASS_S
|
|
18745U, // VFCMP_CAF_D
|
|
24101U, // VFCMP_CAF_S
|
|
19752U, // VFCMP_CEQ_D
|
|
24470U, // VFCMP_CEQ_S
|
|
18518U, // VFCMP_CLE_D
|
|
23927U, // VFCMP_CLE_S
|
|
20181U, // VFCMP_CLT_D
|
|
24619U, // VFCMP_CLT_S
|
|
18623U, // VFCMP_CNE_D
|
|
24003U, // VFCMP_CNE_S
|
|
19926U, // VFCMP_COR_D
|
|
24553U, // VFCMP_COR_S
|
|
19789U, // VFCMP_CUEQ_D
|
|
24498U, // VFCMP_CUEQ_S
|
|
18583U, // VFCMP_CULE_D
|
|
23973U, // VFCMP_CULE_S
|
|
20218U, // VFCMP_CULT_D
|
|
24647U, // VFCMP_CULT_S
|
|
18665U, // VFCMP_CUNE_D
|
|
24045U, // VFCMP_CUNE_S
|
|
19500U, // VFCMP_CUN_D
|
|
24417U, // VFCMP_CUN_S
|
|
18759U, // VFCMP_SAF_D
|
|
24115U, // VFCMP_SAF_S
|
|
19766U, // VFCMP_SEQ_D
|
|
24484U, // VFCMP_SEQ_S
|
|
18541U, // VFCMP_SLE_D
|
|
23950U, // VFCMP_SLE_S
|
|
20195U, // VFCMP_SLT_D
|
|
24633U, // VFCMP_SLT_S
|
|
18651U, // VFCMP_SNE_D
|
|
24031U, // VFCMP_SNE_S
|
|
19948U, // VFCMP_SOR_D
|
|
24567U, // VFCMP_SOR_S
|
|
19804U, // VFCMP_SUEQ_D
|
|
24513U, // VFCMP_SUEQ_S
|
|
18598U, // VFCMP_SULE_D
|
|
23988U, // VFCMP_SULE_S
|
|
20233U, // VFCMP_SULT_D
|
|
24662U, // VFCMP_SULT_S
|
|
18680U, // VFCMP_SUNE_D
|
|
24060U, // VFCMP_SUNE_S
|
|
19514U, // VFCMP_SUN_D
|
|
24431U, // VFCMP_SUN_S
|
|
23851U, // VFCVTH_D_S
|
|
22471U, // VFCVTH_S_H
|
|
23864U, // VFCVTL_D_S
|
|
22484U, // VFCVTL_S_H
|
|
24137U, // VFCVT_H_S
|
|
20067U, // VFCVT_S_D
|
|
20589U, // VFDIV_D
|
|
24748U, // VFDIV_S
|
|
27363U, // VFFINTH_D_W
|
|
27403U, // VFFINTL_D_W
|
|
23261U, // VFFINT_D_L
|
|
26322U, // VFFINT_D_LU
|
|
23274U, // VFFINT_S_L
|
|
28944U, // VFFINT_S_W
|
|
26751U, // VFFINT_S_WU
|
|
18198U, // VFLOGB_D
|
|
23807U, // VFLOGB_S
|
|
18364U, // VFMADD_D
|
|
23897U, // VFMADD_S
|
|
18080U, // VFMAXA_D
|
|
23785U, // VFMAXA_S
|
|
20929U, // VFMAX_D
|
|
24840U, // VFMAX_S
|
|
18050U, // VFMINA_D
|
|
23774U, // VFMINA_S
|
|
19472U, // VFMIN_D
|
|
24407U, // VFMIN_S
|
|
18229U, // VFMSUB_D
|
|
23828U, // VFMSUB_S
|
|
19406U, // VFMUL_D
|
|
24371U, // VFMUL_S
|
|
18375U, // VFNMADD_D
|
|
23908U, // VFNMADD_S
|
|
18240U, // VFNMSUB_D
|
|
23839U, // VFNMSUB_S
|
|
18695U, // VFRECIPE_D
|
|
24075U, // VFRECIPE_S
|
|
19554U, // VFRECIP_D
|
|
24445U, // VFRECIP_S
|
|
19446U, // VFRINTRM_D
|
|
24381U, // VFRINTRM_S
|
|
18637U, // VFRINTRNE_D
|
|
24017U, // VFRINTRNE_S
|
|
19566U, // VFRINTRP_D
|
|
24457U, // VFRINTRP_S
|
|
21012U, // VFRINTRZ_D
|
|
24866U, // VFRINTRZ_S
|
|
20258U, // VFRINT_D
|
|
24677U, // VFRINT_S
|
|
18708U, // VFRSQRTE_D
|
|
24088U, // VFRSQRTE_S
|
|
20280U, // VFRSQRT_D
|
|
24699U, // VFRSQRT_S
|
|
33534U, // VFRSTPI_B
|
|
38414U, // VFRSTPI_H
|
|
33839U, // VFRSTP_B
|
|
38690U, // VFRSTP_H
|
|
20269U, // VFSQRT_D
|
|
24688U, // VFSQRT_S
|
|
18219U, // VFSUB_D
|
|
23818U, // VFSUB_S
|
|
24212U, // VFTINTH_L_S
|
|
24291U, // VFTINTL_L_S
|
|
24180U, // VFTINTRMH_L_S
|
|
24259U, // VFTINTRML_L_S
|
|
19236U, // VFTINTRM_L_D
|
|
20767U, // VFTINTRM_W_D
|
|
24782U, // VFTINTRM_W_S
|
|
24163U, // VFTINTRNEH_L_S
|
|
24242U, // VFTINTRNEL_L_S
|
|
19220U, // VFTINTRNE_L_D
|
|
20639U, // VFTINTRNE_W_D
|
|
24766U, // VFTINTRNE_W_S
|
|
24196U, // VFTINTRPH_L_S
|
|
24275U, // VFTINTRPL_L_S
|
|
19251U, // VFTINTRP_L_D
|
|
20886U, // VFTINTRP_W_D
|
|
24797U, // VFTINTRP_W_S
|
|
24226U, // VFTINTRZH_L_S
|
|
24305U, // VFTINTRZL_L_S
|
|
20417U, // VFTINTRZ_LU_D
|
|
19279U, // VFTINTRZ_L_D
|
|
24732U, // VFTINTRZ_WU_S
|
|
20914U, // VFTINTRZ_W_D
|
|
24825U, // VFTINTRZ_W_S
|
|
20403U, // VFTINT_LU_D
|
|
19266U, // VFTINT_L_D
|
|
24718U, // VFTINT_WU_S
|
|
20901U, // VFTINT_W_D
|
|
24812U, // VFTINT_W_S
|
|
26845U, // VHADDW_DU_WU
|
|
27534U, // VHADDW_D_W
|
|
25321U, // VHADDW_HU_BU
|
|
16938U, // VHADDW_H_B
|
|
25818U, // VHADDW_QU_DU
|
|
19730U, // VHADDW_Q_D
|
|
26157U, // VHADDW_WU_HU
|
|
23038U, // VHADDW_W_H
|
|
26830U, // VHSUBW_DU_WU
|
|
27521U, // VHSUBW_D_W
|
|
25306U, // VHSUBW_HU_BU
|
|
16925U, // VHSUBW_H_B
|
|
25803U, // VHSUBW_QU_DU
|
|
19717U, // VHSUBW_Q_D
|
|
26142U, // VHSUBW_WU_HU
|
|
23025U, // VHSUBW_W_H
|
|
16960U, // VILVH_B
|
|
18834U, // VILVH_D
|
|
21863U, // VILVH_H
|
|
28061U, // VILVH_W
|
|
17406U, // VILVL_B
|
|
19425U, // VILVL_D
|
|
22257U, // VILVL_H
|
|
28613U, // VILVL_W
|
|
33979U, // VINSGR2VR_B
|
|
36426U, // VINSGR2VR_D
|
|
38830U, // VINSGR2VR_H
|
|
45303U, // VINSGR2VR_W
|
|
21084U, // VLD
|
|
23204U, // VLDI
|
|
17345U, // VLDREPL_B
|
|
19339U, // VLDREPL_D
|
|
22196U, // VLDREPL_H
|
|
28527U, // VLDREPL_W
|
|
29503U, // VLDX
|
|
43826U, // VMADDWEV_D_W
|
|
42856U, // VMADDWEV_D_WU
|
|
45618U, // VMADDWEV_D_WU_W
|
|
33253U, // VMADDWEV_H_B
|
|
41441U, // VMADDWEV_H_BU
|
|
34140U, // VMADDWEV_H_BU_B
|
|
36058U, // VMADDWEV_Q_D
|
|
42066U, // VMADDWEV_Q_DU
|
|
36735U, // VMADDWEV_Q_DU_D
|
|
39353U, // VMADDWEV_W_H
|
|
42642U, // VMADDWEV_W_HU
|
|
39137U, // VMADDWEV_W_HU_H
|
|
43704U, // VMADDWOD_D_W
|
|
42795U, // VMADDWOD_D_WU
|
|
45566U, // VMADDWOD_D_WU_W
|
|
33170U, // VMADDWOD_H_B
|
|
41380U, // VMADDWOD_H_BU
|
|
34088U, // VMADDWOD_H_BU_B
|
|
35977U, // VMADDWOD_Q_D
|
|
42005U, // VMADDWOD_Q_DU
|
|
36683U, // VMADDWOD_Q_DU_D
|
|
39261U, // VMADDWOD_W_H
|
|
42581U, // VMADDWOD_W_HU
|
|
39085U, // VMADDWOD_W_HU_H
|
|
32992U, // VMADD_B
|
|
34771U, // VMADD_D
|
|
38074U, // VMADD_H
|
|
43970U, // VMADD_W
|
|
17306U, // VMAXI_B
|
|
25168U, // VMAXI_BU
|
|
19186U, // VMAXI_D
|
|
25564U, // VMAXI_DU
|
|
22157U, // VMAXI_H
|
|
26004U, // VMAXI_HU
|
|
28427U, // VMAXI_W
|
|
26673U, // VMAXI_WU
|
|
17888U, // VMAX_B
|
|
25361U, // VMAX_BU
|
|
20948U, // VMAX_D
|
|
25853U, // VMAX_DU
|
|
23051U, // VMAX_H
|
|
26304U, // VMAX_HU
|
|
29386U, // VMAX_W
|
|
26880U, // VMAX_WU
|
|
17140U, // VMINI_B
|
|
25146U, // VMINI_BU
|
|
19061U, // VMINI_D
|
|
25542U, // VMINI_DU
|
|
22020U, // VMINI_H
|
|
25982U, // VMINI_HU
|
|
28290U, // VMINI_W
|
|
26651U, // VMINI_WU
|
|
17427U, // VMIN_B
|
|
25190U, // VMIN_BU
|
|
19491U, // VMIN_D
|
|
25596U, // VMIN_DU
|
|
22278U, // VMIN_H
|
|
26026U, // VMIN_HU
|
|
28653U, // VMIN_W
|
|
26714U, // VMIN_WU
|
|
16677U, // VMOD_B
|
|
24940U, // VMOD_BU
|
|
18477U, // VMOD_D
|
|
25449U, // VMOD_DU
|
|
21759U, // VMOD_H
|
|
25898U, // VMOD_HU
|
|
27674U, // VMOD_W
|
|
26558U, // VMOD_WU
|
|
17911U, // VMSKGEZ_B
|
|
17973U, // VMSKLTZ_B
|
|
21032U, // VMSKLTZ_D
|
|
23113U, // VMSKLTZ_H
|
|
29465U, // VMSKLTZ_W
|
|
17947U, // VMSKNZ_B
|
|
32891U, // VMSUB_B
|
|
34636U, // VMSUB_D
|
|
37973U, // VMSUB_H
|
|
43595U, // VMSUB_W
|
|
16951U, // VMUH_B
|
|
25103U, // VMUH_BU
|
|
18817U, // VMUH_D
|
|
25499U, // VMUH_DU
|
|
21854U, // VMUH_H
|
|
25939U, // VMUH_HU
|
|
28052U, // VMUH_W
|
|
26608U, // VMUH_WU
|
|
27471U, // VMULWEV_D_W
|
|
26503U, // VMULWEV_D_WU
|
|
29269U, // VMULWEV_D_WU_W
|
|
16898U, // VMULWEV_H_B
|
|
25088U, // VMULWEV_H_BU
|
|
17791U, // VMULWEV_H_BU_B
|
|
19703U, // VMULWEV_Q_D
|
|
25713U, // VMULWEV_Q_DU
|
|
20386U, // VMULWEV_Q_DU_D
|
|
22998U, // VMULWEV_W_H
|
|
26289U, // VMULWEV_W_HU
|
|
22788U, // VMULWEV_W_HU_H
|
|
27349U, // VMULWOD_D_W
|
|
26442U, // VMULWOD_D_WU
|
|
29217U, // VMULWOD_D_WU_W
|
|
16815U, // VMULWOD_H_B
|
|
25027U, // VMULWOD_H_BU
|
|
17739U, // VMULWOD_H_BU_B
|
|
19622U, // VMULWOD_Q_D
|
|
25652U, // VMULWOD_Q_DU
|
|
20334U, // VMULWOD_Q_DU_D
|
|
22906U, // VMULWOD_W_H
|
|
26228U, // VMULWOD_W_HU
|
|
22736U, // VMULWOD_W_HU_H
|
|
17397U, // VMUL_B
|
|
19416U, // VMUL_D
|
|
22248U, // VMUL_H
|
|
28604U, // VMUL_W
|
|
16754U, // VNEG_B
|
|
18791U, // VNEG_D
|
|
21836U, // VNEG_H
|
|
27763U, // VNEG_W
|
|
17218U, // VNORI_B
|
|
26958U, // VNOR_V
|
|
17228U, // VORI_B
|
|
26949U, // VORN_V
|
|
26967U, // VOR_V
|
|
17808U, // VPACKEV_B
|
|
20553U, // VPACKEV_D
|
|
22805U, // VPACKEV_H
|
|
29286U, // VPACKEV_W
|
|
16653U, // VPACKOD_B
|
|
18453U, // VPACKOD_D
|
|
21735U, // VPACKOD_H
|
|
27650U, // VPACKOD_W
|
|
17688U, // VPCNT_B
|
|
20248U, // VPCNT_D
|
|
22565U, // VPCNT_H
|
|
29036U, // VPCNT_W
|
|
44663U, // VPERMI_W
|
|
17820U, // VPICKEV_B
|
|
20565U, // VPICKEV_D
|
|
22817U, // VPICKEV_H
|
|
29298U, // VPICKEV_W
|
|
16665U, // VPICKOD_B
|
|
18465U, // VPICKOD_D
|
|
21747U, // VPICKOD_H
|
|
27662U, // VPICKOD_W
|
|
17494U, // VPICKVE2GR_B
|
|
25199U, // VPICKVE2GR_BU
|
|
19858U, // VPICKVE2GR_D
|
|
25728U, // VPICKVE2GR_DU
|
|
22345U, // VPICKVE2GR_H
|
|
26035U, // VPICKVE2GR_HU
|
|
28745U, // VPICKVE2GR_W
|
|
26724U, // VPICKVE2GR_WU
|
|
17581U, // VREPLGR2VR_B
|
|
20027U, // VREPLGR2VR_D
|
|
22432U, // VREPLGR2VR_H
|
|
28904U, // VREPLGR2VR_W
|
|
17038U, // VREPLVEI_B
|
|
18950U, // VREPLVEI_D
|
|
21931U, // VREPLVEI_H
|
|
28168U, // VREPLVEI_W
|
|
16732U, // VREPLVE_B
|
|
18733U, // VREPLVE_D
|
|
21814U, // VREPLVE_H
|
|
27741U, // VREPLVE_W
|
|
17259U, // VROTRI_B
|
|
19139U, // VROTRI_D
|
|
22110U, // VROTRI_H
|
|
28380U, // VROTRI_W
|
|
17571U, // VROTR_B
|
|
19992U, // VROTR_D
|
|
22422U, // VROTR_H
|
|
28869U, // VROTR_W
|
|
16618U, // VSADD_B
|
|
24922U, // VSADD_BU
|
|
18397U, // VSADD_D
|
|
25438U, // VSADD_DU
|
|
21700U, // VSADD_H
|
|
25880U, // VSADD_HU
|
|
27596U, // VSADD_W
|
|
26540U, // VSADD_WU
|
|
17642U, // VSAT_B
|
|
25226U, // VSAT_BU
|
|
20132U, // VSAT_D
|
|
25755U, // VSAT_DU
|
|
22519U, // VSAT_H
|
|
26062U, // VSAT_HU
|
|
28990U, // VSAT_W
|
|
26765U, // VSAT_WU
|
|
17162U, // VSEQI_B
|
|
19071U, // VSEQI_D
|
|
22042U, // VSEQI_H
|
|
28300U, // VSEQI_W
|
|
17466U, // VSEQ_B
|
|
19780U, // VSEQ_D
|
|
22317U, // VSEQ_H
|
|
28697U, // VSEQ_W
|
|
17923U, // VSETALLNEZ_B
|
|
20973U, // VSETALLNEZ_D
|
|
23074U, // VSETALLNEZ_H
|
|
29419U, // VSETALLNEZ_W
|
|
17958U, // VSETANYEQZ_B
|
|
20997U, // VSETANYEQZ_D
|
|
23098U, // VSETANYEQZ_H
|
|
29443U, // VSETANYEQZ_W
|
|
26996U, // VSETEQZ_V
|
|
26984U, // VSETNEZ_V
|
|
16970U, // VSHUF4I_B
|
|
35257U, // VSHUF4I_D
|
|
21873U, // VSHUF4I_H
|
|
28091U, // VSHUF4I_W
|
|
16744U, // VSHUF_B
|
|
35157U, // VSHUF_D
|
|
38210U, // VSHUF_H
|
|
44137U, // VSHUF_W
|
|
17853U, // VSIGNCOV_B
|
|
20608U, // VSIGNCOV_D
|
|
22850U, // VSIGNCOV_H
|
|
29331U, // VSIGNCOV_W
|
|
17013U, // VSLEI_B
|
|
25135U, // VSLEI_BU
|
|
18925U, // VSLEI_D
|
|
25531U, // VSLEI_DU
|
|
21906U, // VSLEI_H
|
|
25971U, // VSLEI_HU
|
|
28143U, // VSLEI_W
|
|
26640U, // VSLEI_WU
|
|
16715U, // VSLE_B
|
|
24961U, // VSLE_BU
|
|
18555U, // VSLE_D
|
|
25470U, // VSLE_DU
|
|
21797U, // VSLE_H
|
|
25919U, // VSLE_HU
|
|
27712U, // VSLE_W
|
|
26579U, // VSLE_WU
|
|
17086U, // VSLLI_B
|
|
18996U, // VSLLI_D
|
|
21966U, // VSLLI_H
|
|
28214U, // VSLLI_W
|
|
26799U, // VSLLWIL_DU_WU
|
|
27389U, // VSLLWIL_D_W
|
|
25275U, // VSLLWIL_HU_BU
|
|
16841U, // VSLLWIL_H_B
|
|
26111U, // VSLLWIL_WU_HU
|
|
22932U, // VSLLWIL_W_H
|
|
17336U, // VSLL_B
|
|
19330U, // VSLL_D
|
|
22187U, // VSLL_H
|
|
28518U, // VSLL_W
|
|
17283U, // VSLTI_B
|
|
25157U, // VSLTI_BU
|
|
19163U, // VSLTI_D
|
|
25553U, // VSLTI_DU
|
|
22134U, // VSLTI_H
|
|
25993U, // VSLTI_HU
|
|
28404U, // VSLTI_W
|
|
26662U, // VSLTI_WU
|
|
17679U, // VSLT_B
|
|
25236U, // VSLT_BU
|
|
20209U, // VSLT_D
|
|
25765U, // VSLT_DU
|
|
22556U, // VSLT_H
|
|
26072U, // VSLT_HU
|
|
29027U, // VSLT_W
|
|
26775U, // VSLT_WU
|
|
16993U, // VSRAI_B
|
|
18907U, // VSRAI_D
|
|
21896U, // VSRAI_H
|
|
28125U, // VSRAI_W
|
|
37724U, // VSRANI_B_H
|
|
39855U, // VSRANI_D_Q
|
|
44179U, // VSRANI_H_W
|
|
37053U, // VSRANI_W_D
|
|
21451U, // VSRAN_B_H
|
|
27906U, // VSRAN_H_W
|
|
20795U, // VSRAN_W_D
|
|
17172U, // VSRARI_B
|
|
19081U, // VSRARI_D
|
|
22052U, // VSRARI_H
|
|
28310U, // VSRARI_W
|
|
37779U, // VSRARNI_B_H
|
|
39910U, // VSRARNI_D_Q
|
|
44234U, // VSRARNI_H_W
|
|
37108U, // VSRARNI_W_D
|
|
21502U, // VSRARN_B_H
|
|
27957U, // VSRARN_H_W
|
|
20846U, // VSRARN_W_D
|
|
17475U, // VSRAR_B
|
|
19819U, // VSRAR_D
|
|
22326U, // VSRAR_H
|
|
28706U, // VSRAR_W
|
|
16451U, // VSRA_B
|
|
18071U, // VSRA_D
|
|
21317U, // VSRA_H
|
|
27063U, // VSRA_W
|
|
17118U, // VSRLI_B
|
|
19028U, // VSRLI_D
|
|
21998U, // VSRLI_H
|
|
28257U, // VSRLI_W
|
|
37751U, // VSRLNI_B_H
|
|
39882U, // VSRLNI_D_Q
|
|
44206U, // VSRLNI_H_W
|
|
37080U, // VSRLNI_W_D
|
|
21476U, // VSRLN_B_H
|
|
27931U, // VSRLN_H_W
|
|
20820U, // VSRLN_W_D
|
|
17207U, // VSRLRI_B
|
|
19116U, // VSRLRI_D
|
|
22087U, // VSRLRI_H
|
|
28345U, // VSRLRI_W
|
|
37808U, // VSRLRNI_B_H
|
|
39939U, // VSRLRNI_D_Q
|
|
44263U, // VSRLRNI_H_W
|
|
37137U, // VSRLRNI_W_D
|
|
21529U, // VSRLRN_B_H
|
|
27984U, // VSRLRN_H_W
|
|
20873U, // VSRLRN_W_D
|
|
17531U, // VSRLR_B
|
|
19907U, // VSRLR_D
|
|
22382U, // VSRLR_H
|
|
28782U, // VSRLR_W
|
|
17367U, // VSRL_B
|
|
19361U, // VSRL_D
|
|
22218U, // VSRL_H
|
|
28559U, // VSRL_W
|
|
38965U, // VSSRANI_BU_H
|
|
37710U, // VSSRANI_B_H
|
|
39973U, // VSSRANI_DU_Q
|
|
39841U, // VSSRANI_D_Q
|
|
45446U, // VSSRANI_HU_W
|
|
44165U, // VSSRANI_H_W
|
|
36817U, // VSSRANI_WU_D
|
|
37039U, // VSSRANI_W_D
|
|
22643U, // VSSRAN_BU_H
|
|
21438U, // VSSRAN_B_H
|
|
29124U, // VSSRAN_HU_W
|
|
27893U, // VSSRAN_H_W
|
|
20495U, // VSSRAN_WU_D
|
|
20782U, // VSSRAN_W_D
|
|
38995U, // VSSRARNI_BU_H
|
|
37764U, // VSSRARNI_B_H
|
|
40003U, // VSSRARNI_DU_Q
|
|
39895U, // VSSRARNI_D_Q
|
|
45476U, // VSSRARNI_HU_W
|
|
44219U, // VSSRARNI_H_W
|
|
36847U, // VSSRARNI_WU_D
|
|
37093U, // VSSRARNI_W_D
|
|
22671U, // VSSRARN_BU_H
|
|
21488U, // VSSRARN_B_H
|
|
29152U, // VSSRARN_HU_W
|
|
27943U, // VSSRARN_H_W
|
|
20523U, // VSSRARN_WU_D
|
|
20832U, // VSSRARN_W_D
|
|
38980U, // VSSRLNI_BU_H
|
|
37737U, // VSSRLNI_B_H
|
|
39988U, // VSSRLNI_DU_Q
|
|
39868U, // VSSRLNI_D_Q
|
|
45461U, // VSSRLNI_HU_W
|
|
44192U, // VSSRLNI_H_W
|
|
36832U, // VSSRLNI_WU_D
|
|
37066U, // VSSRLNI_W_D
|
|
22657U, // VSSRLN_BU_H
|
|
21463U, // VSSRLN_B_H
|
|
29138U, // VSSRLN_HU_W
|
|
27918U, // VSSRLN_H_W
|
|
20509U, // VSSRLN_WU_D
|
|
20807U, // VSSRLN_W_D
|
|
39011U, // VSSRLRNI_BU_H
|
|
37793U, // VSSRLRNI_B_H
|
|
40019U, // VSSRLRNI_DU_Q
|
|
39924U, // VSSRLRNI_D_Q
|
|
45492U, // VSSRLRNI_HU_W
|
|
44248U, // VSSRLRNI_H_W
|
|
36863U, // VSSRLRNI_WU_D
|
|
37122U, // VSSRLRNI_W_D
|
|
22686U, // VSSRLRN_BU_H
|
|
21515U, // VSSRLRN_B_H
|
|
29167U, // VSSRLRN_HU_W
|
|
27970U, // VSSRLRN_H_W
|
|
20538U, // VSSRLRN_WU_D
|
|
20859U, // VSSRLRN_W_D
|
|
16517U, // VSSUB_B
|
|
24911U, // VSSUB_BU
|
|
18262U, // VSSUB_D
|
|
25416U, // VSSUB_DU
|
|
21599U, // VSSUB_H
|
|
25869U, // VSSUB_HU
|
|
27221U, // VSSUB_W
|
|
26385U, // VSSUB_WU
|
|
24905U, // VST
|
|
17416U, // VSTELM_B
|
|
19435U, // VSTELM_D
|
|
22267U, // VSTELM_H
|
|
28623U, // VSTELM_W
|
|
29510U, // VSTX
|
|
25113U, // VSUBI_BU
|
|
25509U, // VSUBI_DU
|
|
25949U, // VSUBI_HU
|
|
26618U, // VSUBI_WU
|
|
27428U, // VSUBWEV_D_W
|
|
26457U, // VSUBWEV_D_WU
|
|
16855U, // VSUBWEV_H_B
|
|
25042U, // VSUBWEV_H_BU
|
|
19660U, // VSUBWEV_Q_D
|
|
25667U, // VSUBWEV_Q_DU
|
|
22955U, // VSUBWEV_W_H
|
|
26243U, // VSUBWEV_W_HU
|
|
27306U, // VSUBWOD_D_W
|
|
26396U, // VSUBWOD_D_WU
|
|
16772U, // VSUBWOD_H_B
|
|
24981U, // VSUBWOD_H_BU
|
|
19579U, // VSUBWOD_Q_D
|
|
25606U, // VSUBWOD_Q_DU
|
|
22863U, // VSUBWOD_W_H
|
|
26182U, // VSUBWOD_W_HU
|
|
16527U, // VSUB_B
|
|
18272U, // VSUB_D
|
|
21609U, // VSUB_H
|
|
23442U, // VSUB_Q
|
|
27231U, // VSUB_W
|
|
17237U, // VXORI_B
|
|
26975U, // VXOR_V
|
|
16545U, // X86ADC_B
|
|
18298U, // X86ADC_D
|
|
21627U, // X86ADC_H
|
|
27259U, // X86ADC_W
|
|
16588U, // X86ADD_B
|
|
18334U, // X86ADD_D
|
|
25426U, // X86ADD_DU
|
|
21670U, // X86ADD_H
|
|
27556U, // X86ADD_W
|
|
26528U, // X86ADD_WU
|
|
16642U, // X86AND_B
|
|
18433U, // X86AND_D
|
|
21724U, // X86AND_H
|
|
27620U, // X86AND_W
|
|
6958U, // X86CLRTM
|
|
7002U, // X86DECTOP
|
|
16555U, // X86DEC_B
|
|
18308U, // X86DEC_D
|
|
21637U, // X86DEC_H
|
|
27279U, // X86DEC_W
|
|
7013U, // X86INCTOP
|
|
16565U, // X86INC_B
|
|
18318U, // X86INC_D
|
|
21647U, // X86INC_H
|
|
27289U, // X86INC_W
|
|
21210U, // X86MFFLAG
|
|
23408U, // X86MFTOP
|
|
21232U, // X86MTFLAG
|
|
23418U, // X86MTTOP
|
|
17386U, // X86MUL_B
|
|
25178U, // X86MUL_BU
|
|
19395U, // X86MUL_D
|
|
25574U, // X86MUL_DU
|
|
22237U, // X86MUL_H
|
|
26014U, // X86MUL_HU
|
|
28593U, // X86MUL_W
|
|
26692U, // X86MUL_WU
|
|
17540U, // X86OR_B
|
|
19916U, // X86OR_D
|
|
22391U, // X86OR_H
|
|
28791U, // X86OR_W
|
|
17050U, // X86RCLI_B
|
|
18962U, // X86RCLI_D
|
|
21943U, // X86RCLI_H
|
|
28180U, // X86RCLI_W
|
|
17315U, // X86RCL_B
|
|
19293U, // X86RCL_D
|
|
22166U, // X86RCL_H
|
|
28460U, // X86RCL_W
|
|
17182U, // X86RCRI_B
|
|
19091U, // X86RCRI_D
|
|
22062U, // X86RCRI_H
|
|
28320U, // X86RCRI_W
|
|
17484U, // X86RCR_B
|
|
19828U, // X86RCR_D
|
|
22335U, // X86RCR_H
|
|
28715U, // X86RCR_W
|
|
17127U, // X86ROTLI_B
|
|
19037U, // X86ROTLI_D
|
|
22007U, // X86ROTLI_H
|
|
28266U, // X86ROTLI_W
|
|
17375U, // X86ROTL_B
|
|
19377U, // X86ROTL_D
|
|
22226U, // X86ROTL_H
|
|
28575U, // X86ROTL_W
|
|
17246U, // X86ROTRI_B
|
|
19126U, // X86ROTRI_D
|
|
22097U, // X86ROTRI_H
|
|
28355U, // X86ROTRI_W
|
|
17559U, // X86ROTR_B
|
|
19980U, // X86ROTR_D
|
|
22410U, // X86ROTR_H
|
|
28846U, // X86ROTR_W
|
|
16535U, // X86SBC_B
|
|
18288U, // X86SBC_D
|
|
21617U, // X86SBC_H
|
|
27239U, // X86SBC_W
|
|
21254U, // X86SETTAG
|
|
6968U, // X86SETTM
|
|
17074U, // X86SLLI_B
|
|
18984U, // X86SLLI_D
|
|
21954U, // X86SLLI_H
|
|
28191U, // X86SLLI_W
|
|
17325U, // X86SLL_B
|
|
19319U, // X86SLL_D
|
|
22176U, // X86SLL_H
|
|
28497U, // X86SLL_W
|
|
16981U, // X86SRAI_B
|
|
18895U, // X86SRAI_D
|
|
21884U, // X86SRAI_H
|
|
28102U, // X86SRAI_W
|
|
16440U, // X86SRA_B
|
|
18060U, // X86SRA_D
|
|
21306U, // X86SRA_H
|
|
27042U, // X86SRA_W
|
|
17106U, // X86SRLI_B
|
|
19016U, // X86SRLI_D
|
|
21986U, // X86SRLI_H
|
|
28234U, // X86SRLI_W
|
|
17356U, // X86SRL_B
|
|
19350U, // X86SRL_D
|
|
22207U, // X86SRL_H
|
|
28538U, // X86SRL_W
|
|
16496U, // X86SUB_B
|
|
18208U, // X86SUB_D
|
|
25404U, // X86SUB_DU
|
|
21578U, // X86SUB_H
|
|
27190U, // X86SUB_W
|
|
26373U, // X86SUB_WU
|
|
17549U, // X86XOR_B
|
|
19961U, // X86XOR_D
|
|
22400U, // X86XOR_H
|
|
28817U, // X86XOR_W
|
|
23741U, // XOR
|
|
23216U, // XORI
|
|
16696U, // XVABSD_B
|
|
24949U, // XVABSD_BU
|
|
18496U, // XVABSD_D
|
|
25458U, // XVABSD_DU
|
|
21778U, // XVABSD_H
|
|
25907U, // XVABSD_HU
|
|
27693U, // XVABSD_W
|
|
26567U, // XVABSD_WU
|
|
16430U, // XVADDA_B
|
|
18039U, // XVADDA_D
|
|
21296U, // XVADDA_H
|
|
27032U, // XVADDA_W
|
|
25123U, // XVADDI_BU
|
|
25519U, // XVADDI_DU
|
|
25959U, // XVADDI_HU
|
|
26628U, // XVADDI_WU
|
|
27456U, // XVADDWEV_D_W
|
|
26487U, // XVADDWEV_D_WU
|
|
29251U, // XVADDWEV_D_WU_W
|
|
16883U, // XVADDWEV_H_B
|
|
25072U, // XVADDWEV_H_BU
|
|
17773U, // XVADDWEV_H_BU_B
|
|
19688U, // XVADDWEV_Q_D
|
|
25697U, // XVADDWEV_Q_DU
|
|
20368U, // XVADDWEV_Q_DU_D
|
|
22983U, // XVADDWEV_W_H
|
|
26273U, // XVADDWEV_W_HU
|
|
22770U, // XVADDWEV_W_HU_H
|
|
27334U, // XVADDWOD_D_W
|
|
26426U, // XVADDWOD_D_WU
|
|
29199U, // XVADDWOD_D_WU_W
|
|
16800U, // XVADDWOD_H_B
|
|
25011U, // XVADDWOD_H_BU
|
|
17721U, // XVADDWOD_H_BU_B
|
|
19607U, // XVADDWOD_Q_D
|
|
25636U, // XVADDWOD_Q_DU
|
|
20316U, // XVADDWOD_Q_DU_D
|
|
22891U, // XVADDWOD_W_H
|
|
26212U, // XVADDWOD_W_HU
|
|
22718U, // XVADDWOD_W_HU_H
|
|
16627U, // XVADD_B
|
|
18406U, // XVADD_D
|
|
21709U, // XVADD_H
|
|
23568U, // XVADD_Q
|
|
27605U, // XVADD_W
|
|
17002U, // XVANDI_B
|
|
26938U, // XVANDN_V
|
|
26897U, // XVAND_V
|
|
17508U, // XVAVGR_B
|
|
25214U, // XVAVGR_BU
|
|
19884U, // XVAVGR_D
|
|
25743U, // XVAVGR_DU
|
|
22359U, // XVAVGR_H
|
|
26050U, // XVAVGR_HU
|
|
28759U, // XVAVGR_W
|
|
26739U, // XVAVGR_WU
|
|
16762U, // XVAVG_B
|
|
24970U, // XVAVG_BU
|
|
18799U, // XVAVG_D
|
|
25479U, // XVAVG_DU
|
|
21844U, // XVAVG_H
|
|
25928U, // XVAVG_HU
|
|
27771U, // XVAVG_W
|
|
26588U, // XVAVG_WU
|
|
17193U, // XVBITCLRI_B
|
|
19102U, // XVBITCLRI_D
|
|
22073U, // XVBITCLRI_H
|
|
28331U, // XVBITCLRI_W
|
|
17518U, // XVBITCLR_B
|
|
19894U, // XVBITCLR_D
|
|
22369U, // XVBITCLR_H
|
|
28769U, // XVBITCLR_W
|
|
17292U, // XVBITREVI_B
|
|
19172U, // XVBITREVI_D
|
|
22143U, // XVBITREVI_H
|
|
28413U, // XVBITREVI_W
|
|
17831U, // XVBITREV_B
|
|
20576U, // XVBITREV_D
|
|
22828U, // XVBITREV_H
|
|
29309U, // XVBITREV_W
|
|
33445U, // XVBITSELI_B
|
|
26906U, // XVBITSEL_V
|
|
17269U, // XVBITSETI_B
|
|
19149U, // XVBITSETI_D
|
|
22120U, // XVBITSETI_H
|
|
28390U, // XVBITSETI_W
|
|
17650U, // XVBITSET_B
|
|
20140U, // XVBITSET_D
|
|
22527U, // XVBITSET_H
|
|
28998U, // XVBITSET_W
|
|
26918U, // XVBSLL_V
|
|
26928U, // XVBSRL_V
|
|
17435U, // XVCLO_B
|
|
19527U, // XVCLO_D
|
|
22286U, // XVCLO_H
|
|
28661U, // XVCLO_W
|
|
17937U, // XVCLZ_B
|
|
20987U, // XVCLZ_D
|
|
23088U, // XVCLZ_H
|
|
29433U, // XVCLZ_W
|
|
17843U, // XVDIV_B
|
|
25350U, // XVDIV_BU
|
|
20598U, // XVDIV_D
|
|
25832U, // XVDIV_DU
|
|
22840U, // XVDIV_H
|
|
26171U, // XVDIV_HU
|
|
29321U, // XVDIV_W
|
|
26859U, // XVDIV_WU
|
|
26784U, // XVEXTH_DU_WU
|
|
27376U, // XVEXTH_D_W
|
|
25260U, // XVEXTH_HU_BU
|
|
16828U, // XVEXTH_H_B
|
|
25774U, // XVEXTH_QU_DU
|
|
19635U, // XVEXTH_Q_D
|
|
26096U, // XVEXTH_WU_HU
|
|
22919U, // XVEXTH_W_H
|
|
25788U, // XVEXTL_QU_DU
|
|
19647U, // XVEXTL_Q_D
|
|
34012U, // XVEXTRINS_B
|
|
36490U, // XVEXTRINS_D
|
|
38889U, // XVEXTRINS_H
|
|
45360U, // XVEXTRINS_W
|
|
18344U, // XVFADD_D
|
|
23886U, // XVFADD_S
|
|
20119U, // XVFCLASS_D
|
|
24588U, // XVFCLASS_S
|
|
18744U, // XVFCMP_CAF_D
|
|
24100U, // XVFCMP_CAF_S
|
|
19751U, // XVFCMP_CEQ_D
|
|
24469U, // XVFCMP_CEQ_S
|
|
18517U, // XVFCMP_CLE_D
|
|
23926U, // XVFCMP_CLE_S
|
|
20180U, // XVFCMP_CLT_D
|
|
24618U, // XVFCMP_CLT_S
|
|
18622U, // XVFCMP_CNE_D
|
|
24002U, // XVFCMP_CNE_S
|
|
19925U, // XVFCMP_COR_D
|
|
24552U, // XVFCMP_COR_S
|
|
19788U, // XVFCMP_CUEQ_D
|
|
24497U, // XVFCMP_CUEQ_S
|
|
18582U, // XVFCMP_CULE_D
|
|
23972U, // XVFCMP_CULE_S
|
|
20217U, // XVFCMP_CULT_D
|
|
24646U, // XVFCMP_CULT_S
|
|
18664U, // XVFCMP_CUNE_D
|
|
24044U, // XVFCMP_CUNE_S
|
|
19499U, // XVFCMP_CUN_D
|
|
24416U, // XVFCMP_CUN_S
|
|
18758U, // XVFCMP_SAF_D
|
|
24114U, // XVFCMP_SAF_S
|
|
19765U, // XVFCMP_SEQ_D
|
|
24483U, // XVFCMP_SEQ_S
|
|
18540U, // XVFCMP_SLE_D
|
|
23949U, // XVFCMP_SLE_S
|
|
20194U, // XVFCMP_SLT_D
|
|
24632U, // XVFCMP_SLT_S
|
|
18650U, // XVFCMP_SNE_D
|
|
24030U, // XVFCMP_SNE_S
|
|
19947U, // XVFCMP_SOR_D
|
|
24566U, // XVFCMP_SOR_S
|
|
19803U, // XVFCMP_SUEQ_D
|
|
24512U, // XVFCMP_SUEQ_S
|
|
18597U, // XVFCMP_SULE_D
|
|
23987U, // XVFCMP_SULE_S
|
|
20232U, // XVFCMP_SULT_D
|
|
24661U, // XVFCMP_SULT_S
|
|
18679U, // XVFCMP_SUNE_D
|
|
24059U, // XVFCMP_SUNE_S
|
|
19513U, // XVFCMP_SUN_D
|
|
24430U, // XVFCMP_SUN_S
|
|
23850U, // XVFCVTH_D_S
|
|
22470U, // XVFCVTH_S_H
|
|
23863U, // XVFCVTL_D_S
|
|
22483U, // XVFCVTL_S_H
|
|
24136U, // XVFCVT_H_S
|
|
20066U, // XVFCVT_S_D
|
|
20588U, // XVFDIV_D
|
|
24747U, // XVFDIV_S
|
|
27362U, // XVFFINTH_D_W
|
|
27402U, // XVFFINTL_D_W
|
|
23260U, // XVFFINT_D_L
|
|
26321U, // XVFFINT_D_LU
|
|
23273U, // XVFFINT_S_L
|
|
28943U, // XVFFINT_S_W
|
|
26750U, // XVFFINT_S_WU
|
|
18197U, // XVFLOGB_D
|
|
23806U, // XVFLOGB_S
|
|
18363U, // XVFMADD_D
|
|
23896U, // XVFMADD_S
|
|
18079U, // XVFMAXA_D
|
|
23784U, // XVFMAXA_S
|
|
20928U, // XVFMAX_D
|
|
24839U, // XVFMAX_S
|
|
18049U, // XVFMINA_D
|
|
23773U, // XVFMINA_S
|
|
19471U, // XVFMIN_D
|
|
24406U, // XVFMIN_S
|
|
18228U, // XVFMSUB_D
|
|
23827U, // XVFMSUB_S
|
|
19405U, // XVFMUL_D
|
|
24370U, // XVFMUL_S
|
|
18374U, // XVFNMADD_D
|
|
23907U, // XVFNMADD_S
|
|
18239U, // XVFNMSUB_D
|
|
23838U, // XVFNMSUB_S
|
|
18694U, // XVFRECIPE_D
|
|
24074U, // XVFRECIPE_S
|
|
19553U, // XVFRECIP_D
|
|
24444U, // XVFRECIP_S
|
|
19445U, // XVFRINTRM_D
|
|
24380U, // XVFRINTRM_S
|
|
18636U, // XVFRINTRNE_D
|
|
24016U, // XVFRINTRNE_S
|
|
19565U, // XVFRINTRP_D
|
|
24456U, // XVFRINTRP_S
|
|
21011U, // XVFRINTRZ_D
|
|
24865U, // XVFRINTRZ_S
|
|
20257U, // XVFRINT_D
|
|
24676U, // XVFRINT_S
|
|
18707U, // XVFRSQRTE_D
|
|
24087U, // XVFRSQRTE_S
|
|
20279U, // XVFRSQRT_D
|
|
24698U, // XVFRSQRT_S
|
|
33533U, // XVFRSTPI_B
|
|
38413U, // XVFRSTPI_H
|
|
33838U, // XVFRSTP_B
|
|
38689U, // XVFRSTP_H
|
|
20268U, // XVFSQRT_D
|
|
24687U, // XVFSQRT_S
|
|
18218U, // XVFSUB_D
|
|
23817U, // XVFSUB_S
|
|
24211U, // XVFTINTH_L_S
|
|
24290U, // XVFTINTL_L_S
|
|
24179U, // XVFTINTRMH_L_S
|
|
24258U, // XVFTINTRML_L_S
|
|
19235U, // XVFTINTRM_L_D
|
|
20766U, // XVFTINTRM_W_D
|
|
24781U, // XVFTINTRM_W_S
|
|
24162U, // XVFTINTRNEH_L_S
|
|
24241U, // XVFTINTRNEL_L_S
|
|
19219U, // XVFTINTRNE_L_D
|
|
20638U, // XVFTINTRNE_W_D
|
|
24765U, // XVFTINTRNE_W_S
|
|
24195U, // XVFTINTRPH_L_S
|
|
24274U, // XVFTINTRPL_L_S
|
|
19250U, // XVFTINTRP_L_D
|
|
20885U, // XVFTINTRP_W_D
|
|
24796U, // XVFTINTRP_W_S
|
|
24225U, // XVFTINTRZH_L_S
|
|
24304U, // XVFTINTRZL_L_S
|
|
20416U, // XVFTINTRZ_LU_D
|
|
19278U, // XVFTINTRZ_L_D
|
|
24731U, // XVFTINTRZ_WU_S
|
|
20913U, // XVFTINTRZ_W_D
|
|
24824U, // XVFTINTRZ_W_S
|
|
20402U, // XVFTINT_LU_D
|
|
19265U, // XVFTINT_L_D
|
|
24717U, // XVFTINT_WU_S
|
|
20900U, // XVFTINT_W_D
|
|
24811U, // XVFTINT_W_S
|
|
26844U, // XVHADDW_DU_WU
|
|
27533U, // XVHADDW_D_W
|
|
25320U, // XVHADDW_HU_BU
|
|
16937U, // XVHADDW_H_B
|
|
25817U, // XVHADDW_QU_DU
|
|
19729U, // XVHADDW_Q_D
|
|
26156U, // XVHADDW_WU_HU
|
|
23037U, // XVHADDW_W_H
|
|
18973U, // XVHSELI_D
|
|
26829U, // XVHSUBW_DU_WU
|
|
27520U, // XVHSUBW_D_W
|
|
25305U, // XVHSUBW_HU_BU
|
|
16924U, // XVHSUBW_H_B
|
|
25802U, // XVHSUBW_QU_DU
|
|
19716U, // XVHSUBW_Q_D
|
|
26141U, // XVHSUBW_WU_HU
|
|
23024U, // XVHSUBW_W_H
|
|
16959U, // XVILVH_B
|
|
18833U, // XVILVH_D
|
|
21862U, // XVILVH_H
|
|
28060U, // XVILVH_W
|
|
17405U, // XVILVL_B
|
|
19424U, // XVILVL_D
|
|
22256U, // XVILVL_H
|
|
28612U, // XVILVL_W
|
|
36425U, // XVINSGR2VR_D
|
|
45302U, // XVINSGR2VR_W
|
|
34411U, // XVINSVE0_D
|
|
43404U, // XVINSVE0_W
|
|
21083U, // XVLD
|
|
23203U, // XVLDI
|
|
17344U, // XVLDREPL_B
|
|
19338U, // XVLDREPL_D
|
|
22195U, // XVLDREPL_H
|
|
28526U, // XVLDREPL_W
|
|
29502U, // XVLDX
|
|
43825U, // XVMADDWEV_D_W
|
|
42855U, // XVMADDWEV_D_WU
|
|
45617U, // XVMADDWEV_D_WU_W
|
|
33252U, // XVMADDWEV_H_B
|
|
41440U, // XVMADDWEV_H_BU
|
|
34139U, // XVMADDWEV_H_BU_B
|
|
36057U, // XVMADDWEV_Q_D
|
|
42065U, // XVMADDWEV_Q_DU
|
|
36734U, // XVMADDWEV_Q_DU_D
|
|
39352U, // XVMADDWEV_W_H
|
|
42641U, // XVMADDWEV_W_HU
|
|
39136U, // XVMADDWEV_W_HU_H
|
|
43703U, // XVMADDWOD_D_W
|
|
42794U, // XVMADDWOD_D_WU
|
|
45565U, // XVMADDWOD_D_WU_W
|
|
33169U, // XVMADDWOD_H_B
|
|
41379U, // XVMADDWOD_H_BU
|
|
34087U, // XVMADDWOD_H_BU_B
|
|
35976U, // XVMADDWOD_Q_D
|
|
42004U, // XVMADDWOD_Q_DU
|
|
36682U, // XVMADDWOD_Q_DU_D
|
|
39260U, // XVMADDWOD_W_H
|
|
42580U, // XVMADDWOD_W_HU
|
|
39084U, // XVMADDWOD_W_HU_H
|
|
32991U, // XVMADD_B
|
|
34770U, // XVMADD_D
|
|
38073U, // XVMADD_H
|
|
43969U, // XVMADD_W
|
|
17305U, // XVMAXI_B
|
|
25167U, // XVMAXI_BU
|
|
19185U, // XVMAXI_D
|
|
25563U, // XVMAXI_DU
|
|
22156U, // XVMAXI_H
|
|
26003U, // XVMAXI_HU
|
|
28426U, // XVMAXI_W
|
|
26672U, // XVMAXI_WU
|
|
17887U, // XVMAX_B
|
|
25360U, // XVMAX_BU
|
|
20947U, // XVMAX_D
|
|
25852U, // XVMAX_DU
|
|
23050U, // XVMAX_H
|
|
26303U, // XVMAX_HU
|
|
29385U, // XVMAX_W
|
|
26879U, // XVMAX_WU
|
|
17139U, // XVMINI_B
|
|
25145U, // XVMINI_BU
|
|
19060U, // XVMINI_D
|
|
25541U, // XVMINI_DU
|
|
22019U, // XVMINI_H
|
|
25981U, // XVMINI_HU
|
|
28289U, // XVMINI_W
|
|
26650U, // XVMINI_WU
|
|
17426U, // XVMIN_B
|
|
25189U, // XVMIN_BU
|
|
19490U, // XVMIN_D
|
|
25595U, // XVMIN_DU
|
|
22277U, // XVMIN_H
|
|
26025U, // XVMIN_HU
|
|
28652U, // XVMIN_W
|
|
26713U, // XVMIN_WU
|
|
16676U, // XVMOD_B
|
|
24939U, // XVMOD_BU
|
|
18476U, // XVMOD_D
|
|
25448U, // XVMOD_DU
|
|
21758U, // XVMOD_H
|
|
25897U, // XVMOD_HU
|
|
27673U, // XVMOD_W
|
|
26557U, // XVMOD_WU
|
|
17910U, // XVMSKGEZ_B
|
|
17972U, // XVMSKLTZ_B
|
|
21031U, // XVMSKLTZ_D
|
|
23112U, // XVMSKLTZ_H
|
|
29464U, // XVMSKLTZ_W
|
|
17946U, // XVMSKNZ_B
|
|
32890U, // XVMSUB_B
|
|
34635U, // XVMSUB_D
|
|
37972U, // XVMSUB_H
|
|
43594U, // XVMSUB_W
|
|
16950U, // XVMUH_B
|
|
25102U, // XVMUH_BU
|
|
18816U, // XVMUH_D
|
|
25498U, // XVMUH_DU
|
|
21853U, // XVMUH_H
|
|
25938U, // XVMUH_HU
|
|
28051U, // XVMUH_W
|
|
26607U, // XVMUH_WU
|
|
27470U, // XVMULWEV_D_W
|
|
26502U, // XVMULWEV_D_WU
|
|
29268U, // XVMULWEV_D_WU_W
|
|
16897U, // XVMULWEV_H_B
|
|
25087U, // XVMULWEV_H_BU
|
|
17790U, // XVMULWEV_H_BU_B
|
|
19702U, // XVMULWEV_Q_D
|
|
25712U, // XVMULWEV_Q_DU
|
|
20385U, // XVMULWEV_Q_DU_D
|
|
22997U, // XVMULWEV_W_H
|
|
26288U, // XVMULWEV_W_HU
|
|
22787U, // XVMULWEV_W_HU_H
|
|
27348U, // XVMULWOD_D_W
|
|
26441U, // XVMULWOD_D_WU
|
|
29216U, // XVMULWOD_D_WU_W
|
|
16814U, // XVMULWOD_H_B
|
|
25026U, // XVMULWOD_H_BU
|
|
17738U, // XVMULWOD_H_BU_B
|
|
19621U, // XVMULWOD_Q_D
|
|
25651U, // XVMULWOD_Q_DU
|
|
20333U, // XVMULWOD_Q_DU_D
|
|
22905U, // XVMULWOD_W_H
|
|
26227U, // XVMULWOD_W_HU
|
|
22735U, // XVMULWOD_W_HU_H
|
|
17396U, // XVMUL_B
|
|
19415U, // XVMUL_D
|
|
22247U, // XVMUL_H
|
|
28603U, // XVMUL_W
|
|
16753U, // XVNEG_B
|
|
18790U, // XVNEG_D
|
|
21835U, // XVNEG_H
|
|
27762U, // XVNEG_W
|
|
17217U, // XVNORI_B
|
|
26957U, // XVNOR_V
|
|
17227U, // XVORI_B
|
|
26948U, // XVORN_V
|
|
26966U, // XVOR_V
|
|
17807U, // XVPACKEV_B
|
|
20552U, // XVPACKEV_D
|
|
22804U, // XVPACKEV_H
|
|
29285U, // XVPACKEV_W
|
|
16652U, // XVPACKOD_B
|
|
18452U, // XVPACKOD_D
|
|
21734U, // XVPACKOD_H
|
|
27649U, // XVPACKOD_W
|
|
17687U, // XVPCNT_B
|
|
20247U, // XVPCNT_D
|
|
22564U, // XVPCNT_H
|
|
29035U, // XVPCNT_W
|
|
19049U, // XVPERMI_D
|
|
39961U, // XVPERMI_Q
|
|
44662U, // XVPERMI_W
|
|
28633U, // XVPERM_W
|
|
17819U, // XVPICKEV_B
|
|
20564U, // XVPICKEV_D
|
|
22816U, // XVPICKEV_H
|
|
29297U, // XVPICKEV_W
|
|
16664U, // XVPICKOD_B
|
|
18464U, // XVPICKOD_D
|
|
21746U, // XVPICKOD_H
|
|
27661U, // XVPICKOD_W
|
|
19857U, // XVPICKVE2GR_D
|
|
25727U, // XVPICKVE2GR_DU
|
|
28744U, // XVPICKVE2GR_W
|
|
26723U, // XVPICKVE2GR_WU
|
|
18720U, // XVPICKVE_D
|
|
27728U, // XVPICKVE_W
|
|
17022U, // XVREPL128VEI_B
|
|
18934U, // XVREPL128VEI_D
|
|
21915U, // XVREPL128VEI_H
|
|
28152U, // XVREPL128VEI_W
|
|
17580U, // XVREPLGR2VR_B
|
|
20026U, // XVREPLGR2VR_D
|
|
22431U, // XVREPLGR2VR_H
|
|
28903U, // XVREPLGR2VR_W
|
|
16417U, // XVREPLVE0_B
|
|
18014U, // XVREPLVE0_D
|
|
21283U, // XVREPLVE0_H
|
|
23428U, // XVREPLVE0_Q
|
|
27007U, // XVREPLVE0_W
|
|
16731U, // XVREPLVE_B
|
|
18732U, // XVREPLVE_D
|
|
21813U, // XVREPLVE_H
|
|
27740U, // XVREPLVE_W
|
|
17258U, // XVROTRI_B
|
|
19138U, // XVROTRI_D
|
|
22109U, // XVROTRI_H
|
|
28379U, // XVROTRI_W
|
|
17570U, // XVROTR_B
|
|
19991U, // XVROTR_D
|
|
22421U, // XVROTR_H
|
|
28868U, // XVROTR_W
|
|
16617U, // XVSADD_B
|
|
24921U, // XVSADD_BU
|
|
18396U, // XVSADD_D
|
|
25437U, // XVSADD_DU
|
|
21699U, // XVSADD_H
|
|
25879U, // XVSADD_HU
|
|
27595U, // XVSADD_W
|
|
26539U, // XVSADD_WU
|
|
17641U, // XVSAT_B
|
|
25225U, // XVSAT_BU
|
|
20131U, // XVSAT_D
|
|
25754U, // XVSAT_DU
|
|
22518U, // XVSAT_H
|
|
26061U, // XVSAT_HU
|
|
28989U, // XVSAT_W
|
|
26764U, // XVSAT_WU
|
|
17161U, // XVSEQI_B
|
|
19070U, // XVSEQI_D
|
|
22041U, // XVSEQI_H
|
|
28299U, // XVSEQI_W
|
|
17465U, // XVSEQ_B
|
|
19779U, // XVSEQ_D
|
|
22316U, // XVSEQ_H
|
|
28696U, // XVSEQ_W
|
|
17922U, // XVSETALLNEZ_B
|
|
20972U, // XVSETALLNEZ_D
|
|
23073U, // XVSETALLNEZ_H
|
|
29418U, // XVSETALLNEZ_W
|
|
17957U, // XVSETANYEQZ_B
|
|
20996U, // XVSETANYEQZ_D
|
|
23097U, // XVSETANYEQZ_H
|
|
29442U, // XVSETANYEQZ_W
|
|
26995U, // XVSETEQZ_V
|
|
26983U, // XVSETNEZ_V
|
|
16969U, // XVSHUF4I_B
|
|
35256U, // XVSHUF4I_D
|
|
21872U, // XVSHUF4I_H
|
|
28090U, // XVSHUF4I_W
|
|
16743U, // XVSHUF_B
|
|
35156U, // XVSHUF_D
|
|
38209U, // XVSHUF_H
|
|
44136U, // XVSHUF_W
|
|
17852U, // XVSIGNCOV_B
|
|
20607U, // XVSIGNCOV_D
|
|
22849U, // XVSIGNCOV_H
|
|
29330U, // XVSIGNCOV_W
|
|
17012U, // XVSLEI_B
|
|
25134U, // XVSLEI_BU
|
|
18924U, // XVSLEI_D
|
|
25530U, // XVSLEI_DU
|
|
21905U, // XVSLEI_H
|
|
25970U, // XVSLEI_HU
|
|
28142U, // XVSLEI_W
|
|
26639U, // XVSLEI_WU
|
|
16714U, // XVSLE_B
|
|
24960U, // XVSLE_BU
|
|
18554U, // XVSLE_D
|
|
25469U, // XVSLE_DU
|
|
21796U, // XVSLE_H
|
|
25918U, // XVSLE_HU
|
|
27711U, // XVSLE_W
|
|
26578U, // XVSLE_WU
|
|
17085U, // XVSLLI_B
|
|
18995U, // XVSLLI_D
|
|
21965U, // XVSLLI_H
|
|
28213U, // XVSLLI_W
|
|
26798U, // XVSLLWIL_DU_WU
|
|
27388U, // XVSLLWIL_D_W
|
|
25274U, // XVSLLWIL_HU_BU
|
|
16840U, // XVSLLWIL_H_B
|
|
26110U, // XVSLLWIL_WU_HU
|
|
22931U, // XVSLLWIL_W_H
|
|
17335U, // XVSLL_B
|
|
19329U, // XVSLL_D
|
|
22186U, // XVSLL_H
|
|
28517U, // XVSLL_W
|
|
17282U, // XVSLTI_B
|
|
25156U, // XVSLTI_BU
|
|
19162U, // XVSLTI_D
|
|
25552U, // XVSLTI_DU
|
|
22133U, // XVSLTI_H
|
|
25992U, // XVSLTI_HU
|
|
28403U, // XVSLTI_W
|
|
26661U, // XVSLTI_WU
|
|
17678U, // XVSLT_B
|
|
25235U, // XVSLT_BU
|
|
20208U, // XVSLT_D
|
|
25764U, // XVSLT_DU
|
|
22555U, // XVSLT_H
|
|
26071U, // XVSLT_HU
|
|
29026U, // XVSLT_W
|
|
26774U, // XVSLT_WU
|
|
16992U, // XVSRAI_B
|
|
18906U, // XVSRAI_D
|
|
21895U, // XVSRAI_H
|
|
28124U, // XVSRAI_W
|
|
37723U, // XVSRANI_B_H
|
|
39854U, // XVSRANI_D_Q
|
|
44178U, // XVSRANI_H_W
|
|
37052U, // XVSRANI_W_D
|
|
21450U, // XVSRAN_B_H
|
|
27905U, // XVSRAN_H_W
|
|
20794U, // XVSRAN_W_D
|
|
17171U, // XVSRARI_B
|
|
19080U, // XVSRARI_D
|
|
22051U, // XVSRARI_H
|
|
28309U, // XVSRARI_W
|
|
37778U, // XVSRARNI_B_H
|
|
39909U, // XVSRARNI_D_Q
|
|
44233U, // XVSRARNI_H_W
|
|
37107U, // XVSRARNI_W_D
|
|
21501U, // XVSRARN_B_H
|
|
27956U, // XVSRARN_H_W
|
|
20845U, // XVSRARN_W_D
|
|
17474U, // XVSRAR_B
|
|
19818U, // XVSRAR_D
|
|
22325U, // XVSRAR_H
|
|
28705U, // XVSRAR_W
|
|
16450U, // XVSRA_B
|
|
18070U, // XVSRA_D
|
|
21316U, // XVSRA_H
|
|
27062U, // XVSRA_W
|
|
17117U, // XVSRLI_B
|
|
19027U, // XVSRLI_D
|
|
21997U, // XVSRLI_H
|
|
28256U, // XVSRLI_W
|
|
37750U, // XVSRLNI_B_H
|
|
39881U, // XVSRLNI_D_Q
|
|
44205U, // XVSRLNI_H_W
|
|
37079U, // XVSRLNI_W_D
|
|
21475U, // XVSRLN_B_H
|
|
27930U, // XVSRLN_H_W
|
|
20819U, // XVSRLN_W_D
|
|
17206U, // XVSRLRI_B
|
|
19115U, // XVSRLRI_D
|
|
22086U, // XVSRLRI_H
|
|
28344U, // XVSRLRI_W
|
|
37807U, // XVSRLRNI_B_H
|
|
39938U, // XVSRLRNI_D_Q
|
|
44262U, // XVSRLRNI_H_W
|
|
37136U, // XVSRLRNI_W_D
|
|
21528U, // XVSRLRN_B_H
|
|
27983U, // XVSRLRN_H_W
|
|
20872U, // XVSRLRN_W_D
|
|
17530U, // XVSRLR_B
|
|
19906U, // XVSRLR_D
|
|
22381U, // XVSRLR_H
|
|
28781U, // XVSRLR_W
|
|
17366U, // XVSRL_B
|
|
19360U, // XVSRL_D
|
|
22217U, // XVSRL_H
|
|
28558U, // XVSRL_W
|
|
38964U, // XVSSRANI_BU_H
|
|
37709U, // XVSSRANI_B_H
|
|
39972U, // XVSSRANI_DU_Q
|
|
39840U, // XVSSRANI_D_Q
|
|
45445U, // XVSSRANI_HU_W
|
|
44164U, // XVSSRANI_H_W
|
|
36816U, // XVSSRANI_WU_D
|
|
37038U, // XVSSRANI_W_D
|
|
22642U, // XVSSRAN_BU_H
|
|
21437U, // XVSSRAN_B_H
|
|
29123U, // XVSSRAN_HU_W
|
|
27892U, // XVSSRAN_H_W
|
|
20494U, // XVSSRAN_WU_D
|
|
20781U, // XVSSRAN_W_D
|
|
38994U, // XVSSRARNI_BU_H
|
|
37763U, // XVSSRARNI_B_H
|
|
40002U, // XVSSRARNI_DU_Q
|
|
39894U, // XVSSRARNI_D_Q
|
|
45475U, // XVSSRARNI_HU_W
|
|
44218U, // XVSSRARNI_H_W
|
|
36846U, // XVSSRARNI_WU_D
|
|
37092U, // XVSSRARNI_W_D
|
|
22670U, // XVSSRARN_BU_H
|
|
21487U, // XVSSRARN_B_H
|
|
29151U, // XVSSRARN_HU_W
|
|
27942U, // XVSSRARN_H_W
|
|
20522U, // XVSSRARN_WU_D
|
|
20831U, // XVSSRARN_W_D
|
|
38979U, // XVSSRLNI_BU_H
|
|
37736U, // XVSSRLNI_B_H
|
|
39987U, // XVSSRLNI_DU_Q
|
|
39867U, // XVSSRLNI_D_Q
|
|
45460U, // XVSSRLNI_HU_W
|
|
44191U, // XVSSRLNI_H_W
|
|
36831U, // XVSSRLNI_WU_D
|
|
37065U, // XVSSRLNI_W_D
|
|
22656U, // XVSSRLN_BU_H
|
|
21462U, // XVSSRLN_B_H
|
|
29137U, // XVSSRLN_HU_W
|
|
27917U, // XVSSRLN_H_W
|
|
20508U, // XVSSRLN_WU_D
|
|
20806U, // XVSSRLN_W_D
|
|
39010U, // XVSSRLRNI_BU_H
|
|
37792U, // XVSSRLRNI_B_H
|
|
40018U, // XVSSRLRNI_DU_Q
|
|
39923U, // XVSSRLRNI_D_Q
|
|
45491U, // XVSSRLRNI_HU_W
|
|
44247U, // XVSSRLRNI_H_W
|
|
36862U, // XVSSRLRNI_WU_D
|
|
37121U, // XVSSRLRNI_W_D
|
|
22685U, // XVSSRLRN_BU_H
|
|
21514U, // XVSSRLRN_B_H
|
|
29166U, // XVSSRLRN_HU_W
|
|
27969U, // XVSSRLRN_H_W
|
|
20537U, // XVSSRLRN_WU_D
|
|
20858U, // XVSSRLRN_W_D
|
|
16516U, // XVSSUB_B
|
|
24910U, // XVSSUB_BU
|
|
18261U, // XVSSUB_D
|
|
25415U, // XVSSUB_DU
|
|
21598U, // XVSSUB_H
|
|
25868U, // XVSSUB_HU
|
|
27220U, // XVSSUB_W
|
|
26384U, // XVSSUB_WU
|
|
24904U, // XVST
|
|
17415U, // XVSTELM_B
|
|
19434U, // XVSTELM_D
|
|
22266U, // XVSTELM_H
|
|
28622U, // XVSTELM_W
|
|
29509U, // XVSTX
|
|
25112U, // XVSUBI_BU
|
|
25508U, // XVSUBI_DU
|
|
25948U, // XVSUBI_HU
|
|
26617U, // XVSUBI_WU
|
|
27427U, // XVSUBWEV_D_W
|
|
26456U, // XVSUBWEV_D_WU
|
|
16854U, // XVSUBWEV_H_B
|
|
25041U, // XVSUBWEV_H_BU
|
|
19659U, // XVSUBWEV_Q_D
|
|
25666U, // XVSUBWEV_Q_DU
|
|
22954U, // XVSUBWEV_W_H
|
|
26242U, // XVSUBWEV_W_HU
|
|
27305U, // XVSUBWOD_D_W
|
|
26395U, // XVSUBWOD_D_WU
|
|
16771U, // XVSUBWOD_H_B
|
|
24980U, // XVSUBWOD_H_BU
|
|
19578U, // XVSUBWOD_Q_D
|
|
25605U, // XVSUBWOD_Q_DU
|
|
22862U, // XVSUBWOD_W_H
|
|
26181U, // XVSUBWOD_W_HU
|
|
16526U, // XVSUB_B
|
|
18271U, // XVSUB_D
|
|
21608U, // XVSUB_H
|
|
23441U, // XVSUB_Q
|
|
27230U, // XVSUB_W
|
|
17236U, // XVXORI_B
|
|
26974U, // XVXOR_V
|
|
};
|
|
|
|
static const uint8_t OpInfo1[] = {
|
|
0U, // PHI
|
|
0U, // INLINEASM
|
|
0U, // INLINEASM_BR
|
|
0U, // CFI_INSTRUCTION
|
|
0U, // EH_LABEL
|
|
0U, // GC_LABEL
|
|
0U, // ANNOTATION_LABEL
|
|
0U, // KILL
|
|
0U, // EXTRACT_SUBREG
|
|
0U, // INSERT_SUBREG
|
|
0U, // IMPLICIT_DEF
|
|
0U, // SUBREG_TO_REG
|
|
0U, // COPY_TO_REGCLASS
|
|
0U, // DBG_VALUE
|
|
0U, // DBG_VALUE_LIST
|
|
0U, // DBG_INSTR_REF
|
|
0U, // DBG_PHI
|
|
0U, // DBG_LABEL
|
|
0U, // REG_SEQUENCE
|
|
0U, // COPY
|
|
0U, // BUNDLE
|
|
0U, // LIFETIME_START
|
|
0U, // LIFETIME_END
|
|
0U, // PSEUDO_PROBE
|
|
0U, // ARITH_FENCE
|
|
0U, // STACKMAP
|
|
0U, // FENTRY_CALL
|
|
0U, // PATCHPOINT
|
|
0U, // LOAD_STACK_GUARD
|
|
0U, // PREALLOCATED_SETUP
|
|
0U, // PREALLOCATED_ARG
|
|
0U, // STATEPOINT
|
|
0U, // LOCAL_ESCAPE
|
|
0U, // FAULTING_OP
|
|
0U, // PATCHABLE_OP
|
|
0U, // PATCHABLE_FUNCTION_ENTER
|
|
0U, // PATCHABLE_RET
|
|
0U, // PATCHABLE_FUNCTION_EXIT
|
|
0U, // PATCHABLE_TAIL_CALL
|
|
0U, // PATCHABLE_EVENT_CALL
|
|
0U, // PATCHABLE_TYPED_EVENT_CALL
|
|
0U, // ICALL_BRANCH_FUNNEL
|
|
0U, // MEMBARRIER
|
|
0U, // JUMP_TABLE_DEBUG_INFO
|
|
0U, // G_ASSERT_SEXT
|
|
0U, // G_ASSERT_ZEXT
|
|
0U, // G_ASSERT_ALIGN
|
|
0U, // G_ADD
|
|
0U, // G_SUB
|
|
0U, // G_MUL
|
|
0U, // G_SDIV
|
|
0U, // G_UDIV
|
|
0U, // G_SREM
|
|
0U, // G_UREM
|
|
0U, // G_SDIVREM
|
|
0U, // G_UDIVREM
|
|
0U, // G_AND
|
|
0U, // G_OR
|
|
0U, // G_XOR
|
|
0U, // G_IMPLICIT_DEF
|
|
0U, // G_PHI
|
|
0U, // G_FRAME_INDEX
|
|
0U, // G_GLOBAL_VALUE
|
|
0U, // G_CONSTANT_POOL
|
|
0U, // G_EXTRACT
|
|
0U, // G_UNMERGE_VALUES
|
|
0U, // G_INSERT
|
|
0U, // G_MERGE_VALUES
|
|
0U, // G_BUILD_VECTOR
|
|
0U, // G_BUILD_VECTOR_TRUNC
|
|
0U, // G_CONCAT_VECTORS
|
|
0U, // G_PTRTOINT
|
|
0U, // G_INTTOPTR
|
|
0U, // G_BITCAST
|
|
0U, // G_FREEZE
|
|
0U, // G_CONSTANT_FOLD_BARRIER
|
|
0U, // G_INTRINSIC_FPTRUNC_ROUND
|
|
0U, // G_INTRINSIC_TRUNC
|
|
0U, // G_INTRINSIC_ROUND
|
|
0U, // G_INTRINSIC_LRINT
|
|
0U, // G_INTRINSIC_ROUNDEVEN
|
|
0U, // G_READCYCLECOUNTER
|
|
0U, // G_LOAD
|
|
0U, // G_SEXTLOAD
|
|
0U, // G_ZEXTLOAD
|
|
0U, // G_INDEXED_LOAD
|
|
0U, // G_INDEXED_SEXTLOAD
|
|
0U, // G_INDEXED_ZEXTLOAD
|
|
0U, // G_STORE
|
|
0U, // G_INDEXED_STORE
|
|
0U, // G_ATOMIC_CMPXCHG_WITH_SUCCESS
|
|
0U, // G_ATOMIC_CMPXCHG
|
|
0U, // G_ATOMICRMW_XCHG
|
|
0U, // G_ATOMICRMW_ADD
|
|
0U, // G_ATOMICRMW_SUB
|
|
0U, // G_ATOMICRMW_AND
|
|
0U, // G_ATOMICRMW_NAND
|
|
0U, // G_ATOMICRMW_OR
|
|
0U, // G_ATOMICRMW_XOR
|
|
0U, // G_ATOMICRMW_MAX
|
|
0U, // G_ATOMICRMW_MIN
|
|
0U, // G_ATOMICRMW_UMAX
|
|
0U, // G_ATOMICRMW_UMIN
|
|
0U, // G_ATOMICRMW_FADD
|
|
0U, // G_ATOMICRMW_FSUB
|
|
0U, // G_ATOMICRMW_FMAX
|
|
0U, // G_ATOMICRMW_FMIN
|
|
0U, // G_ATOMICRMW_UINC_WRAP
|
|
0U, // G_ATOMICRMW_UDEC_WRAP
|
|
0U, // G_FENCE
|
|
0U, // G_PREFETCH
|
|
0U, // G_BRCOND
|
|
0U, // G_BRINDIRECT
|
|
0U, // G_INVOKE_REGION_START
|
|
0U, // G_INTRINSIC
|
|
0U, // G_INTRINSIC_W_SIDE_EFFECTS
|
|
0U, // G_INTRINSIC_CONVERGENT
|
|
0U, // G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS
|
|
0U, // G_ANYEXT
|
|
0U, // G_TRUNC
|
|
0U, // G_CONSTANT
|
|
0U, // G_FCONSTANT
|
|
0U, // G_VASTART
|
|
0U, // G_VAARG
|
|
0U, // G_SEXT
|
|
0U, // G_SEXT_INREG
|
|
0U, // G_ZEXT
|
|
0U, // G_SHL
|
|
0U, // G_LSHR
|
|
0U, // G_ASHR
|
|
0U, // G_FSHL
|
|
0U, // G_FSHR
|
|
0U, // G_ROTR
|
|
0U, // G_ROTL
|
|
0U, // G_ICMP
|
|
0U, // G_FCMP
|
|
0U, // G_SELECT
|
|
0U, // G_UADDO
|
|
0U, // G_UADDE
|
|
0U, // G_USUBO
|
|
0U, // G_USUBE
|
|
0U, // G_SADDO
|
|
0U, // G_SADDE
|
|
0U, // G_SSUBO
|
|
0U, // G_SSUBE
|
|
0U, // G_UMULO
|
|
0U, // G_SMULO
|
|
0U, // G_UMULH
|
|
0U, // G_SMULH
|
|
0U, // G_UADDSAT
|
|
0U, // G_SADDSAT
|
|
0U, // G_USUBSAT
|
|
0U, // G_SSUBSAT
|
|
0U, // G_USHLSAT
|
|
0U, // G_SSHLSAT
|
|
0U, // G_SMULFIX
|
|
0U, // G_UMULFIX
|
|
0U, // G_SMULFIXSAT
|
|
0U, // G_UMULFIXSAT
|
|
0U, // G_SDIVFIX
|
|
0U, // G_UDIVFIX
|
|
0U, // G_SDIVFIXSAT
|
|
0U, // G_UDIVFIXSAT
|
|
0U, // G_FADD
|
|
0U, // G_FSUB
|
|
0U, // G_FMUL
|
|
0U, // G_FMA
|
|
0U, // G_FMAD
|
|
0U, // G_FDIV
|
|
0U, // G_FREM
|
|
0U, // G_FPOW
|
|
0U, // G_FPOWI
|
|
0U, // G_FEXP
|
|
0U, // G_FEXP2
|
|
0U, // G_FEXP10
|
|
0U, // G_FLOG
|
|
0U, // G_FLOG2
|
|
0U, // G_FLOG10
|
|
0U, // G_FLDEXP
|
|
0U, // G_FFREXP
|
|
0U, // G_FNEG
|
|
0U, // G_FPEXT
|
|
0U, // G_FPTRUNC
|
|
0U, // G_FPTOSI
|
|
0U, // G_FPTOUI
|
|
0U, // G_SITOFP
|
|
0U, // G_UITOFP
|
|
0U, // G_FABS
|
|
0U, // G_FCOPYSIGN
|
|
0U, // G_IS_FPCLASS
|
|
0U, // G_FCANONICALIZE
|
|
0U, // G_FMINNUM
|
|
0U, // G_FMAXNUM
|
|
0U, // G_FMINNUM_IEEE
|
|
0U, // G_FMAXNUM_IEEE
|
|
0U, // G_FMINIMUM
|
|
0U, // G_FMAXIMUM
|
|
0U, // G_GET_FPENV
|
|
0U, // G_SET_FPENV
|
|
0U, // G_RESET_FPENV
|
|
0U, // G_GET_FPMODE
|
|
0U, // G_SET_FPMODE
|
|
0U, // G_RESET_FPMODE
|
|
0U, // G_PTR_ADD
|
|
0U, // G_PTRMASK
|
|
0U, // G_SMIN
|
|
0U, // G_SMAX
|
|
0U, // G_UMIN
|
|
0U, // G_UMAX
|
|
0U, // G_ABS
|
|
0U, // G_LROUND
|
|
0U, // G_LLROUND
|
|
0U, // G_BR
|
|
0U, // G_BRJT
|
|
0U, // G_INSERT_VECTOR_ELT
|
|
0U, // G_EXTRACT_VECTOR_ELT
|
|
0U, // G_SHUFFLE_VECTOR
|
|
0U, // G_CTTZ
|
|
0U, // G_CTTZ_ZERO_UNDEF
|
|
0U, // G_CTLZ
|
|
0U, // G_CTLZ_ZERO_UNDEF
|
|
0U, // G_CTPOP
|
|
0U, // G_BSWAP
|
|
0U, // G_BITREVERSE
|
|
0U, // G_FCEIL
|
|
0U, // G_FCOS
|
|
0U, // G_FSIN
|
|
0U, // G_FSQRT
|
|
0U, // G_FFLOOR
|
|
0U, // G_FRINT
|
|
0U, // G_FNEARBYINT
|
|
0U, // G_ADDRSPACE_CAST
|
|
0U, // G_BLOCK_ADDR
|
|
0U, // G_JUMP_TABLE
|
|
0U, // G_DYN_STACKALLOC
|
|
0U, // G_STACKSAVE
|
|
0U, // G_STACKRESTORE
|
|
0U, // G_STRICT_FADD
|
|
0U, // G_STRICT_FSUB
|
|
0U, // G_STRICT_FMUL
|
|
0U, // G_STRICT_FDIV
|
|
0U, // G_STRICT_FREM
|
|
0U, // G_STRICT_FMA
|
|
0U, // G_STRICT_FSQRT
|
|
0U, // G_STRICT_FLDEXP
|
|
0U, // G_READ_REGISTER
|
|
0U, // G_WRITE_REGISTER
|
|
0U, // G_MEMCPY
|
|
0U, // G_MEMCPY_INLINE
|
|
0U, // G_MEMMOVE
|
|
0U, // G_MEMSET
|
|
0U, // G_BZERO
|
|
0U, // G_VECREDUCE_SEQ_FADD
|
|
0U, // G_VECREDUCE_SEQ_FMUL
|
|
0U, // G_VECREDUCE_FADD
|
|
0U, // G_VECREDUCE_FMUL
|
|
0U, // G_VECREDUCE_FMAX
|
|
0U, // G_VECREDUCE_FMIN
|
|
0U, // G_VECREDUCE_FMAXIMUM
|
|
0U, // G_VECREDUCE_FMINIMUM
|
|
0U, // G_VECREDUCE_ADD
|
|
0U, // G_VECREDUCE_MUL
|
|
0U, // G_VECREDUCE_AND
|
|
0U, // G_VECREDUCE_OR
|
|
0U, // G_VECREDUCE_XOR
|
|
0U, // G_VECREDUCE_SMAX
|
|
0U, // G_VECREDUCE_SMIN
|
|
0U, // G_VECREDUCE_UMAX
|
|
0U, // G_VECREDUCE_UMIN
|
|
0U, // G_SBFX
|
|
0U, // G_UBFX
|
|
0U, // ADJCALLSTACKDOWN
|
|
0U, // ADJCALLSTACKUP
|
|
0U, // PseudoAtomicLoadAdd32
|
|
0U, // PseudoAtomicLoadAnd32
|
|
0U, // PseudoAtomicLoadNand32
|
|
0U, // PseudoAtomicLoadNand64
|
|
0U, // PseudoAtomicLoadOr32
|
|
0U, // PseudoAtomicLoadSub32
|
|
0U, // PseudoAtomicLoadXor32
|
|
0U, // PseudoAtomicStoreD
|
|
0U, // PseudoAtomicStoreW
|
|
0U, // PseudoAtomicSwap32
|
|
0U, // PseudoBR
|
|
0U, // PseudoBRIND
|
|
0U, // PseudoB_TAIL
|
|
0U, // PseudoCALL
|
|
0U, // PseudoCALL36
|
|
0U, // PseudoCALLIndirect
|
|
0U, // PseudoCALL_LARGE
|
|
0U, // PseudoCALL_MEDIUM
|
|
0U, // PseudoCmpXchg32
|
|
0U, // PseudoCmpXchg64
|
|
0U, // PseudoCopyCFR
|
|
0U, // PseudoJIRL_CALL
|
|
0U, // PseudoJIRL_TAIL
|
|
1U, // PseudoLA_ABS
|
|
5U, // PseudoLA_ABS_LARGE
|
|
1U, // PseudoLA_GOT
|
|
17U, // PseudoLA_GOT_LARGE
|
|
1U, // PseudoLA_PCREL
|
|
17U, // PseudoLA_PCREL_LARGE
|
|
1U, // PseudoLA_TLS_GD
|
|
17U, // PseudoLA_TLS_GD_LARGE
|
|
1U, // PseudoLA_TLS_IE
|
|
17U, // PseudoLA_TLS_IE_LARGE
|
|
1U, // PseudoLA_TLS_LD
|
|
17U, // PseudoLA_TLS_LD_LARGE
|
|
1U, // PseudoLA_TLS_LE
|
|
0U, // PseudoLD_CFR
|
|
1U, // PseudoLI_D
|
|
1U, // PseudoLI_W
|
|
0U, // PseudoMaskedAtomicLoadAdd32
|
|
0U, // PseudoMaskedAtomicLoadMax32
|
|
0U, // PseudoMaskedAtomicLoadMin32
|
|
0U, // PseudoMaskedAtomicLoadNand32
|
|
0U, // PseudoMaskedAtomicLoadSub32
|
|
0U, // PseudoMaskedAtomicLoadUMax32
|
|
0U, // PseudoMaskedAtomicLoadUMin32
|
|
0U, // PseudoMaskedAtomicSwap32
|
|
0U, // PseudoMaskedCmpXchg32
|
|
0U, // PseudoRET
|
|
0U, // PseudoST_CFR
|
|
0U, // PseudoTAIL
|
|
1U, // PseudoTAIL36
|
|
0U, // PseudoTAILIndirect
|
|
0U, // PseudoTAIL_LARGE
|
|
0U, // PseudoTAIL_MEDIUM
|
|
0U, // PseudoUNIMP
|
|
0U, // PseudoVBNZ
|
|
0U, // PseudoVBNZ_B
|
|
0U, // PseudoVBNZ_D
|
|
0U, // PseudoVBNZ_H
|
|
0U, // PseudoVBNZ_W
|
|
0U, // PseudoVBZ
|
|
0U, // PseudoVBZ_B
|
|
0U, // PseudoVBZ_D
|
|
0U, // PseudoVBZ_H
|
|
0U, // PseudoVBZ_W
|
|
1U, // PseudoVREPLI_B
|
|
1U, // PseudoVREPLI_D
|
|
1U, // PseudoVREPLI_H
|
|
1U, // PseudoVREPLI_W
|
|
0U, // PseudoXVBNZ
|
|
0U, // PseudoXVBNZ_B
|
|
0U, // PseudoXVBNZ_D
|
|
0U, // PseudoXVBNZ_H
|
|
0U, // PseudoXVBNZ_W
|
|
0U, // PseudoXVBZ
|
|
0U, // PseudoXVBZ_B
|
|
0U, // PseudoXVBZ_D
|
|
0U, // PseudoXVBZ_H
|
|
0U, // PseudoXVBZ_W
|
|
0U, // PseudoXVINSGR2VR_B
|
|
0U, // PseudoXVINSGR2VR_H
|
|
1U, // PseudoXVREPLI_B
|
|
1U, // PseudoXVREPLI_D
|
|
1U, // PseudoXVREPLI_H
|
|
1U, // PseudoXVREPLI_W
|
|
0U, // RDFCSR
|
|
0U, // WRFCSR
|
|
17U, // ADC_B
|
|
17U, // ADC_D
|
|
17U, // ADC_H
|
|
17U, // ADC_W
|
|
17U, // ADDI_D
|
|
17U, // ADDI_W
|
|
17U, // ADDU12I_D
|
|
17U, // ADDU12I_W
|
|
17U, // ADDU16I_D
|
|
17U, // ADD_D
|
|
17U, // ADD_W
|
|
145U, // ALSL_D
|
|
145U, // ALSL_W
|
|
145U, // ALSL_WU
|
|
49U, // AMADD_B
|
|
49U, // AMADD_D
|
|
49U, // AMADD_H
|
|
49U, // AMADD_W
|
|
49U, // AMADD__DB_B
|
|
49U, // AMADD__DB_D
|
|
49U, // AMADD__DB_H
|
|
49U, // AMADD__DB_W
|
|
49U, // AMAND_D
|
|
49U, // AMAND_W
|
|
49U, // AMAND__DB_D
|
|
49U, // AMAND__DB_W
|
|
49U, // AMCAS_B
|
|
49U, // AMCAS_D
|
|
49U, // AMCAS_H
|
|
49U, // AMCAS_W
|
|
49U, // AMCAS__DB_B
|
|
49U, // AMCAS__DB_D
|
|
49U, // AMCAS__DB_H
|
|
49U, // AMCAS__DB_W
|
|
49U, // AMMAX_D
|
|
49U, // AMMAX_DU
|
|
49U, // AMMAX_W
|
|
49U, // AMMAX_WU
|
|
49U, // AMMAX__DB_D
|
|
49U, // AMMAX__DB_DU
|
|
49U, // AMMAX__DB_W
|
|
49U, // AMMAX__DB_WU
|
|
49U, // AMMIN_D
|
|
49U, // AMMIN_DU
|
|
49U, // AMMIN_W
|
|
49U, // AMMIN_WU
|
|
49U, // AMMIN__DB_D
|
|
49U, // AMMIN__DB_DU
|
|
49U, // AMMIN__DB_W
|
|
49U, // AMMIN__DB_WU
|
|
49U, // AMOR_D
|
|
49U, // AMOR_W
|
|
49U, // AMOR__DB_D
|
|
49U, // AMOR__DB_W
|
|
49U, // AMSWAP_B
|
|
49U, // AMSWAP_D
|
|
49U, // AMSWAP_H
|
|
49U, // AMSWAP_W
|
|
49U, // AMSWAP__DB_B
|
|
49U, // AMSWAP__DB_D
|
|
49U, // AMSWAP__DB_H
|
|
49U, // AMSWAP__DB_W
|
|
49U, // AMXOR_D
|
|
49U, // AMXOR_W
|
|
49U, // AMXOR__DB_D
|
|
49U, // AMXOR__DB_W
|
|
17U, // AND
|
|
17U, // ANDI
|
|
17U, // ANDN
|
|
17U, // ARMADC_W
|
|
17U, // ARMADD_W
|
|
17U, // ARMAND_W
|
|
1U, // ARMMFFLAG
|
|
17U, // ARMMOVE
|
|
1U, // ARMMOV_D
|
|
1U, // ARMMOV_W
|
|
1U, // ARMMTFLAG
|
|
1U, // ARMNOT_W
|
|
17U, // ARMOR_W
|
|
17U, // ARMROTRI_W
|
|
17U, // ARMROTR_W
|
|
1U, // ARMRRX_W
|
|
17U, // ARMSBC_W
|
|
17U, // ARMSLLI_W
|
|
17U, // ARMSLL_W
|
|
17U, // ARMSRAI_W
|
|
17U, // ARMSRA_W
|
|
17U, // ARMSRLI_W
|
|
17U, // ARMSRL_W
|
|
17U, // ARMSUB_W
|
|
17U, // ARMXOR_W
|
|
1U, // ASRTGT_D
|
|
1U, // ASRTLE_D
|
|
0U, // B
|
|
1U, // BCEQZ
|
|
1U, // BCNEZ
|
|
17U, // BEQ
|
|
1U, // BEQZ
|
|
17U, // BGE
|
|
17U, // BGEU
|
|
1U, // BITREV_4B
|
|
1U, // BITREV_8B
|
|
1U, // BITREV_D
|
|
1U, // BITREV_W
|
|
0U, // BL
|
|
17U, // BLT
|
|
17U, // BLTU
|
|
17U, // BNE
|
|
1U, // BNEZ
|
|
0U, // BREAK
|
|
89U, // BSTRINS_D
|
|
89U, // BSTRINS_W
|
|
145U, // BSTRPICK_D
|
|
145U, // BSTRPICK_W
|
|
145U, // BYTEPICK_D
|
|
145U, // BYTEPICK_W
|
|
17U, // CACOP
|
|
1U, // CLO_D
|
|
1U, // CLO_W
|
|
1U, // CLZ_D
|
|
1U, // CLZ_W
|
|
1U, // CPUCFG
|
|
17U, // CRCC_W_B_W
|
|
17U, // CRCC_W_D_W
|
|
17U, // CRCC_W_H_W
|
|
17U, // CRCC_W_W_W
|
|
17U, // CRC_W_B_W
|
|
17U, // CRC_W_D_W
|
|
17U, // CRC_W_H_W
|
|
17U, // CRC_W_W_W
|
|
1U, // CSRRD
|
|
0U, // CSRWR
|
|
9U, // CSRXCHG
|
|
1U, // CTO_D
|
|
1U, // CTO_W
|
|
1U, // CTZ_D
|
|
1U, // CTZ_W
|
|
0U, // DBAR
|
|
0U, // DBCL
|
|
17U, // DIV_D
|
|
17U, // DIV_DU
|
|
17U, // DIV_W
|
|
17U, // DIV_WU
|
|
0U, // ERTN
|
|
1U, // EXT_W_B
|
|
1U, // EXT_W_H
|
|
1U, // FABS_D
|
|
1U, // FABS_S
|
|
17U, // FADD_D
|
|
17U, // FADD_S
|
|
1U, // FCLASS_D
|
|
1U, // FCLASS_S
|
|
17U, // FCMP_CAF_D
|
|
17U, // FCMP_CAF_S
|
|
17U, // FCMP_CEQ_D
|
|
17U, // FCMP_CEQ_S
|
|
17U, // FCMP_CLE_D
|
|
17U, // FCMP_CLE_S
|
|
17U, // FCMP_CLT_D
|
|
17U, // FCMP_CLT_S
|
|
17U, // FCMP_CNE_D
|
|
17U, // FCMP_CNE_S
|
|
17U, // FCMP_COR_D
|
|
17U, // FCMP_COR_S
|
|
17U, // FCMP_CUEQ_D
|
|
17U, // FCMP_CUEQ_S
|
|
17U, // FCMP_CULE_D
|
|
17U, // FCMP_CULE_S
|
|
17U, // FCMP_CULT_D
|
|
17U, // FCMP_CULT_S
|
|
17U, // FCMP_CUNE_D
|
|
17U, // FCMP_CUNE_S
|
|
17U, // FCMP_CUN_D
|
|
17U, // FCMP_CUN_S
|
|
17U, // FCMP_SAF_D
|
|
17U, // FCMP_SAF_S
|
|
17U, // FCMP_SEQ_D
|
|
17U, // FCMP_SEQ_S
|
|
17U, // FCMP_SLE_D
|
|
17U, // FCMP_SLE_S
|
|
17U, // FCMP_SLT_D
|
|
17U, // FCMP_SLT_S
|
|
17U, // FCMP_SNE_D
|
|
17U, // FCMP_SNE_S
|
|
17U, // FCMP_SOR_D
|
|
17U, // FCMP_SOR_S
|
|
17U, // FCMP_SUEQ_D
|
|
17U, // FCMP_SUEQ_S
|
|
17U, // FCMP_SULE_D
|
|
17U, // FCMP_SULE_S
|
|
17U, // FCMP_SULT_D
|
|
17U, // FCMP_SULT_S
|
|
17U, // FCMP_SUNE_D
|
|
17U, // FCMP_SUNE_S
|
|
17U, // FCMP_SUN_D
|
|
17U, // FCMP_SUN_S
|
|
17U, // FCOPYSIGN_D
|
|
17U, // FCOPYSIGN_S
|
|
17U, // FCVT_D_LD
|
|
1U, // FCVT_D_S
|
|
1U, // FCVT_LD_D
|
|
1U, // FCVT_S_D
|
|
1U, // FCVT_UD_D
|
|
17U, // FDIV_D
|
|
17U, // FDIV_S
|
|
1U, // FFINT_D_L
|
|
1U, // FFINT_D_W
|
|
1U, // FFINT_S_L
|
|
1U, // FFINT_S_W
|
|
17U, // FLDGT_D
|
|
17U, // FLDGT_S
|
|
17U, // FLDLE_D
|
|
17U, // FLDLE_S
|
|
17U, // FLDX_D
|
|
17U, // FLDX_S
|
|
17U, // FLD_D
|
|
17U, // FLD_S
|
|
1U, // FLOGB_D
|
|
1U, // FLOGB_S
|
|
145U, // FMADD_D
|
|
145U, // FMADD_S
|
|
17U, // FMAXA_D
|
|
17U, // FMAXA_S
|
|
17U, // FMAX_D
|
|
17U, // FMAX_S
|
|
17U, // FMINA_D
|
|
17U, // FMINA_S
|
|
17U, // FMIN_D
|
|
17U, // FMIN_S
|
|
1U, // FMOV_D
|
|
1U, // FMOV_S
|
|
145U, // FMSUB_D
|
|
145U, // FMSUB_S
|
|
17U, // FMUL_D
|
|
17U, // FMUL_S
|
|
1U, // FNEG_D
|
|
1U, // FNEG_S
|
|
145U, // FNMADD_D
|
|
145U, // FNMADD_S
|
|
145U, // FNMSUB_D
|
|
145U, // FNMSUB_S
|
|
1U, // FRECIPE_D
|
|
1U, // FRECIPE_S
|
|
1U, // FRECIP_D
|
|
1U, // FRECIP_S
|
|
1U, // FRINT_D
|
|
1U, // FRINT_S
|
|
1U, // FRSQRTE_D
|
|
1U, // FRSQRTE_S
|
|
1U, // FRSQRT_D
|
|
1U, // FRSQRT_S
|
|
17U, // FSCALEB_D
|
|
17U, // FSCALEB_S
|
|
145U, // FSEL_xD
|
|
145U, // FSEL_xS
|
|
1U, // FSQRT_D
|
|
1U, // FSQRT_S
|
|
17U, // FSTGT_D
|
|
17U, // FSTGT_S
|
|
17U, // FSTLE_D
|
|
17U, // FSTLE_S
|
|
17U, // FSTX_D
|
|
17U, // FSTX_S
|
|
17U, // FST_D
|
|
17U, // FST_S
|
|
17U, // FSUB_D
|
|
17U, // FSUB_S
|
|
1U, // FTINTRM_L_D
|
|
1U, // FTINTRM_L_S
|
|
1U, // FTINTRM_W_D
|
|
1U, // FTINTRM_W_S
|
|
1U, // FTINTRNE_L_D
|
|
1U, // FTINTRNE_L_S
|
|
1U, // FTINTRNE_W_D
|
|
1U, // FTINTRNE_W_S
|
|
1U, // FTINTRP_L_D
|
|
1U, // FTINTRP_L_S
|
|
1U, // FTINTRP_W_D
|
|
1U, // FTINTRP_W_S
|
|
1U, // FTINTRZ_L_D
|
|
1U, // FTINTRZ_L_S
|
|
1U, // FTINTRZ_W_D
|
|
1U, // FTINTRZ_W_S
|
|
1U, // FTINT_L_D
|
|
1U, // FTINT_L_S
|
|
1U, // FTINT_W_D
|
|
1U, // FTINT_W_S
|
|
1U, // GCSRRD
|
|
0U, // GCSRWR
|
|
9U, // GCSRXCHG
|
|
0U, // GTLBFLUSH
|
|
0U, // HVCL
|
|
0U, // IBAR
|
|
0U, // IDLE
|
|
0U, // INVTLB
|
|
1U, // IOCSRRD_B
|
|
1U, // IOCSRRD_D
|
|
1U, // IOCSRRD_H
|
|
1U, // IOCSRRD_W
|
|
1U, // IOCSRWR_B
|
|
1U, // IOCSRWR_D
|
|
1U, // IOCSRWR_H
|
|
1U, // IOCSRWR_W
|
|
17U, // JIRL
|
|
0U, // JISCR0
|
|
0U, // JISCR1
|
|
17U, // LDDIR
|
|
17U, // LDGT_B
|
|
17U, // LDGT_D
|
|
17U, // LDGT_H
|
|
17U, // LDGT_W
|
|
17U, // LDLE_B
|
|
17U, // LDLE_D
|
|
17U, // LDLE_H
|
|
17U, // LDLE_W
|
|
17U, // LDL_D
|
|
17U, // LDL_W
|
|
1U, // LDPTE
|
|
17U, // LDPTR_D
|
|
17U, // LDPTR_W
|
|
17U, // LDR_D
|
|
17U, // LDR_W
|
|
17U, // LDX_B
|
|
17U, // LDX_BU
|
|
17U, // LDX_D
|
|
17U, // LDX_H
|
|
17U, // LDX_HU
|
|
17U, // LDX_W
|
|
17U, // LDX_WU
|
|
17U, // LD_B
|
|
17U, // LD_BU
|
|
17U, // LD_D
|
|
17U, // LD_H
|
|
17U, // LD_HU
|
|
17U, // LD_W
|
|
17U, // LD_WU
|
|
1U, // LLACQ_D
|
|
1U, // LLACQ_W
|
|
17U, // LL_D
|
|
17U, // LL_W
|
|
1U, // LU12I_W
|
|
0U, // LU32I_D
|
|
17U, // LU52I_D
|
|
17U, // MASKEQZ
|
|
17U, // MASKNEZ
|
|
17U, // MOD_D
|
|
17U, // MOD_DU
|
|
17U, // MOD_W
|
|
17U, // MOD_WU
|
|
1U, // MOVCF2FR_xS
|
|
1U, // MOVCF2GR
|
|
1U, // MOVFCSR2GR
|
|
1U, // MOVFR2CF_xS
|
|
1U, // MOVFR2GR_D
|
|
1U, // MOVFR2GR_S
|
|
1U, // MOVFR2GR_S_64
|
|
1U, // MOVFRH2GR_S
|
|
1U, // MOVGR2CF
|
|
1U, // MOVGR2FCSR
|
|
0U, // MOVGR2FRH_W
|
|
1U, // MOVGR2FR_D
|
|
1U, // MOVGR2FR_W
|
|
1U, // MOVGR2FR_W_64
|
|
1U, // MOVGR2SCR
|
|
1U, // MOVSCR2GR
|
|
17U, // MULH_D
|
|
17U, // MULH_DU
|
|
17U, // MULH_W
|
|
17U, // MULH_WU
|
|
17U, // MULW_D_W
|
|
17U, // MULW_D_WU
|
|
17U, // MUL_D
|
|
17U, // MUL_W
|
|
17U, // NOR
|
|
17U, // OR
|
|
17U, // ORI
|
|
17U, // ORN
|
|
1U, // PCADDI
|
|
1U, // PCADDU12I
|
|
1U, // PCADDU18I
|
|
1U, // PCALAU12I
|
|
17U, // PRELD
|
|
17U, // PRELDX
|
|
17U, // RCRI_B
|
|
17U, // RCRI_D
|
|
17U, // RCRI_H
|
|
17U, // RCRI_W
|
|
17U, // RCR_B
|
|
17U, // RCR_D
|
|
17U, // RCR_H
|
|
17U, // RCR_W
|
|
1U, // RDTIMEH_W
|
|
1U, // RDTIMEL_W
|
|
1U, // RDTIME_D
|
|
1U, // REVB_2H
|
|
1U, // REVB_2W
|
|
1U, // REVB_4H
|
|
1U, // REVB_D
|
|
1U, // REVH_2W
|
|
1U, // REVH_D
|
|
17U, // ROTRI_B
|
|
17U, // ROTRI_D
|
|
17U, // ROTRI_H
|
|
17U, // ROTRI_W
|
|
17U, // ROTR_B
|
|
17U, // ROTR_D
|
|
17U, // ROTR_H
|
|
17U, // ROTR_W
|
|
17U, // SBC_B
|
|
17U, // SBC_D
|
|
17U, // SBC_H
|
|
17U, // SBC_W
|
|
0U, // SCREL_D
|
|
0U, // SCREL_W
|
|
9U, // SC_D
|
|
9U, // SC_Q
|
|
9U, // SC_W
|
|
1U, // SETARMJ
|
|
1U, // SETX86J
|
|
1U, // SETX86LOOPE
|
|
1U, // SETX86LOOPNE
|
|
2U, // SET_CFR_FALSE
|
|
2U, // SET_CFR_TRUE
|
|
17U, // SLLI_D
|
|
17U, // SLLI_W
|
|
17U, // SLL_D
|
|
17U, // SLL_W
|
|
17U, // SLT
|
|
17U, // SLTI
|
|
17U, // SLTU
|
|
17U, // SLTUI
|
|
17U, // SRAI_D
|
|
17U, // SRAI_W
|
|
17U, // SRA_D
|
|
17U, // SRA_W
|
|
17U, // SRLI_D
|
|
17U, // SRLI_W
|
|
17U, // SRL_D
|
|
17U, // SRL_W
|
|
17U, // STGT_B
|
|
17U, // STGT_D
|
|
17U, // STGT_H
|
|
17U, // STGT_W
|
|
17U, // STLE_B
|
|
17U, // STLE_D
|
|
17U, // STLE_H
|
|
17U, // STLE_W
|
|
17U, // STL_D
|
|
17U, // STL_W
|
|
17U, // STPTR_D
|
|
17U, // STPTR_W
|
|
17U, // STR_D
|
|
17U, // STR_W
|
|
17U, // STX_B
|
|
17U, // STX_D
|
|
17U, // STX_H
|
|
17U, // STX_W
|
|
17U, // ST_B
|
|
17U, // ST_D
|
|
17U, // ST_H
|
|
17U, // ST_W
|
|
17U, // SUB_D
|
|
17U, // SUB_W
|
|
0U, // SYSCALL
|
|
0U, // TLBCLR
|
|
0U, // TLBFILL
|
|
0U, // TLBFLUSH
|
|
0U, // TLBRD
|
|
0U, // TLBSRCH
|
|
0U, // TLBWR
|
|
17U, // VABSD_B
|
|
17U, // VABSD_BU
|
|
17U, // VABSD_D
|
|
17U, // VABSD_DU
|
|
17U, // VABSD_H
|
|
17U, // VABSD_HU
|
|
17U, // VABSD_W
|
|
17U, // VABSD_WU
|
|
17U, // VADDA_B
|
|
17U, // VADDA_D
|
|
17U, // VADDA_H
|
|
17U, // VADDA_W
|
|
17U, // VADDI_BU
|
|
17U, // VADDI_DU
|
|
17U, // VADDI_HU
|
|
17U, // VADDI_WU
|
|
17U, // VADDWEV_D_W
|
|
17U, // VADDWEV_D_WU
|
|
17U, // VADDWEV_D_WU_W
|
|
17U, // VADDWEV_H_B
|
|
17U, // VADDWEV_H_BU
|
|
17U, // VADDWEV_H_BU_B
|
|
17U, // VADDWEV_Q_D
|
|
17U, // VADDWEV_Q_DU
|
|
17U, // VADDWEV_Q_DU_D
|
|
17U, // VADDWEV_W_H
|
|
17U, // VADDWEV_W_HU
|
|
17U, // VADDWEV_W_HU_H
|
|
17U, // VADDWOD_D_W
|
|
17U, // VADDWOD_D_WU
|
|
17U, // VADDWOD_D_WU_W
|
|
17U, // VADDWOD_H_B
|
|
17U, // VADDWOD_H_BU
|
|
17U, // VADDWOD_H_BU_B
|
|
17U, // VADDWOD_Q_D
|
|
17U, // VADDWOD_Q_DU
|
|
17U, // VADDWOD_Q_DU_D
|
|
17U, // VADDWOD_W_H
|
|
17U, // VADDWOD_W_HU
|
|
17U, // VADDWOD_W_HU_H
|
|
17U, // VADD_B
|
|
17U, // VADD_D
|
|
17U, // VADD_H
|
|
17U, // VADD_Q
|
|
17U, // VADD_W
|
|
17U, // VANDI_B
|
|
17U, // VANDN_V
|
|
17U, // VAND_V
|
|
17U, // VAVGR_B
|
|
17U, // VAVGR_BU
|
|
17U, // VAVGR_D
|
|
17U, // VAVGR_DU
|
|
17U, // VAVGR_H
|
|
17U, // VAVGR_HU
|
|
17U, // VAVGR_W
|
|
17U, // VAVGR_WU
|
|
17U, // VAVG_B
|
|
17U, // VAVG_BU
|
|
17U, // VAVG_D
|
|
17U, // VAVG_DU
|
|
17U, // VAVG_H
|
|
17U, // VAVG_HU
|
|
17U, // VAVG_W
|
|
17U, // VAVG_WU
|
|
17U, // VBITCLRI_B
|
|
17U, // VBITCLRI_D
|
|
17U, // VBITCLRI_H
|
|
17U, // VBITCLRI_W
|
|
17U, // VBITCLR_B
|
|
17U, // VBITCLR_D
|
|
17U, // VBITCLR_H
|
|
17U, // VBITCLR_W
|
|
17U, // VBITREVI_B
|
|
17U, // VBITREVI_D
|
|
17U, // VBITREVI_H
|
|
17U, // VBITREVI_W
|
|
17U, // VBITREV_B
|
|
17U, // VBITREV_D
|
|
17U, // VBITREV_H
|
|
17U, // VBITREV_W
|
|
9U, // VBITSELI_B
|
|
145U, // VBITSEL_V
|
|
17U, // VBITSETI_B
|
|
17U, // VBITSETI_D
|
|
17U, // VBITSETI_H
|
|
17U, // VBITSETI_W
|
|
17U, // VBITSET_B
|
|
17U, // VBITSET_D
|
|
17U, // VBITSET_H
|
|
17U, // VBITSET_W
|
|
17U, // VBSLL_V
|
|
17U, // VBSRL_V
|
|
1U, // VCLO_B
|
|
1U, // VCLO_D
|
|
1U, // VCLO_H
|
|
1U, // VCLO_W
|
|
1U, // VCLZ_B
|
|
1U, // VCLZ_D
|
|
1U, // VCLZ_H
|
|
1U, // VCLZ_W
|
|
17U, // VDIV_B
|
|
17U, // VDIV_BU
|
|
17U, // VDIV_D
|
|
17U, // VDIV_DU
|
|
17U, // VDIV_H
|
|
17U, // VDIV_HU
|
|
17U, // VDIV_W
|
|
17U, // VDIV_WU
|
|
1U, // VEXT2XV_DU_BU
|
|
1U, // VEXT2XV_DU_HU
|
|
1U, // VEXT2XV_DU_WU
|
|
1U, // VEXT2XV_D_B
|
|
1U, // VEXT2XV_D_H
|
|
1U, // VEXT2XV_D_W
|
|
1U, // VEXT2XV_HU_BU
|
|
1U, // VEXT2XV_H_B
|
|
1U, // VEXT2XV_WU_BU
|
|
1U, // VEXT2XV_WU_HU
|
|
1U, // VEXT2XV_W_B
|
|
1U, // VEXT2XV_W_H
|
|
1U, // VEXTH_DU_WU
|
|
1U, // VEXTH_D_W
|
|
1U, // VEXTH_HU_BU
|
|
1U, // VEXTH_H_B
|
|
1U, // VEXTH_QU_DU
|
|
1U, // VEXTH_Q_D
|
|
1U, // VEXTH_WU_HU
|
|
1U, // VEXTH_W_H
|
|
1U, // VEXTL_QU_DU
|
|
1U, // VEXTL_Q_D
|
|
9U, // VEXTRINS_B
|
|
9U, // VEXTRINS_D
|
|
9U, // VEXTRINS_H
|
|
9U, // VEXTRINS_W
|
|
17U, // VFADD_D
|
|
17U, // VFADD_S
|
|
1U, // VFCLASS_D
|
|
1U, // VFCLASS_S
|
|
17U, // VFCMP_CAF_D
|
|
17U, // VFCMP_CAF_S
|
|
17U, // VFCMP_CEQ_D
|
|
17U, // VFCMP_CEQ_S
|
|
17U, // VFCMP_CLE_D
|
|
17U, // VFCMP_CLE_S
|
|
17U, // VFCMP_CLT_D
|
|
17U, // VFCMP_CLT_S
|
|
17U, // VFCMP_CNE_D
|
|
17U, // VFCMP_CNE_S
|
|
17U, // VFCMP_COR_D
|
|
17U, // VFCMP_COR_S
|
|
17U, // VFCMP_CUEQ_D
|
|
17U, // VFCMP_CUEQ_S
|
|
17U, // VFCMP_CULE_D
|
|
17U, // VFCMP_CULE_S
|
|
17U, // VFCMP_CULT_D
|
|
17U, // VFCMP_CULT_S
|
|
17U, // VFCMP_CUNE_D
|
|
17U, // VFCMP_CUNE_S
|
|
17U, // VFCMP_CUN_D
|
|
17U, // VFCMP_CUN_S
|
|
17U, // VFCMP_SAF_D
|
|
17U, // VFCMP_SAF_S
|
|
17U, // VFCMP_SEQ_D
|
|
17U, // VFCMP_SEQ_S
|
|
17U, // VFCMP_SLE_D
|
|
17U, // VFCMP_SLE_S
|
|
17U, // VFCMP_SLT_D
|
|
17U, // VFCMP_SLT_S
|
|
17U, // VFCMP_SNE_D
|
|
17U, // VFCMP_SNE_S
|
|
17U, // VFCMP_SOR_D
|
|
17U, // VFCMP_SOR_S
|
|
17U, // VFCMP_SUEQ_D
|
|
17U, // VFCMP_SUEQ_S
|
|
17U, // VFCMP_SULE_D
|
|
17U, // VFCMP_SULE_S
|
|
17U, // VFCMP_SULT_D
|
|
17U, // VFCMP_SULT_S
|
|
17U, // VFCMP_SUNE_D
|
|
17U, // VFCMP_SUNE_S
|
|
17U, // VFCMP_SUN_D
|
|
17U, // VFCMP_SUN_S
|
|
1U, // VFCVTH_D_S
|
|
1U, // VFCVTH_S_H
|
|
1U, // VFCVTL_D_S
|
|
1U, // VFCVTL_S_H
|
|
17U, // VFCVT_H_S
|
|
17U, // VFCVT_S_D
|
|
17U, // VFDIV_D
|
|
17U, // VFDIV_S
|
|
1U, // VFFINTH_D_W
|
|
1U, // VFFINTL_D_W
|
|
1U, // VFFINT_D_L
|
|
1U, // VFFINT_D_LU
|
|
17U, // VFFINT_S_L
|
|
1U, // VFFINT_S_W
|
|
1U, // VFFINT_S_WU
|
|
1U, // VFLOGB_D
|
|
1U, // VFLOGB_S
|
|
145U, // VFMADD_D
|
|
145U, // VFMADD_S
|
|
17U, // VFMAXA_D
|
|
17U, // VFMAXA_S
|
|
17U, // VFMAX_D
|
|
17U, // VFMAX_S
|
|
17U, // VFMINA_D
|
|
17U, // VFMINA_S
|
|
17U, // VFMIN_D
|
|
17U, // VFMIN_S
|
|
145U, // VFMSUB_D
|
|
145U, // VFMSUB_S
|
|
17U, // VFMUL_D
|
|
17U, // VFMUL_S
|
|
145U, // VFNMADD_D
|
|
145U, // VFNMADD_S
|
|
145U, // VFNMSUB_D
|
|
145U, // VFNMSUB_S
|
|
1U, // VFRECIPE_D
|
|
1U, // VFRECIPE_S
|
|
1U, // VFRECIP_D
|
|
1U, // VFRECIP_S
|
|
1U, // VFRINTRM_D
|
|
1U, // VFRINTRM_S
|
|
1U, // VFRINTRNE_D
|
|
1U, // VFRINTRNE_S
|
|
1U, // VFRINTRP_D
|
|
1U, // VFRINTRP_S
|
|
1U, // VFRINTRZ_D
|
|
1U, // VFRINTRZ_S
|
|
1U, // VFRINT_D
|
|
1U, // VFRINT_S
|
|
1U, // VFRSQRTE_D
|
|
1U, // VFRSQRTE_S
|
|
1U, // VFRSQRT_D
|
|
1U, // VFRSQRT_S
|
|
9U, // VFRSTPI_B
|
|
9U, // VFRSTPI_H
|
|
9U, // VFRSTP_B
|
|
9U, // VFRSTP_H
|
|
1U, // VFSQRT_D
|
|
1U, // VFSQRT_S
|
|
17U, // VFSUB_D
|
|
17U, // VFSUB_S
|
|
1U, // VFTINTH_L_S
|
|
1U, // VFTINTL_L_S
|
|
1U, // VFTINTRMH_L_S
|
|
1U, // VFTINTRML_L_S
|
|
1U, // VFTINTRM_L_D
|
|
17U, // VFTINTRM_W_D
|
|
1U, // VFTINTRM_W_S
|
|
1U, // VFTINTRNEH_L_S
|
|
1U, // VFTINTRNEL_L_S
|
|
1U, // VFTINTRNE_L_D
|
|
17U, // VFTINTRNE_W_D
|
|
1U, // VFTINTRNE_W_S
|
|
1U, // VFTINTRPH_L_S
|
|
1U, // VFTINTRPL_L_S
|
|
1U, // VFTINTRP_L_D
|
|
17U, // VFTINTRP_W_D
|
|
1U, // VFTINTRP_W_S
|
|
1U, // VFTINTRZH_L_S
|
|
1U, // VFTINTRZL_L_S
|
|
1U, // VFTINTRZ_LU_D
|
|
1U, // VFTINTRZ_L_D
|
|
1U, // VFTINTRZ_WU_S
|
|
17U, // VFTINTRZ_W_D
|
|
1U, // VFTINTRZ_W_S
|
|
1U, // VFTINT_LU_D
|
|
1U, // VFTINT_L_D
|
|
1U, // VFTINT_WU_S
|
|
17U, // VFTINT_W_D
|
|
1U, // VFTINT_W_S
|
|
17U, // VHADDW_DU_WU
|
|
17U, // VHADDW_D_W
|
|
17U, // VHADDW_HU_BU
|
|
17U, // VHADDW_H_B
|
|
17U, // VHADDW_QU_DU
|
|
17U, // VHADDW_Q_D
|
|
17U, // VHADDW_WU_HU
|
|
17U, // VHADDW_W_H
|
|
17U, // VHSUBW_DU_WU
|
|
17U, // VHSUBW_D_W
|
|
17U, // VHSUBW_HU_BU
|
|
17U, // VHSUBW_H_B
|
|
17U, // VHSUBW_QU_DU
|
|
17U, // VHSUBW_Q_D
|
|
17U, // VHSUBW_WU_HU
|
|
17U, // VHSUBW_W_H
|
|
17U, // VILVH_B
|
|
17U, // VILVH_D
|
|
17U, // VILVH_H
|
|
17U, // VILVH_W
|
|
17U, // VILVL_B
|
|
17U, // VILVL_D
|
|
17U, // VILVL_H
|
|
17U, // VILVL_W
|
|
9U, // VINSGR2VR_B
|
|
9U, // VINSGR2VR_D
|
|
9U, // VINSGR2VR_H
|
|
9U, // VINSGR2VR_W
|
|
17U, // VLD
|
|
1U, // VLDI
|
|
17U, // VLDREPL_B
|
|
17U, // VLDREPL_D
|
|
17U, // VLDREPL_H
|
|
17U, // VLDREPL_W
|
|
17U, // VLDX
|
|
9U, // VMADDWEV_D_W
|
|
9U, // VMADDWEV_D_WU
|
|
9U, // VMADDWEV_D_WU_W
|
|
9U, // VMADDWEV_H_B
|
|
9U, // VMADDWEV_H_BU
|
|
9U, // VMADDWEV_H_BU_B
|
|
9U, // VMADDWEV_Q_D
|
|
9U, // VMADDWEV_Q_DU
|
|
9U, // VMADDWEV_Q_DU_D
|
|
9U, // VMADDWEV_W_H
|
|
9U, // VMADDWEV_W_HU
|
|
9U, // VMADDWEV_W_HU_H
|
|
9U, // VMADDWOD_D_W
|
|
9U, // VMADDWOD_D_WU
|
|
9U, // VMADDWOD_D_WU_W
|
|
9U, // VMADDWOD_H_B
|
|
9U, // VMADDWOD_H_BU
|
|
9U, // VMADDWOD_H_BU_B
|
|
9U, // VMADDWOD_Q_D
|
|
9U, // VMADDWOD_Q_DU
|
|
9U, // VMADDWOD_Q_DU_D
|
|
9U, // VMADDWOD_W_H
|
|
9U, // VMADDWOD_W_HU
|
|
9U, // VMADDWOD_W_HU_H
|
|
9U, // VMADD_B
|
|
9U, // VMADD_D
|
|
9U, // VMADD_H
|
|
9U, // VMADD_W
|
|
17U, // VMAXI_B
|
|
17U, // VMAXI_BU
|
|
17U, // VMAXI_D
|
|
17U, // VMAXI_DU
|
|
17U, // VMAXI_H
|
|
17U, // VMAXI_HU
|
|
17U, // VMAXI_W
|
|
17U, // VMAXI_WU
|
|
17U, // VMAX_B
|
|
17U, // VMAX_BU
|
|
17U, // VMAX_D
|
|
17U, // VMAX_DU
|
|
17U, // VMAX_H
|
|
17U, // VMAX_HU
|
|
17U, // VMAX_W
|
|
17U, // VMAX_WU
|
|
17U, // VMINI_B
|
|
17U, // VMINI_BU
|
|
17U, // VMINI_D
|
|
17U, // VMINI_DU
|
|
17U, // VMINI_H
|
|
17U, // VMINI_HU
|
|
17U, // VMINI_W
|
|
17U, // VMINI_WU
|
|
17U, // VMIN_B
|
|
17U, // VMIN_BU
|
|
17U, // VMIN_D
|
|
17U, // VMIN_DU
|
|
17U, // VMIN_H
|
|
17U, // VMIN_HU
|
|
17U, // VMIN_W
|
|
17U, // VMIN_WU
|
|
17U, // VMOD_B
|
|
17U, // VMOD_BU
|
|
17U, // VMOD_D
|
|
17U, // VMOD_DU
|
|
17U, // VMOD_H
|
|
17U, // VMOD_HU
|
|
17U, // VMOD_W
|
|
17U, // VMOD_WU
|
|
1U, // VMSKGEZ_B
|
|
1U, // VMSKLTZ_B
|
|
1U, // VMSKLTZ_D
|
|
1U, // VMSKLTZ_H
|
|
1U, // VMSKLTZ_W
|
|
1U, // VMSKNZ_B
|
|
9U, // VMSUB_B
|
|
9U, // VMSUB_D
|
|
9U, // VMSUB_H
|
|
9U, // VMSUB_W
|
|
17U, // VMUH_B
|
|
17U, // VMUH_BU
|
|
17U, // VMUH_D
|
|
17U, // VMUH_DU
|
|
17U, // VMUH_H
|
|
17U, // VMUH_HU
|
|
17U, // VMUH_W
|
|
17U, // VMUH_WU
|
|
17U, // VMULWEV_D_W
|
|
17U, // VMULWEV_D_WU
|
|
17U, // VMULWEV_D_WU_W
|
|
17U, // VMULWEV_H_B
|
|
17U, // VMULWEV_H_BU
|
|
17U, // VMULWEV_H_BU_B
|
|
17U, // VMULWEV_Q_D
|
|
17U, // VMULWEV_Q_DU
|
|
17U, // VMULWEV_Q_DU_D
|
|
17U, // VMULWEV_W_H
|
|
17U, // VMULWEV_W_HU
|
|
17U, // VMULWEV_W_HU_H
|
|
17U, // VMULWOD_D_W
|
|
17U, // VMULWOD_D_WU
|
|
17U, // VMULWOD_D_WU_W
|
|
17U, // VMULWOD_H_B
|
|
17U, // VMULWOD_H_BU
|
|
17U, // VMULWOD_H_BU_B
|
|
17U, // VMULWOD_Q_D
|
|
17U, // VMULWOD_Q_DU
|
|
17U, // VMULWOD_Q_DU_D
|
|
17U, // VMULWOD_W_H
|
|
17U, // VMULWOD_W_HU
|
|
17U, // VMULWOD_W_HU_H
|
|
17U, // VMUL_B
|
|
17U, // VMUL_D
|
|
17U, // VMUL_H
|
|
17U, // VMUL_W
|
|
1U, // VNEG_B
|
|
1U, // VNEG_D
|
|
1U, // VNEG_H
|
|
1U, // VNEG_W
|
|
17U, // VNORI_B
|
|
17U, // VNOR_V
|
|
17U, // VORI_B
|
|
17U, // VORN_V
|
|
17U, // VOR_V
|
|
17U, // VPACKEV_B
|
|
17U, // VPACKEV_D
|
|
17U, // VPACKEV_H
|
|
17U, // VPACKEV_W
|
|
17U, // VPACKOD_B
|
|
17U, // VPACKOD_D
|
|
17U, // VPACKOD_H
|
|
17U, // VPACKOD_W
|
|
1U, // VPCNT_B
|
|
1U, // VPCNT_D
|
|
1U, // VPCNT_H
|
|
1U, // VPCNT_W
|
|
9U, // VPERMI_W
|
|
17U, // VPICKEV_B
|
|
17U, // VPICKEV_D
|
|
17U, // VPICKEV_H
|
|
17U, // VPICKEV_W
|
|
17U, // VPICKOD_B
|
|
17U, // VPICKOD_D
|
|
17U, // VPICKOD_H
|
|
17U, // VPICKOD_W
|
|
17U, // VPICKVE2GR_B
|
|
17U, // VPICKVE2GR_BU
|
|
17U, // VPICKVE2GR_D
|
|
17U, // VPICKVE2GR_DU
|
|
17U, // VPICKVE2GR_H
|
|
17U, // VPICKVE2GR_HU
|
|
17U, // VPICKVE2GR_W
|
|
17U, // VPICKVE2GR_WU
|
|
1U, // VREPLGR2VR_B
|
|
1U, // VREPLGR2VR_D
|
|
1U, // VREPLGR2VR_H
|
|
1U, // VREPLGR2VR_W
|
|
17U, // VREPLVEI_B
|
|
17U, // VREPLVEI_D
|
|
17U, // VREPLVEI_H
|
|
17U, // VREPLVEI_W
|
|
17U, // VREPLVE_B
|
|
17U, // VREPLVE_D
|
|
17U, // VREPLVE_H
|
|
17U, // VREPLVE_W
|
|
17U, // VROTRI_B
|
|
17U, // VROTRI_D
|
|
17U, // VROTRI_H
|
|
17U, // VROTRI_W
|
|
17U, // VROTR_B
|
|
17U, // VROTR_D
|
|
17U, // VROTR_H
|
|
17U, // VROTR_W
|
|
17U, // VSADD_B
|
|
17U, // VSADD_BU
|
|
17U, // VSADD_D
|
|
17U, // VSADD_DU
|
|
17U, // VSADD_H
|
|
17U, // VSADD_HU
|
|
17U, // VSADD_W
|
|
17U, // VSADD_WU
|
|
17U, // VSAT_B
|
|
17U, // VSAT_BU
|
|
17U, // VSAT_D
|
|
17U, // VSAT_DU
|
|
17U, // VSAT_H
|
|
17U, // VSAT_HU
|
|
17U, // VSAT_W
|
|
17U, // VSAT_WU
|
|
17U, // VSEQI_B
|
|
17U, // VSEQI_D
|
|
17U, // VSEQI_H
|
|
17U, // VSEQI_W
|
|
17U, // VSEQ_B
|
|
17U, // VSEQ_D
|
|
17U, // VSEQ_H
|
|
17U, // VSEQ_W
|
|
1U, // VSETALLNEZ_B
|
|
1U, // VSETALLNEZ_D
|
|
1U, // VSETALLNEZ_H
|
|
1U, // VSETALLNEZ_W
|
|
1U, // VSETANYEQZ_B
|
|
1U, // VSETANYEQZ_D
|
|
1U, // VSETANYEQZ_H
|
|
1U, // VSETANYEQZ_W
|
|
1U, // VSETEQZ_V
|
|
1U, // VSETNEZ_V
|
|
17U, // VSHUF4I_B
|
|
9U, // VSHUF4I_D
|
|
17U, // VSHUF4I_H
|
|
17U, // VSHUF4I_W
|
|
145U, // VSHUF_B
|
|
9U, // VSHUF_D
|
|
9U, // VSHUF_H
|
|
9U, // VSHUF_W
|
|
17U, // VSIGNCOV_B
|
|
17U, // VSIGNCOV_D
|
|
17U, // VSIGNCOV_H
|
|
17U, // VSIGNCOV_W
|
|
17U, // VSLEI_B
|
|
17U, // VSLEI_BU
|
|
17U, // VSLEI_D
|
|
17U, // VSLEI_DU
|
|
17U, // VSLEI_H
|
|
17U, // VSLEI_HU
|
|
17U, // VSLEI_W
|
|
17U, // VSLEI_WU
|
|
17U, // VSLE_B
|
|
17U, // VSLE_BU
|
|
17U, // VSLE_D
|
|
17U, // VSLE_DU
|
|
17U, // VSLE_H
|
|
17U, // VSLE_HU
|
|
17U, // VSLE_W
|
|
17U, // VSLE_WU
|
|
17U, // VSLLI_B
|
|
17U, // VSLLI_D
|
|
17U, // VSLLI_H
|
|
17U, // VSLLI_W
|
|
17U, // VSLLWIL_DU_WU
|
|
17U, // VSLLWIL_D_W
|
|
17U, // VSLLWIL_HU_BU
|
|
17U, // VSLLWIL_H_B
|
|
17U, // VSLLWIL_WU_HU
|
|
17U, // VSLLWIL_W_H
|
|
17U, // VSLL_B
|
|
17U, // VSLL_D
|
|
17U, // VSLL_H
|
|
17U, // VSLL_W
|
|
17U, // VSLTI_B
|
|
17U, // VSLTI_BU
|
|
17U, // VSLTI_D
|
|
17U, // VSLTI_DU
|
|
17U, // VSLTI_H
|
|
17U, // VSLTI_HU
|
|
17U, // VSLTI_W
|
|
17U, // VSLTI_WU
|
|
17U, // VSLT_B
|
|
17U, // VSLT_BU
|
|
17U, // VSLT_D
|
|
17U, // VSLT_DU
|
|
17U, // VSLT_H
|
|
17U, // VSLT_HU
|
|
17U, // VSLT_W
|
|
17U, // VSLT_WU
|
|
17U, // VSRAI_B
|
|
17U, // VSRAI_D
|
|
17U, // VSRAI_H
|
|
17U, // VSRAI_W
|
|
9U, // VSRANI_B_H
|
|
9U, // VSRANI_D_Q
|
|
9U, // VSRANI_H_W
|
|
9U, // VSRANI_W_D
|
|
17U, // VSRAN_B_H
|
|
17U, // VSRAN_H_W
|
|
17U, // VSRAN_W_D
|
|
17U, // VSRARI_B
|
|
17U, // VSRARI_D
|
|
17U, // VSRARI_H
|
|
17U, // VSRARI_W
|
|
9U, // VSRARNI_B_H
|
|
9U, // VSRARNI_D_Q
|
|
9U, // VSRARNI_H_W
|
|
9U, // VSRARNI_W_D
|
|
17U, // VSRARN_B_H
|
|
17U, // VSRARN_H_W
|
|
17U, // VSRARN_W_D
|
|
17U, // VSRAR_B
|
|
17U, // VSRAR_D
|
|
17U, // VSRAR_H
|
|
17U, // VSRAR_W
|
|
17U, // VSRA_B
|
|
17U, // VSRA_D
|
|
17U, // VSRA_H
|
|
17U, // VSRA_W
|
|
17U, // VSRLI_B
|
|
17U, // VSRLI_D
|
|
17U, // VSRLI_H
|
|
17U, // VSRLI_W
|
|
9U, // VSRLNI_B_H
|
|
9U, // VSRLNI_D_Q
|
|
9U, // VSRLNI_H_W
|
|
9U, // VSRLNI_W_D
|
|
17U, // VSRLN_B_H
|
|
17U, // VSRLN_H_W
|
|
17U, // VSRLN_W_D
|
|
17U, // VSRLRI_B
|
|
17U, // VSRLRI_D
|
|
17U, // VSRLRI_H
|
|
17U, // VSRLRI_W
|
|
9U, // VSRLRNI_B_H
|
|
9U, // VSRLRNI_D_Q
|
|
9U, // VSRLRNI_H_W
|
|
9U, // VSRLRNI_W_D
|
|
17U, // VSRLRN_B_H
|
|
17U, // VSRLRN_H_W
|
|
17U, // VSRLRN_W_D
|
|
17U, // VSRLR_B
|
|
17U, // VSRLR_D
|
|
17U, // VSRLR_H
|
|
17U, // VSRLR_W
|
|
17U, // VSRL_B
|
|
17U, // VSRL_D
|
|
17U, // VSRL_H
|
|
17U, // VSRL_W
|
|
9U, // VSSRANI_BU_H
|
|
9U, // VSSRANI_B_H
|
|
9U, // VSSRANI_DU_Q
|
|
9U, // VSSRANI_D_Q
|
|
9U, // VSSRANI_HU_W
|
|
9U, // VSSRANI_H_W
|
|
9U, // VSSRANI_WU_D
|
|
9U, // VSSRANI_W_D
|
|
17U, // VSSRAN_BU_H
|
|
17U, // VSSRAN_B_H
|
|
17U, // VSSRAN_HU_W
|
|
17U, // VSSRAN_H_W
|
|
17U, // VSSRAN_WU_D
|
|
17U, // VSSRAN_W_D
|
|
9U, // VSSRARNI_BU_H
|
|
9U, // VSSRARNI_B_H
|
|
9U, // VSSRARNI_DU_Q
|
|
9U, // VSSRARNI_D_Q
|
|
9U, // VSSRARNI_HU_W
|
|
9U, // VSSRARNI_H_W
|
|
9U, // VSSRARNI_WU_D
|
|
9U, // VSSRARNI_W_D
|
|
17U, // VSSRARN_BU_H
|
|
17U, // VSSRARN_B_H
|
|
17U, // VSSRARN_HU_W
|
|
17U, // VSSRARN_H_W
|
|
17U, // VSSRARN_WU_D
|
|
17U, // VSSRARN_W_D
|
|
9U, // VSSRLNI_BU_H
|
|
9U, // VSSRLNI_B_H
|
|
9U, // VSSRLNI_DU_Q
|
|
9U, // VSSRLNI_D_Q
|
|
9U, // VSSRLNI_HU_W
|
|
9U, // VSSRLNI_H_W
|
|
9U, // VSSRLNI_WU_D
|
|
9U, // VSSRLNI_W_D
|
|
17U, // VSSRLN_BU_H
|
|
17U, // VSSRLN_B_H
|
|
17U, // VSSRLN_HU_W
|
|
17U, // VSSRLN_H_W
|
|
17U, // VSSRLN_WU_D
|
|
17U, // VSSRLN_W_D
|
|
9U, // VSSRLRNI_BU_H
|
|
9U, // VSSRLRNI_B_H
|
|
9U, // VSSRLRNI_DU_Q
|
|
9U, // VSSRLRNI_D_Q
|
|
9U, // VSSRLRNI_HU_W
|
|
9U, // VSSRLRNI_H_W
|
|
9U, // VSSRLRNI_WU_D
|
|
9U, // VSSRLRNI_W_D
|
|
17U, // VSSRLRN_BU_H
|
|
17U, // VSSRLRN_B_H
|
|
17U, // VSSRLRN_HU_W
|
|
17U, // VSSRLRN_H_W
|
|
17U, // VSSRLRN_WU_D
|
|
17U, // VSSRLRN_W_D
|
|
17U, // VSSUB_B
|
|
17U, // VSSUB_BU
|
|
17U, // VSSUB_D
|
|
17U, // VSSUB_DU
|
|
17U, // VSSUB_H
|
|
17U, // VSSUB_HU
|
|
17U, // VSSUB_W
|
|
17U, // VSSUB_WU
|
|
17U, // VST
|
|
145U, // VSTELM_B
|
|
145U, // VSTELM_D
|
|
145U, // VSTELM_H
|
|
145U, // VSTELM_W
|
|
17U, // VSTX
|
|
17U, // VSUBI_BU
|
|
17U, // VSUBI_DU
|
|
17U, // VSUBI_HU
|
|
17U, // VSUBI_WU
|
|
17U, // VSUBWEV_D_W
|
|
17U, // VSUBWEV_D_WU
|
|
17U, // VSUBWEV_H_B
|
|
17U, // VSUBWEV_H_BU
|
|
17U, // VSUBWEV_Q_D
|
|
17U, // VSUBWEV_Q_DU
|
|
17U, // VSUBWEV_W_H
|
|
17U, // VSUBWEV_W_HU
|
|
17U, // VSUBWOD_D_W
|
|
17U, // VSUBWOD_D_WU
|
|
17U, // VSUBWOD_H_B
|
|
17U, // VSUBWOD_H_BU
|
|
17U, // VSUBWOD_Q_D
|
|
17U, // VSUBWOD_Q_DU
|
|
17U, // VSUBWOD_W_H
|
|
17U, // VSUBWOD_W_HU
|
|
17U, // VSUB_B
|
|
17U, // VSUB_D
|
|
17U, // VSUB_H
|
|
17U, // VSUB_Q
|
|
17U, // VSUB_W
|
|
17U, // VXORI_B
|
|
17U, // VXOR_V
|
|
1U, // X86ADC_B
|
|
1U, // X86ADC_D
|
|
1U, // X86ADC_H
|
|
1U, // X86ADC_W
|
|
1U, // X86ADD_B
|
|
1U, // X86ADD_D
|
|
1U, // X86ADD_DU
|
|
1U, // X86ADD_H
|
|
1U, // X86ADD_W
|
|
1U, // X86ADD_WU
|
|
1U, // X86AND_B
|
|
1U, // X86AND_D
|
|
1U, // X86AND_H
|
|
1U, // X86AND_W
|
|
0U, // X86CLRTM
|
|
0U, // X86DECTOP
|
|
0U, // X86DEC_B
|
|
0U, // X86DEC_D
|
|
0U, // X86DEC_H
|
|
0U, // X86DEC_W
|
|
0U, // X86INCTOP
|
|
0U, // X86INC_B
|
|
0U, // X86INC_D
|
|
0U, // X86INC_H
|
|
0U, // X86INC_W
|
|
1U, // X86MFFLAG
|
|
0U, // X86MFTOP
|
|
1U, // X86MTFLAG
|
|
0U, // X86MTTOP
|
|
1U, // X86MUL_B
|
|
1U, // X86MUL_BU
|
|
1U, // X86MUL_D
|
|
1U, // X86MUL_DU
|
|
1U, // X86MUL_H
|
|
1U, // X86MUL_HU
|
|
1U, // X86MUL_W
|
|
1U, // X86MUL_WU
|
|
1U, // X86OR_B
|
|
1U, // X86OR_D
|
|
1U, // X86OR_H
|
|
1U, // X86OR_W
|
|
1U, // X86RCLI_B
|
|
1U, // X86RCLI_D
|
|
1U, // X86RCLI_H
|
|
1U, // X86RCLI_W
|
|
1U, // X86RCL_B
|
|
1U, // X86RCL_D
|
|
1U, // X86RCL_H
|
|
1U, // X86RCL_W
|
|
1U, // X86RCRI_B
|
|
1U, // X86RCRI_D
|
|
1U, // X86RCRI_H
|
|
1U, // X86RCRI_W
|
|
1U, // X86RCR_B
|
|
1U, // X86RCR_D
|
|
1U, // X86RCR_H
|
|
1U, // X86RCR_W
|
|
1U, // X86ROTLI_B
|
|
1U, // X86ROTLI_D
|
|
1U, // X86ROTLI_H
|
|
1U, // X86ROTLI_W
|
|
1U, // X86ROTL_B
|
|
1U, // X86ROTL_D
|
|
1U, // X86ROTL_H
|
|
1U, // X86ROTL_W
|
|
1U, // X86ROTRI_B
|
|
1U, // X86ROTRI_D
|
|
1U, // X86ROTRI_H
|
|
1U, // X86ROTRI_W
|
|
1U, // X86ROTR_B
|
|
1U, // X86ROTR_D
|
|
1U, // X86ROTR_H
|
|
1U, // X86ROTR_W
|
|
1U, // X86SBC_B
|
|
1U, // X86SBC_D
|
|
1U, // X86SBC_H
|
|
1U, // X86SBC_W
|
|
17U, // X86SETTAG
|
|
0U, // X86SETTM
|
|
1U, // X86SLLI_B
|
|
1U, // X86SLLI_D
|
|
1U, // X86SLLI_H
|
|
1U, // X86SLLI_W
|
|
1U, // X86SLL_B
|
|
1U, // X86SLL_D
|
|
1U, // X86SLL_H
|
|
1U, // X86SLL_W
|
|
1U, // X86SRAI_B
|
|
1U, // X86SRAI_D
|
|
1U, // X86SRAI_H
|
|
1U, // X86SRAI_W
|
|
1U, // X86SRA_B
|
|
1U, // X86SRA_D
|
|
1U, // X86SRA_H
|
|
1U, // X86SRA_W
|
|
1U, // X86SRLI_B
|
|
1U, // X86SRLI_D
|
|
1U, // X86SRLI_H
|
|
1U, // X86SRLI_W
|
|
1U, // X86SRL_B
|
|
1U, // X86SRL_D
|
|
1U, // X86SRL_H
|
|
1U, // X86SRL_W
|
|
1U, // X86SUB_B
|
|
1U, // X86SUB_D
|
|
1U, // X86SUB_DU
|
|
1U, // X86SUB_H
|
|
1U, // X86SUB_W
|
|
1U, // X86SUB_WU
|
|
1U, // X86XOR_B
|
|
1U, // X86XOR_D
|
|
1U, // X86XOR_H
|
|
1U, // X86XOR_W
|
|
17U, // XOR
|
|
17U, // XORI
|
|
17U, // XVABSD_B
|
|
17U, // XVABSD_BU
|
|
17U, // XVABSD_D
|
|
17U, // XVABSD_DU
|
|
17U, // XVABSD_H
|
|
17U, // XVABSD_HU
|
|
17U, // XVABSD_W
|
|
17U, // XVABSD_WU
|
|
17U, // XVADDA_B
|
|
17U, // XVADDA_D
|
|
17U, // XVADDA_H
|
|
17U, // XVADDA_W
|
|
17U, // XVADDI_BU
|
|
17U, // XVADDI_DU
|
|
17U, // XVADDI_HU
|
|
17U, // XVADDI_WU
|
|
17U, // XVADDWEV_D_W
|
|
17U, // XVADDWEV_D_WU
|
|
17U, // XVADDWEV_D_WU_W
|
|
17U, // XVADDWEV_H_B
|
|
17U, // XVADDWEV_H_BU
|
|
17U, // XVADDWEV_H_BU_B
|
|
17U, // XVADDWEV_Q_D
|
|
17U, // XVADDWEV_Q_DU
|
|
17U, // XVADDWEV_Q_DU_D
|
|
17U, // XVADDWEV_W_H
|
|
17U, // XVADDWEV_W_HU
|
|
17U, // XVADDWEV_W_HU_H
|
|
17U, // XVADDWOD_D_W
|
|
17U, // XVADDWOD_D_WU
|
|
17U, // XVADDWOD_D_WU_W
|
|
17U, // XVADDWOD_H_B
|
|
17U, // XVADDWOD_H_BU
|
|
17U, // XVADDWOD_H_BU_B
|
|
17U, // XVADDWOD_Q_D
|
|
17U, // XVADDWOD_Q_DU
|
|
17U, // XVADDWOD_Q_DU_D
|
|
17U, // XVADDWOD_W_H
|
|
17U, // XVADDWOD_W_HU
|
|
17U, // XVADDWOD_W_HU_H
|
|
17U, // XVADD_B
|
|
17U, // XVADD_D
|
|
17U, // XVADD_H
|
|
17U, // XVADD_Q
|
|
17U, // XVADD_W
|
|
17U, // XVANDI_B
|
|
17U, // XVANDN_V
|
|
17U, // XVAND_V
|
|
17U, // XVAVGR_B
|
|
17U, // XVAVGR_BU
|
|
17U, // XVAVGR_D
|
|
17U, // XVAVGR_DU
|
|
17U, // XVAVGR_H
|
|
17U, // XVAVGR_HU
|
|
17U, // XVAVGR_W
|
|
17U, // XVAVGR_WU
|
|
17U, // XVAVG_B
|
|
17U, // XVAVG_BU
|
|
17U, // XVAVG_D
|
|
17U, // XVAVG_DU
|
|
17U, // XVAVG_H
|
|
17U, // XVAVG_HU
|
|
17U, // XVAVG_W
|
|
17U, // XVAVG_WU
|
|
17U, // XVBITCLRI_B
|
|
17U, // XVBITCLRI_D
|
|
17U, // XVBITCLRI_H
|
|
17U, // XVBITCLRI_W
|
|
17U, // XVBITCLR_B
|
|
17U, // XVBITCLR_D
|
|
17U, // XVBITCLR_H
|
|
17U, // XVBITCLR_W
|
|
17U, // XVBITREVI_B
|
|
17U, // XVBITREVI_D
|
|
17U, // XVBITREVI_H
|
|
17U, // XVBITREVI_W
|
|
17U, // XVBITREV_B
|
|
17U, // XVBITREV_D
|
|
17U, // XVBITREV_H
|
|
17U, // XVBITREV_W
|
|
9U, // XVBITSELI_B
|
|
145U, // XVBITSEL_V
|
|
17U, // XVBITSETI_B
|
|
17U, // XVBITSETI_D
|
|
17U, // XVBITSETI_H
|
|
17U, // XVBITSETI_W
|
|
17U, // XVBITSET_B
|
|
17U, // XVBITSET_D
|
|
17U, // XVBITSET_H
|
|
17U, // XVBITSET_W
|
|
17U, // XVBSLL_V
|
|
17U, // XVBSRL_V
|
|
1U, // XVCLO_B
|
|
1U, // XVCLO_D
|
|
1U, // XVCLO_H
|
|
1U, // XVCLO_W
|
|
1U, // XVCLZ_B
|
|
1U, // XVCLZ_D
|
|
1U, // XVCLZ_H
|
|
1U, // XVCLZ_W
|
|
17U, // XVDIV_B
|
|
17U, // XVDIV_BU
|
|
17U, // XVDIV_D
|
|
17U, // XVDIV_DU
|
|
17U, // XVDIV_H
|
|
17U, // XVDIV_HU
|
|
17U, // XVDIV_W
|
|
17U, // XVDIV_WU
|
|
1U, // XVEXTH_DU_WU
|
|
1U, // XVEXTH_D_W
|
|
1U, // XVEXTH_HU_BU
|
|
1U, // XVEXTH_H_B
|
|
1U, // XVEXTH_QU_DU
|
|
1U, // XVEXTH_Q_D
|
|
1U, // XVEXTH_WU_HU
|
|
1U, // XVEXTH_W_H
|
|
1U, // XVEXTL_QU_DU
|
|
1U, // XVEXTL_Q_D
|
|
9U, // XVEXTRINS_B
|
|
9U, // XVEXTRINS_D
|
|
9U, // XVEXTRINS_H
|
|
9U, // XVEXTRINS_W
|
|
17U, // XVFADD_D
|
|
17U, // XVFADD_S
|
|
1U, // XVFCLASS_D
|
|
1U, // XVFCLASS_S
|
|
17U, // XVFCMP_CAF_D
|
|
17U, // XVFCMP_CAF_S
|
|
17U, // XVFCMP_CEQ_D
|
|
17U, // XVFCMP_CEQ_S
|
|
17U, // XVFCMP_CLE_D
|
|
17U, // XVFCMP_CLE_S
|
|
17U, // XVFCMP_CLT_D
|
|
17U, // XVFCMP_CLT_S
|
|
17U, // XVFCMP_CNE_D
|
|
17U, // XVFCMP_CNE_S
|
|
17U, // XVFCMP_COR_D
|
|
17U, // XVFCMP_COR_S
|
|
17U, // XVFCMP_CUEQ_D
|
|
17U, // XVFCMP_CUEQ_S
|
|
17U, // XVFCMP_CULE_D
|
|
17U, // XVFCMP_CULE_S
|
|
17U, // XVFCMP_CULT_D
|
|
17U, // XVFCMP_CULT_S
|
|
17U, // XVFCMP_CUNE_D
|
|
17U, // XVFCMP_CUNE_S
|
|
17U, // XVFCMP_CUN_D
|
|
17U, // XVFCMP_CUN_S
|
|
17U, // XVFCMP_SAF_D
|
|
17U, // XVFCMP_SAF_S
|
|
17U, // XVFCMP_SEQ_D
|
|
17U, // XVFCMP_SEQ_S
|
|
17U, // XVFCMP_SLE_D
|
|
17U, // XVFCMP_SLE_S
|
|
17U, // XVFCMP_SLT_D
|
|
17U, // XVFCMP_SLT_S
|
|
17U, // XVFCMP_SNE_D
|
|
17U, // XVFCMP_SNE_S
|
|
17U, // XVFCMP_SOR_D
|
|
17U, // XVFCMP_SOR_S
|
|
17U, // XVFCMP_SUEQ_D
|
|
17U, // XVFCMP_SUEQ_S
|
|
17U, // XVFCMP_SULE_D
|
|
17U, // XVFCMP_SULE_S
|
|
17U, // XVFCMP_SULT_D
|
|
17U, // XVFCMP_SULT_S
|
|
17U, // XVFCMP_SUNE_D
|
|
17U, // XVFCMP_SUNE_S
|
|
17U, // XVFCMP_SUN_D
|
|
17U, // XVFCMP_SUN_S
|
|
1U, // XVFCVTH_D_S
|
|
1U, // XVFCVTH_S_H
|
|
1U, // XVFCVTL_D_S
|
|
1U, // XVFCVTL_S_H
|
|
17U, // XVFCVT_H_S
|
|
17U, // XVFCVT_S_D
|
|
17U, // XVFDIV_D
|
|
17U, // XVFDIV_S
|
|
1U, // XVFFINTH_D_W
|
|
1U, // XVFFINTL_D_W
|
|
1U, // XVFFINT_D_L
|
|
1U, // XVFFINT_D_LU
|
|
17U, // XVFFINT_S_L
|
|
1U, // XVFFINT_S_W
|
|
1U, // XVFFINT_S_WU
|
|
1U, // XVFLOGB_D
|
|
1U, // XVFLOGB_S
|
|
145U, // XVFMADD_D
|
|
145U, // XVFMADD_S
|
|
17U, // XVFMAXA_D
|
|
17U, // XVFMAXA_S
|
|
17U, // XVFMAX_D
|
|
17U, // XVFMAX_S
|
|
17U, // XVFMINA_D
|
|
17U, // XVFMINA_S
|
|
17U, // XVFMIN_D
|
|
17U, // XVFMIN_S
|
|
145U, // XVFMSUB_D
|
|
145U, // XVFMSUB_S
|
|
17U, // XVFMUL_D
|
|
17U, // XVFMUL_S
|
|
145U, // XVFNMADD_D
|
|
145U, // XVFNMADD_S
|
|
145U, // XVFNMSUB_D
|
|
145U, // XVFNMSUB_S
|
|
1U, // XVFRECIPE_D
|
|
1U, // XVFRECIPE_S
|
|
1U, // XVFRECIP_D
|
|
1U, // XVFRECIP_S
|
|
1U, // XVFRINTRM_D
|
|
1U, // XVFRINTRM_S
|
|
1U, // XVFRINTRNE_D
|
|
1U, // XVFRINTRNE_S
|
|
1U, // XVFRINTRP_D
|
|
1U, // XVFRINTRP_S
|
|
1U, // XVFRINTRZ_D
|
|
1U, // XVFRINTRZ_S
|
|
1U, // XVFRINT_D
|
|
1U, // XVFRINT_S
|
|
1U, // XVFRSQRTE_D
|
|
1U, // XVFRSQRTE_S
|
|
1U, // XVFRSQRT_D
|
|
1U, // XVFRSQRT_S
|
|
9U, // XVFRSTPI_B
|
|
9U, // XVFRSTPI_H
|
|
9U, // XVFRSTP_B
|
|
9U, // XVFRSTP_H
|
|
1U, // XVFSQRT_D
|
|
1U, // XVFSQRT_S
|
|
17U, // XVFSUB_D
|
|
17U, // XVFSUB_S
|
|
1U, // XVFTINTH_L_S
|
|
1U, // XVFTINTL_L_S
|
|
1U, // XVFTINTRMH_L_S
|
|
1U, // XVFTINTRML_L_S
|
|
1U, // XVFTINTRM_L_D
|
|
17U, // XVFTINTRM_W_D
|
|
1U, // XVFTINTRM_W_S
|
|
1U, // XVFTINTRNEH_L_S
|
|
1U, // XVFTINTRNEL_L_S
|
|
1U, // XVFTINTRNE_L_D
|
|
17U, // XVFTINTRNE_W_D
|
|
1U, // XVFTINTRNE_W_S
|
|
1U, // XVFTINTRPH_L_S
|
|
1U, // XVFTINTRPL_L_S
|
|
1U, // XVFTINTRP_L_D
|
|
17U, // XVFTINTRP_W_D
|
|
1U, // XVFTINTRP_W_S
|
|
1U, // XVFTINTRZH_L_S
|
|
1U, // XVFTINTRZL_L_S
|
|
1U, // XVFTINTRZ_LU_D
|
|
1U, // XVFTINTRZ_L_D
|
|
1U, // XVFTINTRZ_WU_S
|
|
17U, // XVFTINTRZ_W_D
|
|
1U, // XVFTINTRZ_W_S
|
|
1U, // XVFTINT_LU_D
|
|
1U, // XVFTINT_L_D
|
|
1U, // XVFTINT_WU_S
|
|
17U, // XVFTINT_W_D
|
|
1U, // XVFTINT_W_S
|
|
17U, // XVHADDW_DU_WU
|
|
17U, // XVHADDW_D_W
|
|
17U, // XVHADDW_HU_BU
|
|
17U, // XVHADDW_H_B
|
|
17U, // XVHADDW_QU_DU
|
|
17U, // XVHADDW_Q_D
|
|
17U, // XVHADDW_WU_HU
|
|
17U, // XVHADDW_W_H
|
|
17U, // XVHSELI_D
|
|
17U, // XVHSUBW_DU_WU
|
|
17U, // XVHSUBW_D_W
|
|
17U, // XVHSUBW_HU_BU
|
|
17U, // XVHSUBW_H_B
|
|
17U, // XVHSUBW_QU_DU
|
|
17U, // XVHSUBW_Q_D
|
|
17U, // XVHSUBW_WU_HU
|
|
17U, // XVHSUBW_W_H
|
|
17U, // XVILVH_B
|
|
17U, // XVILVH_D
|
|
17U, // XVILVH_H
|
|
17U, // XVILVH_W
|
|
17U, // XVILVL_B
|
|
17U, // XVILVL_D
|
|
17U, // XVILVL_H
|
|
17U, // XVILVL_W
|
|
9U, // XVINSGR2VR_D
|
|
9U, // XVINSGR2VR_W
|
|
9U, // XVINSVE0_D
|
|
9U, // XVINSVE0_W
|
|
17U, // XVLD
|
|
1U, // XVLDI
|
|
17U, // XVLDREPL_B
|
|
17U, // XVLDREPL_D
|
|
17U, // XVLDREPL_H
|
|
17U, // XVLDREPL_W
|
|
17U, // XVLDX
|
|
9U, // XVMADDWEV_D_W
|
|
9U, // XVMADDWEV_D_WU
|
|
9U, // XVMADDWEV_D_WU_W
|
|
9U, // XVMADDWEV_H_B
|
|
9U, // XVMADDWEV_H_BU
|
|
9U, // XVMADDWEV_H_BU_B
|
|
9U, // XVMADDWEV_Q_D
|
|
9U, // XVMADDWEV_Q_DU
|
|
9U, // XVMADDWEV_Q_DU_D
|
|
9U, // XVMADDWEV_W_H
|
|
9U, // XVMADDWEV_W_HU
|
|
9U, // XVMADDWEV_W_HU_H
|
|
9U, // XVMADDWOD_D_W
|
|
9U, // XVMADDWOD_D_WU
|
|
9U, // XVMADDWOD_D_WU_W
|
|
9U, // XVMADDWOD_H_B
|
|
9U, // XVMADDWOD_H_BU
|
|
9U, // XVMADDWOD_H_BU_B
|
|
9U, // XVMADDWOD_Q_D
|
|
9U, // XVMADDWOD_Q_DU
|
|
9U, // XVMADDWOD_Q_DU_D
|
|
9U, // XVMADDWOD_W_H
|
|
9U, // XVMADDWOD_W_HU
|
|
9U, // XVMADDWOD_W_HU_H
|
|
9U, // XVMADD_B
|
|
9U, // XVMADD_D
|
|
9U, // XVMADD_H
|
|
9U, // XVMADD_W
|
|
17U, // XVMAXI_B
|
|
17U, // XVMAXI_BU
|
|
17U, // XVMAXI_D
|
|
17U, // XVMAXI_DU
|
|
17U, // XVMAXI_H
|
|
17U, // XVMAXI_HU
|
|
17U, // XVMAXI_W
|
|
17U, // XVMAXI_WU
|
|
17U, // XVMAX_B
|
|
17U, // XVMAX_BU
|
|
17U, // XVMAX_D
|
|
17U, // XVMAX_DU
|
|
17U, // XVMAX_H
|
|
17U, // XVMAX_HU
|
|
17U, // XVMAX_W
|
|
17U, // XVMAX_WU
|
|
17U, // XVMINI_B
|
|
17U, // XVMINI_BU
|
|
17U, // XVMINI_D
|
|
17U, // XVMINI_DU
|
|
17U, // XVMINI_H
|
|
17U, // XVMINI_HU
|
|
17U, // XVMINI_W
|
|
17U, // XVMINI_WU
|
|
17U, // XVMIN_B
|
|
17U, // XVMIN_BU
|
|
17U, // XVMIN_D
|
|
17U, // XVMIN_DU
|
|
17U, // XVMIN_H
|
|
17U, // XVMIN_HU
|
|
17U, // XVMIN_W
|
|
17U, // XVMIN_WU
|
|
17U, // XVMOD_B
|
|
17U, // XVMOD_BU
|
|
17U, // XVMOD_D
|
|
17U, // XVMOD_DU
|
|
17U, // XVMOD_H
|
|
17U, // XVMOD_HU
|
|
17U, // XVMOD_W
|
|
17U, // XVMOD_WU
|
|
1U, // XVMSKGEZ_B
|
|
1U, // XVMSKLTZ_B
|
|
1U, // XVMSKLTZ_D
|
|
1U, // XVMSKLTZ_H
|
|
1U, // XVMSKLTZ_W
|
|
1U, // XVMSKNZ_B
|
|
9U, // XVMSUB_B
|
|
9U, // XVMSUB_D
|
|
9U, // XVMSUB_H
|
|
9U, // XVMSUB_W
|
|
17U, // XVMUH_B
|
|
17U, // XVMUH_BU
|
|
17U, // XVMUH_D
|
|
17U, // XVMUH_DU
|
|
17U, // XVMUH_H
|
|
17U, // XVMUH_HU
|
|
17U, // XVMUH_W
|
|
17U, // XVMUH_WU
|
|
17U, // XVMULWEV_D_W
|
|
17U, // XVMULWEV_D_WU
|
|
17U, // XVMULWEV_D_WU_W
|
|
17U, // XVMULWEV_H_B
|
|
17U, // XVMULWEV_H_BU
|
|
17U, // XVMULWEV_H_BU_B
|
|
17U, // XVMULWEV_Q_D
|
|
17U, // XVMULWEV_Q_DU
|
|
17U, // XVMULWEV_Q_DU_D
|
|
17U, // XVMULWEV_W_H
|
|
17U, // XVMULWEV_W_HU
|
|
17U, // XVMULWEV_W_HU_H
|
|
17U, // XVMULWOD_D_W
|
|
17U, // XVMULWOD_D_WU
|
|
17U, // XVMULWOD_D_WU_W
|
|
17U, // XVMULWOD_H_B
|
|
17U, // XVMULWOD_H_BU
|
|
17U, // XVMULWOD_H_BU_B
|
|
17U, // XVMULWOD_Q_D
|
|
17U, // XVMULWOD_Q_DU
|
|
17U, // XVMULWOD_Q_DU_D
|
|
17U, // XVMULWOD_W_H
|
|
17U, // XVMULWOD_W_HU
|
|
17U, // XVMULWOD_W_HU_H
|
|
17U, // XVMUL_B
|
|
17U, // XVMUL_D
|
|
17U, // XVMUL_H
|
|
17U, // XVMUL_W
|
|
1U, // XVNEG_B
|
|
1U, // XVNEG_D
|
|
1U, // XVNEG_H
|
|
1U, // XVNEG_W
|
|
17U, // XVNORI_B
|
|
17U, // XVNOR_V
|
|
17U, // XVORI_B
|
|
17U, // XVORN_V
|
|
17U, // XVOR_V
|
|
17U, // XVPACKEV_B
|
|
17U, // XVPACKEV_D
|
|
17U, // XVPACKEV_H
|
|
17U, // XVPACKEV_W
|
|
17U, // XVPACKOD_B
|
|
17U, // XVPACKOD_D
|
|
17U, // XVPACKOD_H
|
|
17U, // XVPACKOD_W
|
|
1U, // XVPCNT_B
|
|
1U, // XVPCNT_D
|
|
1U, // XVPCNT_H
|
|
1U, // XVPCNT_W
|
|
17U, // XVPERMI_D
|
|
9U, // XVPERMI_Q
|
|
9U, // XVPERMI_W
|
|
17U, // XVPERM_W
|
|
17U, // XVPICKEV_B
|
|
17U, // XVPICKEV_D
|
|
17U, // XVPICKEV_H
|
|
17U, // XVPICKEV_W
|
|
17U, // XVPICKOD_B
|
|
17U, // XVPICKOD_D
|
|
17U, // XVPICKOD_H
|
|
17U, // XVPICKOD_W
|
|
17U, // XVPICKVE2GR_D
|
|
17U, // XVPICKVE2GR_DU
|
|
17U, // XVPICKVE2GR_W
|
|
17U, // XVPICKVE2GR_WU
|
|
17U, // XVPICKVE_D
|
|
17U, // XVPICKVE_W
|
|
17U, // XVREPL128VEI_B
|
|
17U, // XVREPL128VEI_D
|
|
17U, // XVREPL128VEI_H
|
|
17U, // XVREPL128VEI_W
|
|
1U, // XVREPLGR2VR_B
|
|
1U, // XVREPLGR2VR_D
|
|
1U, // XVREPLGR2VR_H
|
|
1U, // XVREPLGR2VR_W
|
|
1U, // XVREPLVE0_B
|
|
1U, // XVREPLVE0_D
|
|
1U, // XVREPLVE0_H
|
|
1U, // XVREPLVE0_Q
|
|
1U, // XVREPLVE0_W
|
|
17U, // XVREPLVE_B
|
|
17U, // XVREPLVE_D
|
|
17U, // XVREPLVE_H
|
|
17U, // XVREPLVE_W
|
|
17U, // XVROTRI_B
|
|
17U, // XVROTRI_D
|
|
17U, // XVROTRI_H
|
|
17U, // XVROTRI_W
|
|
17U, // XVROTR_B
|
|
17U, // XVROTR_D
|
|
17U, // XVROTR_H
|
|
17U, // XVROTR_W
|
|
17U, // XVSADD_B
|
|
17U, // XVSADD_BU
|
|
17U, // XVSADD_D
|
|
17U, // XVSADD_DU
|
|
17U, // XVSADD_H
|
|
17U, // XVSADD_HU
|
|
17U, // XVSADD_W
|
|
17U, // XVSADD_WU
|
|
17U, // XVSAT_B
|
|
17U, // XVSAT_BU
|
|
17U, // XVSAT_D
|
|
17U, // XVSAT_DU
|
|
17U, // XVSAT_H
|
|
17U, // XVSAT_HU
|
|
17U, // XVSAT_W
|
|
17U, // XVSAT_WU
|
|
17U, // XVSEQI_B
|
|
17U, // XVSEQI_D
|
|
17U, // XVSEQI_H
|
|
17U, // XVSEQI_W
|
|
17U, // XVSEQ_B
|
|
17U, // XVSEQ_D
|
|
17U, // XVSEQ_H
|
|
17U, // XVSEQ_W
|
|
1U, // XVSETALLNEZ_B
|
|
1U, // XVSETALLNEZ_D
|
|
1U, // XVSETALLNEZ_H
|
|
1U, // XVSETALLNEZ_W
|
|
1U, // XVSETANYEQZ_B
|
|
1U, // XVSETANYEQZ_D
|
|
1U, // XVSETANYEQZ_H
|
|
1U, // XVSETANYEQZ_W
|
|
1U, // XVSETEQZ_V
|
|
1U, // XVSETNEZ_V
|
|
17U, // XVSHUF4I_B
|
|
9U, // XVSHUF4I_D
|
|
17U, // XVSHUF4I_H
|
|
17U, // XVSHUF4I_W
|
|
145U, // XVSHUF_B
|
|
9U, // XVSHUF_D
|
|
9U, // XVSHUF_H
|
|
9U, // XVSHUF_W
|
|
17U, // XVSIGNCOV_B
|
|
17U, // XVSIGNCOV_D
|
|
17U, // XVSIGNCOV_H
|
|
17U, // XVSIGNCOV_W
|
|
17U, // XVSLEI_B
|
|
17U, // XVSLEI_BU
|
|
17U, // XVSLEI_D
|
|
17U, // XVSLEI_DU
|
|
17U, // XVSLEI_H
|
|
17U, // XVSLEI_HU
|
|
17U, // XVSLEI_W
|
|
17U, // XVSLEI_WU
|
|
17U, // XVSLE_B
|
|
17U, // XVSLE_BU
|
|
17U, // XVSLE_D
|
|
17U, // XVSLE_DU
|
|
17U, // XVSLE_H
|
|
17U, // XVSLE_HU
|
|
17U, // XVSLE_W
|
|
17U, // XVSLE_WU
|
|
17U, // XVSLLI_B
|
|
17U, // XVSLLI_D
|
|
17U, // XVSLLI_H
|
|
17U, // XVSLLI_W
|
|
17U, // XVSLLWIL_DU_WU
|
|
17U, // XVSLLWIL_D_W
|
|
17U, // XVSLLWIL_HU_BU
|
|
17U, // XVSLLWIL_H_B
|
|
17U, // XVSLLWIL_WU_HU
|
|
17U, // XVSLLWIL_W_H
|
|
17U, // XVSLL_B
|
|
17U, // XVSLL_D
|
|
17U, // XVSLL_H
|
|
17U, // XVSLL_W
|
|
17U, // XVSLTI_B
|
|
17U, // XVSLTI_BU
|
|
17U, // XVSLTI_D
|
|
17U, // XVSLTI_DU
|
|
17U, // XVSLTI_H
|
|
17U, // XVSLTI_HU
|
|
17U, // XVSLTI_W
|
|
17U, // XVSLTI_WU
|
|
17U, // XVSLT_B
|
|
17U, // XVSLT_BU
|
|
17U, // XVSLT_D
|
|
17U, // XVSLT_DU
|
|
17U, // XVSLT_H
|
|
17U, // XVSLT_HU
|
|
17U, // XVSLT_W
|
|
17U, // XVSLT_WU
|
|
17U, // XVSRAI_B
|
|
17U, // XVSRAI_D
|
|
17U, // XVSRAI_H
|
|
17U, // XVSRAI_W
|
|
9U, // XVSRANI_B_H
|
|
9U, // XVSRANI_D_Q
|
|
9U, // XVSRANI_H_W
|
|
9U, // XVSRANI_W_D
|
|
17U, // XVSRAN_B_H
|
|
17U, // XVSRAN_H_W
|
|
17U, // XVSRAN_W_D
|
|
17U, // XVSRARI_B
|
|
17U, // XVSRARI_D
|
|
17U, // XVSRARI_H
|
|
17U, // XVSRARI_W
|
|
9U, // XVSRARNI_B_H
|
|
9U, // XVSRARNI_D_Q
|
|
9U, // XVSRARNI_H_W
|
|
9U, // XVSRARNI_W_D
|
|
17U, // XVSRARN_B_H
|
|
17U, // XVSRARN_H_W
|
|
17U, // XVSRARN_W_D
|
|
17U, // XVSRAR_B
|
|
17U, // XVSRAR_D
|
|
17U, // XVSRAR_H
|
|
17U, // XVSRAR_W
|
|
17U, // XVSRA_B
|
|
17U, // XVSRA_D
|
|
17U, // XVSRA_H
|
|
17U, // XVSRA_W
|
|
17U, // XVSRLI_B
|
|
17U, // XVSRLI_D
|
|
17U, // XVSRLI_H
|
|
17U, // XVSRLI_W
|
|
9U, // XVSRLNI_B_H
|
|
9U, // XVSRLNI_D_Q
|
|
9U, // XVSRLNI_H_W
|
|
9U, // XVSRLNI_W_D
|
|
17U, // XVSRLN_B_H
|
|
17U, // XVSRLN_H_W
|
|
17U, // XVSRLN_W_D
|
|
17U, // XVSRLRI_B
|
|
17U, // XVSRLRI_D
|
|
17U, // XVSRLRI_H
|
|
17U, // XVSRLRI_W
|
|
9U, // XVSRLRNI_B_H
|
|
9U, // XVSRLRNI_D_Q
|
|
9U, // XVSRLRNI_H_W
|
|
9U, // XVSRLRNI_W_D
|
|
17U, // XVSRLRN_B_H
|
|
17U, // XVSRLRN_H_W
|
|
17U, // XVSRLRN_W_D
|
|
17U, // XVSRLR_B
|
|
17U, // XVSRLR_D
|
|
17U, // XVSRLR_H
|
|
17U, // XVSRLR_W
|
|
17U, // XVSRL_B
|
|
17U, // XVSRL_D
|
|
17U, // XVSRL_H
|
|
17U, // XVSRL_W
|
|
9U, // XVSSRANI_BU_H
|
|
9U, // XVSSRANI_B_H
|
|
9U, // XVSSRANI_DU_Q
|
|
9U, // XVSSRANI_D_Q
|
|
9U, // XVSSRANI_HU_W
|
|
9U, // XVSSRANI_H_W
|
|
9U, // XVSSRANI_WU_D
|
|
9U, // XVSSRANI_W_D
|
|
17U, // XVSSRAN_BU_H
|
|
17U, // XVSSRAN_B_H
|
|
17U, // XVSSRAN_HU_W
|
|
17U, // XVSSRAN_H_W
|
|
17U, // XVSSRAN_WU_D
|
|
17U, // XVSSRAN_W_D
|
|
9U, // XVSSRARNI_BU_H
|
|
9U, // XVSSRARNI_B_H
|
|
9U, // XVSSRARNI_DU_Q
|
|
9U, // XVSSRARNI_D_Q
|
|
9U, // XVSSRARNI_HU_W
|
|
9U, // XVSSRARNI_H_W
|
|
9U, // XVSSRARNI_WU_D
|
|
9U, // XVSSRARNI_W_D
|
|
17U, // XVSSRARN_BU_H
|
|
17U, // XVSSRARN_B_H
|
|
17U, // XVSSRARN_HU_W
|
|
17U, // XVSSRARN_H_W
|
|
17U, // XVSSRARN_WU_D
|
|
17U, // XVSSRARN_W_D
|
|
9U, // XVSSRLNI_BU_H
|
|
9U, // XVSSRLNI_B_H
|
|
9U, // XVSSRLNI_DU_Q
|
|
9U, // XVSSRLNI_D_Q
|
|
9U, // XVSSRLNI_HU_W
|
|
9U, // XVSSRLNI_H_W
|
|
9U, // XVSSRLNI_WU_D
|
|
9U, // XVSSRLNI_W_D
|
|
17U, // XVSSRLN_BU_H
|
|
17U, // XVSSRLN_B_H
|
|
17U, // XVSSRLN_HU_W
|
|
17U, // XVSSRLN_H_W
|
|
17U, // XVSSRLN_WU_D
|
|
17U, // XVSSRLN_W_D
|
|
9U, // XVSSRLRNI_BU_H
|
|
9U, // XVSSRLRNI_B_H
|
|
9U, // XVSSRLRNI_DU_Q
|
|
9U, // XVSSRLRNI_D_Q
|
|
9U, // XVSSRLRNI_HU_W
|
|
9U, // XVSSRLRNI_H_W
|
|
9U, // XVSSRLRNI_WU_D
|
|
9U, // XVSSRLRNI_W_D
|
|
17U, // XVSSRLRN_BU_H
|
|
17U, // XVSSRLRN_B_H
|
|
17U, // XVSSRLRN_HU_W
|
|
17U, // XVSSRLRN_H_W
|
|
17U, // XVSSRLRN_WU_D
|
|
17U, // XVSSRLRN_W_D
|
|
17U, // XVSSUB_B
|
|
17U, // XVSSUB_BU
|
|
17U, // XVSSUB_D
|
|
17U, // XVSSUB_DU
|
|
17U, // XVSSUB_H
|
|
17U, // XVSSUB_HU
|
|
17U, // XVSSUB_W
|
|
17U, // XVSSUB_WU
|
|
17U, // XVST
|
|
145U, // XVSTELM_B
|
|
145U, // XVSTELM_D
|
|
145U, // XVSTELM_H
|
|
145U, // XVSTELM_W
|
|
17U, // XVSTX
|
|
17U, // XVSUBI_BU
|
|
17U, // XVSUBI_DU
|
|
17U, // XVSUBI_HU
|
|
17U, // XVSUBI_WU
|
|
17U, // XVSUBWEV_D_W
|
|
17U, // XVSUBWEV_D_WU
|
|
17U, // XVSUBWEV_H_B
|
|
17U, // XVSUBWEV_H_BU
|
|
17U, // XVSUBWEV_Q_D
|
|
17U, // XVSUBWEV_Q_DU
|
|
17U, // XVSUBWEV_W_H
|
|
17U, // XVSUBWEV_W_HU
|
|
17U, // XVSUBWOD_D_W
|
|
17U, // XVSUBWOD_D_WU
|
|
17U, // XVSUBWOD_H_B
|
|
17U, // XVSUBWOD_H_BU
|
|
17U, // XVSUBWOD_Q_D
|
|
17U, // XVSUBWOD_Q_DU
|
|
17U, // XVSUBWOD_W_H
|
|
17U, // XVSUBWOD_W_HU
|
|
17U, // XVSUB_B
|
|
17U, // XVSUB_D
|
|
17U, // XVSUB_H
|
|
17U, // XVSUB_Q
|
|
17U, // XVSUB_W
|
|
17U, // XVXORI_B
|
|
17U, // XVXOR_V
|
|
};
|
|
|
|
// Emit the opcode for the instruction.
|
|
uint32_t Bits = 0;
|
|
Bits |= OpInfo0[MCInst_getOpcode(MI)] << 0;
|
|
Bits |= OpInfo1[MCInst_getOpcode(MI)] << 16;
|
|
MnemonicBitsInfo MBI = {
|
|
#ifndef CAPSTONE_DIET
|
|
AsmStrs+(Bits & 16383)-1,
|
|
#else
|
|
NULL,
|
|
#endif // CAPSTONE_DIET
|
|
Bits
|
|
};
|
|
return MBI;
|
|
}
|
|
|
|
/// printInstruction - This method is automatically generated by tablegen
|
|
/// from the instruction set description.
|
|
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O) {
|
|
SStream_concat0(O, "");
|
|
MnemonicBitsInfo MnemonicInfo = getMnemonic(MI, O);
|
|
|
|
SStream_concat0(O, MnemonicInfo.first);
|
|
|
|
uint32_t Bits = MnemonicInfo.second;
|
|
CS_ASSERT_RET(Bits != 0 && "Cannot print this instruction.");
|
|
|
|
// Fragment 0 encoded into 2 bits for 4 unique commands.
|
|
switch ((Bits >> 14) & 3) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// DBG_VALUE, DBG_VALUE_LIST, DBG_INSTR_REF, DBG_PHI, DBG_LABEL, BUNDLE, ...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// PseudoCALL36, PseudoLA_ABS, PseudoLA_ABS_LARGE, PseudoLA_GOT, PseudoLA...
|
|
printOperand(MI, 0, O);
|
|
break;
|
|
case 2:
|
|
// BSTRINS_D, BSTRINS_W, CSRWR, CSRXCHG, GCSRWR, GCSRXCHG, LU32I_D, MOVGR...
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 3:
|
|
// INVTLB
|
|
printOperand(MI, 2, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 1, O);
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 0, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 1 encoded into 2 bits for 3 unique commands.
|
|
switch ((Bits >> 16) & 3) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// PseudoCALL36, B, BL, BREAK, CSRWR, DBAR, DBCL, GCSRWR, HVCL, IBAR, IDL...
|
|
return;
|
|
break;
|
|
case 1:
|
|
// PseudoLA_ABS, PseudoLA_ABS_LARGE, PseudoLA_GOT, PseudoLA_GOT_LARGE, Ps...
|
|
SStream_concat0(O, ", ");
|
|
break;
|
|
case 2:
|
|
// SET_CFR_FALSE, SET_CFR_TRUE
|
|
SStream_concat0(O, ", $fa0, $fa0");
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 2 encoded into 2 bits for 3 unique commands.
|
|
switch ((Bits >> 18) & 3) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// PseudoLA_ABS, PseudoLA_GOT, PseudoLA_GOT_LARGE, PseudoLA_PCREL, Pseudo...
|
|
printOperand(MI, 1, O);
|
|
break;
|
|
case 1:
|
|
// PseudoLA_ABS_LARGE
|
|
printOperand(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// BSTRINS_D, BSTRINS_W, CSRXCHG, GCSRXCHG, SC_D, SC_Q, SC_W, VBITSELI_B,...
|
|
printOperand(MI, 3, O);
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 3 encoded into 1 bits for 2 unique commands.
|
|
if ((Bits >> 20) & 1) {
|
|
// PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud...
|
|
SStream_concat0(O, ", ");
|
|
} else {
|
|
// PseudoLA_ABS, PseudoLA_GOT, PseudoLA_PCREL, PseudoLA_TLS_GD, PseudoLA_...
|
|
return;
|
|
}
|
|
|
|
|
|
// Fragment 4 encoded into 2 bits for 3 unique commands.
|
|
switch ((Bits >> 21) & 3) {
|
|
default: CS_ASSERT_RET(0 && "Invalid command number.");
|
|
case 0:
|
|
// PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud...
|
|
printOperand(MI, 2, O);
|
|
break;
|
|
case 1:
|
|
// AMADD_B, AMADD_D, AMADD_H, AMADD_W, AMADD__DB_B, AMADD__DB_D, AMADD__D...
|
|
printAtomicMemOp(MI, 2, O);
|
|
return;
|
|
break;
|
|
case 2:
|
|
// BSTRINS_D, BSTRINS_W
|
|
printOperand(MI, 4, O);
|
|
return;
|
|
break;
|
|
}
|
|
|
|
|
|
// Fragment 5 encoded into 1 bits for 2 unique commands.
|
|
if ((Bits >> 23) & 1) {
|
|
// ALSL_D, ALSL_W, ALSL_WU, BSTRPICK_D, BSTRPICK_W, BYTEPICK_D, BYTEPICK_...
|
|
SStream_concat0(O, ", ");
|
|
printOperand(MI, 3, O);
|
|
return;
|
|
} else {
|
|
// PseudoLA_GOT_LARGE, PseudoLA_PCREL_LARGE, PseudoLA_TLS_GD_LARGE, Pseud...
|
|
return;
|
|
}
|
|
|
|
}
|
|
|
|
|
|
/// getRegisterName - This method is automatically generated by tblgen
|
|
/// from the register set description. This returns the assembler name
|
|
/// for the specified register.
|
|
static const char *
|
|
getRegisterName(unsigned RegNo, unsigned AltIdx) {
|
|
#ifndef CAPSTONE_DIET
|
|
CS_ASSERT_RET_VAL(RegNo && RegNo < 177 && "Invalid register number!", NULL);
|
|
|
|
static const char AsmStrsNoRegAltName[] = {
|
|
/* 0 */ "f10\0"
|
|
/* 4 */ "vr10\0"
|
|
/* 9 */ "xr10\0"
|
|
/* 14 */ "f20\0"
|
|
/* 18 */ "vr20\0"
|
|
/* 23 */ "xr20\0"
|
|
/* 28 */ "f30\0"
|
|
/* 32 */ "vr30\0"
|
|
/* 37 */ "xr30\0"
|
|
/* 42 */ "fcc0\0"
|
|
/* 47 */ "f0\0"
|
|
/* 50 */ "scr0\0"
|
|
/* 55 */ "fcsr0\0"
|
|
/* 61 */ "vr0\0"
|
|
/* 65 */ "xr0\0"
|
|
/* 69 */ "f11\0"
|
|
/* 73 */ "vr11\0"
|
|
/* 78 */ "xr11\0"
|
|
/* 83 */ "f21\0"
|
|
/* 87 */ "vr21\0"
|
|
/* 92 */ "xr21\0"
|
|
/* 97 */ "f31\0"
|
|
/* 101 */ "vr31\0"
|
|
/* 106 */ "xr31\0"
|
|
/* 111 */ "fcc1\0"
|
|
/* 116 */ "f1\0"
|
|
/* 119 */ "scr1\0"
|
|
/* 124 */ "fcsr1\0"
|
|
/* 130 */ "vr1\0"
|
|
/* 134 */ "xr1\0"
|
|
/* 138 */ "f12\0"
|
|
/* 142 */ "vr12\0"
|
|
/* 147 */ "xr12\0"
|
|
/* 152 */ "f22\0"
|
|
/* 156 */ "vr22\0"
|
|
/* 161 */ "xr22\0"
|
|
/* 166 */ "fcc2\0"
|
|
/* 171 */ "f2\0"
|
|
/* 174 */ "scr2\0"
|
|
/* 179 */ "fcsr2\0"
|
|
/* 185 */ "vr2\0"
|
|
/* 189 */ "xr2\0"
|
|
/* 193 */ "f13\0"
|
|
/* 197 */ "vr13\0"
|
|
/* 202 */ "xr13\0"
|
|
/* 207 */ "f23\0"
|
|
/* 211 */ "vr23\0"
|
|
/* 216 */ "xr23\0"
|
|
/* 221 */ "fcc3\0"
|
|
/* 226 */ "f3\0"
|
|
/* 229 */ "scr3\0"
|
|
/* 234 */ "fcsr3\0"
|
|
/* 240 */ "vr3\0"
|
|
/* 244 */ "xr3\0"
|
|
/* 248 */ "f14\0"
|
|
/* 252 */ "vr14\0"
|
|
/* 257 */ "xr14\0"
|
|
/* 262 */ "f24\0"
|
|
/* 266 */ "vr24\0"
|
|
/* 271 */ "xr24\0"
|
|
/* 276 */ "fcc4\0"
|
|
/* 281 */ "f4\0"
|
|
/* 284 */ "vr4\0"
|
|
/* 288 */ "xr4\0"
|
|
/* 292 */ "f15\0"
|
|
/* 296 */ "vr15\0"
|
|
/* 301 */ "xr15\0"
|
|
/* 306 */ "f25\0"
|
|
/* 310 */ "vr25\0"
|
|
/* 315 */ "xr25\0"
|
|
/* 320 */ "fcc5\0"
|
|
/* 325 */ "f5\0"
|
|
/* 328 */ "vr5\0"
|
|
/* 332 */ "xr5\0"
|
|
/* 336 */ "f16\0"
|
|
/* 340 */ "vr16\0"
|
|
/* 345 */ "xr16\0"
|
|
/* 350 */ "f26\0"
|
|
/* 354 */ "vr26\0"
|
|
/* 359 */ "xr26\0"
|
|
/* 364 */ "fcc6\0"
|
|
/* 369 */ "f6\0"
|
|
/* 372 */ "vr6\0"
|
|
/* 376 */ "xr6\0"
|
|
/* 380 */ "f17\0"
|
|
/* 384 */ "vr17\0"
|
|
/* 389 */ "xr17\0"
|
|
/* 394 */ "f27\0"
|
|
/* 398 */ "vr27\0"
|
|
/* 403 */ "xr27\0"
|
|
/* 408 */ "fcc7\0"
|
|
/* 413 */ "f7\0"
|
|
/* 416 */ "vr7\0"
|
|
/* 420 */ "xr7\0"
|
|
/* 424 */ "f18\0"
|
|
/* 428 */ "vr18\0"
|
|
/* 433 */ "xr18\0"
|
|
/* 438 */ "f28\0"
|
|
/* 442 */ "vr28\0"
|
|
/* 447 */ "xr28\0"
|
|
/* 452 */ "f8\0"
|
|
/* 455 */ "vr8\0"
|
|
/* 459 */ "xr8\0"
|
|
/* 463 */ "f19\0"
|
|
/* 467 */ "vr19\0"
|
|
/* 472 */ "xr19\0"
|
|
/* 477 */ "f29\0"
|
|
/* 481 */ "vr29\0"
|
|
/* 486 */ "xr29\0"
|
|
/* 491 */ "f9\0"
|
|
/* 494 */ "vr9\0"
|
|
/* 498 */ "xr9\0"
|
|
};
|
|
static const uint16_t RegAsmOffsetNoRegAltName[] = {
|
|
47, 116, 171, 226, 281, 325, 369, 413, 452, 491, 0, 69, 138, 193,
|
|
248, 292, 336, 380, 424, 463, 14, 83, 152, 207, 262, 306, 350, 394,
|
|
438, 477, 28, 97, 42, 111, 166, 221, 276, 320, 364, 408, 55, 124,
|
|
179, 234, 52, 121, 176, 231, 285, 329, 373, 417, 456, 495, 5, 74,
|
|
143, 198, 253, 297, 341, 385, 429, 468, 19, 88, 157, 212, 267, 311,
|
|
355, 399, 443, 482, 33, 102, 50, 119, 174, 229, 61, 130, 185, 240,
|
|
284, 328, 372, 416, 455, 494, 4, 73, 142, 197, 252, 296, 340, 384,
|
|
428, 467, 18, 87, 156, 211, 266, 310, 354, 398, 442, 481, 32, 101,
|
|
65, 134, 189, 244, 288, 332, 376, 420, 459, 498, 9, 78, 147, 202,
|
|
257, 301, 345, 389, 433, 472, 23, 92, 161, 216, 271, 315, 359, 403,
|
|
447, 486, 37, 106, 47, 116, 171, 226, 281, 325, 369, 413, 452, 491,
|
|
0, 69, 138, 193, 248, 292, 336, 380, 424, 463, 14, 83, 152, 207,
|
|
262, 306, 350, 394, 438, 477, 28, 97,
|
|
};
|
|
|
|
static const char AsmStrsRegAliasName[] = {
|
|
/* 0 */ "ft10\0"
|
|
/* 5 */ "fa0\0"
|
|
/* 9 */ "fs0\0"
|
|
/* 13 */ "ft0\0"
|
|
/* 17 */ "ft11\0"
|
|
/* 22 */ "fa1\0"
|
|
/* 26 */ "fs1\0"
|
|
/* 30 */ "ft1\0"
|
|
/* 34 */ "ft12\0"
|
|
/* 39 */ "fa2\0"
|
|
/* 43 */ "fs2\0"
|
|
/* 47 */ "ft2\0"
|
|
/* 51 */ "ft13\0"
|
|
/* 56 */ "fa3\0"
|
|
/* 60 */ "fs3\0"
|
|
/* 64 */ "ft3\0"
|
|
/* 68 */ "ft14\0"
|
|
/* 73 */ "fa4\0"
|
|
/* 77 */ "fs4\0"
|
|
/* 81 */ "ft4\0"
|
|
/* 85 */ "ft15\0"
|
|
/* 90 */ "fa5\0"
|
|
/* 94 */ "fs5\0"
|
|
/* 98 */ "ft5\0"
|
|
/* 102 */ "fa6\0"
|
|
/* 106 */ "fs6\0"
|
|
/* 110 */ "ft6\0"
|
|
/* 114 */ "fa7\0"
|
|
/* 118 */ "fs7\0"
|
|
/* 122 */ "ft7\0"
|
|
/* 126 */ "s8\0"
|
|
/* 129 */ "ft8\0"
|
|
/* 133 */ "ft9\0"
|
|
/* 137 */ "ra\0"
|
|
/* 140 */ "zero\0"
|
|
/* 145 */ "fp\0"
|
|
/* 148 */ "sp\0"
|
|
/* 151 */ "tp\0"
|
|
};
|
|
static const uint8_t RegAsmOffsetRegAliasName[] = {
|
|
5, 22, 39, 56, 73, 90, 102, 114, 13, 30, 47, 64, 81, 98,
|
|
110, 122, 129, 133, 0, 17, 34, 51, 68, 85, 9, 26, 43, 60,
|
|
77, 94, 106, 118, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 140, 137, 151, 148, 6, 23, 40, 57, 74, 91, 103, 115,
|
|
14, 31, 48, 65, 82, 99, 111, 123, 130, 4, 145, 10, 27, 44,
|
|
61, 78, 95, 107, 119, 126, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
|
|
4, 4, 4, 4, 5, 22, 39, 56, 73, 90, 102, 114, 13, 30,
|
|
47, 64, 81, 98, 110, 122, 129, 133, 0, 17, 34, 51, 68, 85,
|
|
9, 26, 43, 60, 77, 94, 106, 118,
|
|
};
|
|
|
|
switch(AltIdx) {
|
|
default: CS_ASSERT_RET_VAL(0 && "Invalid register alt name index!", NULL);
|
|
case LoongArch_NoRegAltName:
|
|
CS_ASSERT_RET_VAL(*(AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1]) &&
|
|
"Invalid alt name index for register!", NULL);
|
|
return AsmStrsNoRegAltName+RegAsmOffsetNoRegAltName[RegNo-1];
|
|
case LoongArch_RegAliasName:
|
|
if (!*(AsmStrsRegAliasName+RegAsmOffsetRegAliasName[RegNo-1]))
|
|
return getRegisterName(RegNo, LoongArch_NoRegAltName);
|
|
return AsmStrsRegAliasName+RegAsmOffsetRegAliasName[RegNo-1];
|
|
}
|
|
#else
|
|
return NULL;
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
#ifdef PRINT_ALIAS_INSTR
|
|
#undef PRINT_ALIAS_INSTR
|
|
|
|
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS) {
|
|
#ifndef CAPSTONE_DIET
|
|
static const PatternsForOpcode OpToPatterns[] = {
|
|
{LoongArch_PseudoLA_ABS, 0, 1 },
|
|
{LoongArch_PseudoLA_GOT_LARGE, 1, 1 },
|
|
{LoongArch_PseudoLA_PCREL, 2, 1 },
|
|
{LoongArch_PseudoLA_PCREL_LARGE, 3, 2 },
|
|
{LoongArch_ANDI, 5, 1 },
|
|
{LoongArch_JIRL, 6, 2 },
|
|
{LoongArch_OR, 8, 1 },
|
|
{0}, };
|
|
|
|
static const AliasPattern Patterns[] = {
|
|
// LoongArch_PseudoLA_ABS - 0
|
|
{0, 0, 2, 2 },
|
|
// LoongArch_PseudoLA_GOT_LARGE - 1
|
|
{16, 2, 3, 2 },
|
|
// LoongArch_PseudoLA_PCREL - 2
|
|
{0, 4, 2, 1 },
|
|
// LoongArch_PseudoLA_PCREL_LARGE - 3
|
|
{37, 5, 3, 2 },
|
|
{16, 7, 3, 3 },
|
|
// LoongArch_ANDI - 5
|
|
{57, 10, 3, 3 },
|
|
// LoongArch_JIRL - 6
|
|
{61, 13, 3, 3 },
|
|
{65, 16, 3, 3 },
|
|
// LoongArch_OR - 8
|
|
{71, 19, 3, 3 },
|
|
{0}, };
|
|
|
|
static const AliasPatternCond Conds[] = {
|
|
// (PseudoLA_ABS GPR:$dst, bare_symbol:$src) - 0
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_Feature, LoongArch_LaLocalWithAbs},
|
|
// (PseudoLA_GOT_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 2
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
// (PseudoLA_PCREL GPR:$dst, bare_symbol:$src) - 4
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
// (PseudoLA_PCREL_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 5
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
// (PseudoLA_PCREL_LARGE GPR:$dst, GPR:$tmp, bare_symbol:$src) - 7
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_Feature, LoongArch_LaGlobalWithPcrel},
|
|
// (ANDI R0, R0, 0) - 10
|
|
{AliasPatternCond_K_Reg, LoongArch_R0},
|
|
{AliasPatternCond_K_Reg, LoongArch_R0},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (JIRL R0, R1, 0) - 13
|
|
{AliasPatternCond_K_Reg, LoongArch_R0},
|
|
{AliasPatternCond_K_Reg, LoongArch_R1},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (JIRL R0, GPR:$rj, 0) - 16
|
|
{AliasPatternCond_K_Reg, LoongArch_R0},
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_Imm, (uint32_t)0},
|
|
// (OR GPR:$dst, GPR:$src, R0) - 19
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_RegClass, LoongArch_GPRRegClassID},
|
|
{AliasPatternCond_K_Reg, LoongArch_R0},
|
|
{0}, };
|
|
|
|
static const char AsmStrings[] =
|
|
/* 0 */ "la.local $\x01, $\x02\0"
|
|
/* 16 */ "la.global $\x01, $\x02, $\x03\0"
|
|
/* 37 */ "la.local $\x01, $\x02, $\x03\0"
|
|
/* 57 */ "nop\0"
|
|
/* 61 */ "ret\0"
|
|
/* 65 */ "jr $\x02\0"
|
|
/* 71 */ "move $\x01, $\x02\0"
|
|
;
|
|
|
|
#ifndef NDEBUG
|
|
//static struct SortCheck {
|
|
// SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {
|
|
// assert(std::is_sorted(
|
|
// OpToPatterns.begin(), OpToPatterns.end(),
|
|
// [](const PatternsForOpcode &L, const //PatternsForOpcode &R) {
|
|
// return L.Opcode < R.Opcode;
|
|
// }) &&
|
|
// "tablegen failed to sort opcode patterns");
|
|
// }
|
|
//} sortCheckVar(OpToPatterns);
|
|
#endif
|
|
|
|
AliasMatchingData M = {
|
|
OpToPatterns,
|
|
Patterns,
|
|
Conds,
|
|
AsmStrings,
|
|
NULL,
|
|
};
|
|
const char *AsmString = matchAliasPatterns(MI, &M);
|
|
if (!AsmString) return false;
|
|
|
|
unsigned I = 0;
|
|
while (AsmString[I] != ' ' && AsmString[I] != '\t' &&
|
|
AsmString[I] != '$' && AsmString[I] != '\0')
|
|
++I;
|
|
SStream_concat1(OS, '\t');
|
|
char *substr = malloc(I+1);
|
|
memcpy(substr, AsmString, I);
|
|
substr[I] = '\0';
|
|
SStream_concat0(OS, substr);
|
|
free(substr);
|
|
if (AsmString[I] != '\0') {
|
|
if (AsmString[I] == ' ' || AsmString[I] == '\t') {
|
|
SStream_concat1(OS, '\t');
|
|
++I;
|
|
}
|
|
do {
|
|
if (AsmString[I] == '$') {
|
|
++I;
|
|
if (AsmString[I] == (char)0xff) {
|
|
++I;
|
|
int OpIdx = AsmString[I++] - 1;
|
|
int PrintMethodIdx = AsmString[I++] - 1;
|
|
printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, OS);
|
|
} else
|
|
printOperand(MI, ((unsigned)AsmString[I++]) - 1, OS);
|
|
} else {
|
|
SStream_concat1(OS, AsmString[I++]);
|
|
}
|
|
} while (AsmString[I] != '\0');
|
|
}
|
|
|
|
return true;
|
|
#else
|
|
return false;
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
|
|
static void printCustomAliasOperand(
|
|
MCInst *MI, uint64_t Address, unsigned OpIdx,
|
|
unsigned PrintMethodIdx,
|
|
SStream *OS) {
|
|
#ifndef CAPSTONE_DIET
|
|
CS_ASSERT_RET(0 && "Unknown PrintMethod kind");
|
|
#endif // CAPSTONE_DIET
|
|
}
|
|
|
|
#endif // PRINT_ALIAS_INSTR
|