iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
545 lines
13 KiB
C
545 lines
13 KiB
C
/* Capstone Disassembly Engine */
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/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */
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#include "capstone/mos65xx.h"
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#include "MOS65XXDisassembler.h"
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#include "MOS65XXDisassemblerInternals.h"
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typedef struct OpInfo {
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mos65xx_insn ins;
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mos65xx_address_mode am;
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int operand_bytes;
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} OpInfo;
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static const struct OpInfo OpInfoTable[]= {
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#include "m6502.inc"
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#include "m65c02.inc"
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#include "mw65c02.inc"
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#include "m65816.inc"
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};
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#ifndef CAPSTONE_DIET
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static const char* const RegNames[] = {
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"invalid", "A", "X", "Y", "P", "SP", "DP", "B", "K"
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};
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static const char* const GroupNames[] = {
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NULL,
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"jump",
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"call",
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"ret",
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"int",
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"iret",
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"branch_relative"
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};
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typedef struct InstructionInfo {
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const char* name;
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mos65xx_group_type group_type;
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mos65xx_reg write, read;
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bool modifies_status;
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} InstructionInfo;
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static const struct InstructionInfo InstructionInfoTable[]= {
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#include "instruction_info.inc"
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};
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#endif
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#ifndef CAPSTONE_DIET
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static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
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{
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int i;
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cs_detail *detail = MI->flat_insn->detail;
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InstructionInfo insinfo = InstructionInfoTable[opinfo.ins];
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detail->mos65xx.am = opinfo.am;
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detail->mos65xx.modifies_flags = insinfo.modifies_status;
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detail->groups_count = 0;
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detail->regs_read_count = 0;
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detail->regs_write_count = 0;
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detail->mos65xx.op_count = 0;
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if (insinfo.group_type != MOS65XX_GRP_INVALID) {
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detail->groups[detail->groups_count] = insinfo.group_type;
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detail->groups_count++;
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}
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if (opinfo.am == MOS65XX_AM_REL || opinfo.am == MOS65XX_AM_ZP_REL) {
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detail->groups[detail->groups_count] = MOS65XX_GRP_BRANCH_RELATIVE;
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detail->groups_count++;
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}
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if (insinfo.read != MOS65XX_REG_INVALID) {
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detail->regs_read[detail->regs_read_count++] = insinfo.read;
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} else switch(opinfo.am) {
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case MOS65XX_AM_ACC:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC;
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break;
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case MOS65XX_AM_ZP_Y:
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case MOS65XX_AM_ZP_IND_Y:
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case MOS65XX_AM_ABS_Y:
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case MOS65XX_AM_ZP_IND_LONG_Y:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
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break;
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case MOS65XX_AM_ZP_X:
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case MOS65XX_AM_ZP_X_IND:
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case MOS65XX_AM_ABS_X:
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case MOS65XX_AM_ABS_X_IND:
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case MOS65XX_AM_ABS_LONG_X:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X;
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break;
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case MOS65XX_AM_SR:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
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break;
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case MOS65XX_AM_SR_IND_Y:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
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break;
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default:
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break;
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}
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if (insinfo.write != MOS65XX_REG_INVALID) {
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detail->regs_write[detail->regs_write_count++] = insinfo.write;
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} else if (opinfo.am == MOS65XX_AM_ACC) {
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detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC;
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}
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switch(opinfo.ins) {
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case MOS65XX_INS_ADC:
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case MOS65XX_INS_SBC:
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case MOS65XX_INS_ROL:
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case MOS65XX_INS_ROR:
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/* these read carry flag (and decimal for ADC/SBC) */
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P;
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break;
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/* stack operations */
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case MOS65XX_INS_JSL:
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case MOS65XX_INS_JSR:
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case MOS65XX_INS_PEA:
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case MOS65XX_INS_PEI:
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case MOS65XX_INS_PER:
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case MOS65XX_INS_PHA:
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case MOS65XX_INS_PHB:
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case MOS65XX_INS_PHD:
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case MOS65XX_INS_PHK:
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case MOS65XX_INS_PHP:
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case MOS65XX_INS_PHX:
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case MOS65XX_INS_PHY:
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case MOS65XX_INS_PLA:
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case MOS65XX_INS_PLB:
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case MOS65XX_INS_PLD:
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case MOS65XX_INS_PLP:
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case MOS65XX_INS_PLX:
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case MOS65XX_INS_PLY:
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case MOS65XX_INS_RTI:
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case MOS65XX_INS_RTL:
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case MOS65XX_INS_RTS:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
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detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP;
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break;
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default:
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break;
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}
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if (cpu_type == MOS65XX_CPU_TYPE_65816) {
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switch (opinfo.am) {
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case MOS65XX_AM_ZP:
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case MOS65XX_AM_ZP_X:
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case MOS65XX_AM_ZP_Y:
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case MOS65XX_AM_ZP_IND:
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case MOS65XX_AM_ZP_X_IND:
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case MOS65XX_AM_ZP_IND_Y:
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case MOS65XX_AM_ZP_IND_LONG:
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case MOS65XX_AM_ZP_IND_LONG_Y:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_DP;
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break;
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case MOS65XX_AM_BLOCK:
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC;
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X;
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
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detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC;
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detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_X;
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detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_Y;
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detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_B;
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break;
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default:
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break;
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}
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switch (opinfo.am) {
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case MOS65XX_AM_ZP_IND:
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case MOS65XX_AM_ZP_X_IND:
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case MOS65XX_AM_ZP_IND_Y:
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case MOS65XX_AM_ABS:
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case MOS65XX_AM_ABS_X:
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case MOS65XX_AM_ABS_Y:
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case MOS65XX_AM_ABS_X_IND:
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/* these depend on the databank to generate a 24-bit address */
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/* exceptions: PEA, PEI, and JMP (abs) */
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if (opinfo.ins == MOS65XX_INS_PEI || opinfo.ins == MOS65XX_INS_PEA) break;
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detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_B;
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break;
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default:
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break;
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}
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}
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if (insinfo.modifies_status) {
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detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P;
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}
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switch(opinfo.am) {
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case MOS65XX_AM_IMP:
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break;
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case MOS65XX_AM_IMM:
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detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_IMM;
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detail->mos65xx.operands[detail->mos65xx.op_count].imm = MI->Operands[0].ImmVal;
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detail->mos65xx.op_count++;
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break;
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case MOS65XX_AM_ACC:
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detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_REG;
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detail->mos65xx.operands[detail->mos65xx.op_count].reg = MOS65XX_REG_ACC;
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detail->mos65xx.op_count++;
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break;
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case MOS65XX_AM_REL: {
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int value = MI->Operands[0].ImmVal;
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if (MI->op1_size == 1)
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value = 2 + (signed char)value;
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else
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value = 3 + (signed short)value;
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detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
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detail->mos65xx.operands[detail->mos65xx.op_count].mem = (MI->address + value) & 0xffff;
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detail->mos65xx.op_count++;
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break;
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}
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case MOS65XX_AM_ZP_REL: {
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int value = 3 + (signed char)MI->Operands[1].ImmVal;
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/* BBR0, zp, rel and BBS0, zp, rel */
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detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
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detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal;
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detail->mos65xx.operands[detail->mos65xx.op_count+1].type = MOS65XX_OP_MEM;
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detail->mos65xx.operands[detail->mos65xx.op_count+1].mem = (MI->address + value) & 0xffff;
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detail->mos65xx.op_count+=2;
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break;
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}
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default:
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for (i = 0; i < MI->size; ++i) {
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detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
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detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[i].ImmVal;
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detail->mos65xx.op_count++;
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}
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break;
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}
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}
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#endif
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void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
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{
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#ifndef CAPSTONE_DIET
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unsigned int value;
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unsigned opcode = MCInst_getOpcode(MI);
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mos65xx_info *info = (mos65xx_info *)PrinterInfo;
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OpInfo opinfo = OpInfoTable[opcode];
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const char *prefix = info->hex_prefix ? info->hex_prefix : "0x";
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SStream_concat0(O, InstructionInfoTable[opinfo.ins].name);
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switch (opinfo.ins) {
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/* special case - bit included as part of the instruction name */
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case MOS65XX_INS_BBR:
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case MOS65XX_INS_BBS:
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case MOS65XX_INS_RMB:
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case MOS65XX_INS_SMB:
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SStream_concat(O, "%d", (opcode >> 4) & 0x07);
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break;
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default:
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break;
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}
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value = MI->Operands[0].ImmVal;
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switch (opinfo.am) {
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default:
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break;
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case MOS65XX_AM_IMP:
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break;
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case MOS65XX_AM_ACC:
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SStream_concat0(O, " a");
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break;
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case MOS65XX_AM_IMM:
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if (MI->imm_size == 1)
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SStream_concat(O, " #%s%02x", prefix, value);
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else
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SStream_concat(O, " #%s%04x", prefix, value);
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break;
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case MOS65XX_AM_ZP:
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SStream_concat(O, " %s%02x", prefix, value);
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break;
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case MOS65XX_AM_ABS:
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SStream_concat(O, " %s%04x", prefix, value);
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break;
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case MOS65XX_AM_ABS_LONG_X:
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SStream_concat(O, " %s%06x, x", prefix, value);
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break;
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case MOS65XX_AM_INT:
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SStream_concat(O, " %s%02x", prefix, value);
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break;
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case MOS65XX_AM_ABS_X:
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SStream_concat(O, " %s%04x, x", prefix, value);
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break;
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case MOS65XX_AM_ABS_Y:
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SStream_concat(O, " %s%04x, y", prefix, value);
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break;
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case MOS65XX_AM_ABS_LONG:
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SStream_concat(O, " %s%06x", prefix, value);
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break;
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case MOS65XX_AM_ZP_X:
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SStream_concat(O, " %s%02x, x", prefix, value);
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break;
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case MOS65XX_AM_ZP_Y:
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SStream_concat(O, " %s%02x, y", prefix, value);
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break;
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case MOS65XX_AM_REL:
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if (MI->op1_size == 1)
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value = 2 + (signed char)value;
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else
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value = 3 + (signed short)value;
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SStream_concat(O, " %s%04x", prefix,
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(MI->address + value) & 0xffff);
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break;
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case MOS65XX_AM_ABS_IND:
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SStream_concat(O, " (%s%04x)", prefix, value);
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break;
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case MOS65XX_AM_ABS_X_IND:
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SStream_concat(O, " (%s%04x, x)", prefix, value);
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break;
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case MOS65XX_AM_ABS_IND_LONG:
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SStream_concat(O, " [%s%04x]", prefix, value);
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break;
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case MOS65XX_AM_ZP_IND:
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SStream_concat(O, " (%s%02x)", prefix, value);
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break;
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case MOS65XX_AM_ZP_X_IND:
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SStream_concat(O, " (%s%02x, x)", prefix, value);
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break;
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case MOS65XX_AM_ZP_IND_Y:
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SStream_concat(O, " (%s%02x), y", prefix, value);
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break;
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case MOS65XX_AM_ZP_IND_LONG:
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SStream_concat(O, " [%s%02x]", prefix, value);
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break;
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case MOS65XX_AM_ZP_IND_LONG_Y:
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SStream_concat(O, " [%s%02x], y", prefix, value);
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break;
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case MOS65XX_AM_SR:
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SStream_concat(O, " %s%02x, s", prefix, value);
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break;
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case MOS65XX_AM_SR_IND_Y:
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SStream_concat(O, " (%s%02x, s), y", prefix, value);
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break;
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case MOS65XX_AM_BLOCK:
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SStream_concat(O, " %s%02x, %s%02x",
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prefix, MI->Operands[0].ImmVal,
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prefix, MI->Operands[1].ImmVal);
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break;
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case MOS65XX_AM_ZP_REL:
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value = 3 + (signed char)MI->Operands[1].ImmVal;
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/* BBR0, zp, rel and BBS0, zp, rel */
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SStream_concat(O, " %s%02x, %s%04x",
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prefix, MI->Operands[0].ImmVal,
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prefix, (MI->address + value) & 0xffff);
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break;
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}
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#endif
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}
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bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
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MCInst *MI, uint16_t *size, uint64_t address, void *inst_info)
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{
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int i;
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unsigned char opcode;
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unsigned char len;
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unsigned cpu_offset = 0;
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int cpu_type = MOS65XX_CPU_TYPE_6502;
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cs_struct* handle = MI->csh;
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mos65xx_info *info = (mos65xx_info *)handle->printer_info;
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OpInfo opinfo;
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if (code_len == 0) {
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*size = 1;
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return false;
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}
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cpu_type = info->cpu_type;
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cpu_offset = cpu_type * 256;
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opcode = code[0];
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opinfo = OpInfoTable[cpu_offset + opcode];
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if (opinfo.ins == MOS65XX_INS_INVALID) {
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*size = 1;
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return false;
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}
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len = opinfo.operand_bytes + 1;
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if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) {
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switch(opinfo.ins) {
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case MOS65XX_INS_CPX:
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case MOS65XX_INS_CPY:
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case MOS65XX_INS_LDX:
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case MOS65XX_INS_LDY:
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if (info->long_x) ++len;
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break;
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case MOS65XX_INS_ADC:
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case MOS65XX_INS_AND:
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case MOS65XX_INS_BIT:
|
|
case MOS65XX_INS_CMP:
|
|
case MOS65XX_INS_EOR:
|
|
case MOS65XX_INS_LDA:
|
|
case MOS65XX_INS_ORA:
|
|
case MOS65XX_INS_SBC:
|
|
if (info->long_m) ++len;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (code_len < len) {
|
|
*size = 1;
|
|
return false;
|
|
}
|
|
|
|
MI->address = address;
|
|
|
|
MCInst_setOpcode(MI, cpu_offset + opcode);
|
|
MCInst_setOpcodePub(MI, opinfo.ins);
|
|
|
|
*size = len;
|
|
|
|
/* needed to differentiate relative vs relative long */
|
|
MI->op1_size = len - 1;
|
|
if (opinfo.ins == MOS65XX_INS_NOP) {
|
|
for (i = 1; i < len; ++i)
|
|
MCOperand_CreateImm0(MI, code[i]);
|
|
}
|
|
|
|
switch (opinfo.am) {
|
|
case MOS65XX_AM_ZP_REL:
|
|
MCOperand_CreateImm0(MI, code[1]);
|
|
MCOperand_CreateImm0(MI, code[2]);
|
|
break;
|
|
case MOS65XX_AM_BLOCK:
|
|
MCOperand_CreateImm0(MI, code[2]);
|
|
MCOperand_CreateImm0(MI, code[1]);
|
|
break;
|
|
case MOS65XX_AM_IMP:
|
|
case MOS65XX_AM_ACC:
|
|
break;
|
|
|
|
case MOS65XX_AM_IMM:
|
|
MI->has_imm = 1;
|
|
MI->imm_size = len - 1;
|
|
/* 65816 immediate is either 1 or 2 bytes */
|
|
/* drop through */
|
|
default:
|
|
if (len == 2)
|
|
MCOperand_CreateImm0(MI, code[1]);
|
|
else if (len == 3)
|
|
MCOperand_CreateImm0(MI, (code[2]<<8) | code[1]);
|
|
else if (len == 4)
|
|
MCOperand_CreateImm0(MI, (code[3]<<16) | (code[2]<<8) | code[1]);
|
|
break;
|
|
}
|
|
|
|
#ifndef CAPSTONE_DIET
|
|
if (MI->flat_insn->detail) {
|
|
fillDetails(MI, opinfo, cpu_type);
|
|
}
|
|
#endif
|
|
|
|
return true;
|
|
}
|
|
|
|
const char *MOS65XX_insn_name(csh handle, unsigned int id)
|
|
{
|
|
#ifdef CAPSTONE_DIET
|
|
return NULL;
|
|
#else
|
|
if (id >= ARR_SIZE(InstructionInfoTable)) {
|
|
return NULL;
|
|
}
|
|
return InstructionInfoTable[id].name;
|
|
#endif
|
|
}
|
|
|
|
const char* MOS65XX_reg_name(csh handle, unsigned int reg)
|
|
{
|
|
#ifdef CAPSTONE_DIET
|
|
return NULL;
|
|
#else
|
|
if (reg >= ARR_SIZE(RegNames)) {
|
|
return NULL;
|
|
}
|
|
return RegNames[(int)reg];
|
|
#endif
|
|
}
|
|
|
|
void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
|
{
|
|
/* id is cpu_offset + opcode */
|
|
if (id < ARR_SIZE(OpInfoTable)) {
|
|
insn->id = OpInfoTable[id].ins;
|
|
}
|
|
}
|
|
|
|
const char *MOS65XX_group_name(csh handle, unsigned int id)
|
|
{
|
|
#ifdef CAPSTONE_DIET
|
|
return NULL;
|
|
#else
|
|
if (id >= ARR_SIZE(GroupNames)) {
|
|
return NULL;
|
|
}
|
|
return GroupNames[(int)id];
|
|
#endif
|
|
}
|