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00cc9309cb3a9e41afe5def8dcb9bf5b089b9a21
kaizen/external/capstone/arch/Mips/MipsGenCSAliasEnum.inc
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd 
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

120 lines
5.8 KiB
C
Raw Blame History

/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
MIPS_INS_ALIAS_ADDIU_B32, // Real instr.: MIPS_ADDIUGP48_NM
MIPS_INS_ALIAS_BITREVB, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_BITREVH, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_BYTEREVH, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_NOT, // Real instr.: MIPS_NOR_NM
MIPS_INS_ALIAS_RESTORE_JRC, // Real instr.: MIPS_RESTOREJRC16_NM
MIPS_INS_ALIAS_RESTORE, // Real instr.: MIPS_RESTORE_NM
MIPS_INS_ALIAS_SAVE, // Real instr.: MIPS_SAVE16_NM
MIPS_INS_ALIAS_MOVE, // Real instr.: MIPS_OR
MIPS_INS_ALIAS_BAL, // Real instr.: MIPS_BGEZAL
MIPS_INS_ALIAS_JALR_HB, // Real instr.: MIPS_JALR_HB
MIPS_INS_ALIAS_NEG, // Real instr.: MIPS_SUB
MIPS_INS_ALIAS_NEGU, // Real instr.: MIPS_SUBu
MIPS_INS_ALIAS_NOP, // Real instr.: MIPS_SLL
MIPS_INS_ALIAS_BNEZL, // Real instr.: MIPS_BNEL
MIPS_INS_ALIAS_BEQZL, // Real instr.: MIPS_BEQL
MIPS_INS_ALIAS_SYSCALL, // Real instr.: MIPS_SYSCALL
MIPS_INS_ALIAS_BREAK, // Real instr.: MIPS_BREAK
MIPS_INS_ALIAS_EI, // Real instr.: MIPS_EI
MIPS_INS_ALIAS_DI, // Real instr.: MIPS_DI
MIPS_INS_ALIAS_TEQ, // Real instr.: MIPS_TEQ
MIPS_INS_ALIAS_TGE, // Real instr.: MIPS_TGE
MIPS_INS_ALIAS_TGEU, // Real instr.: MIPS_TGEU
MIPS_INS_ALIAS_TLT, // Real instr.: MIPS_TLT
MIPS_INS_ALIAS_TLTU, // Real instr.: MIPS_TLTU
MIPS_INS_ALIAS_TNE, // Real instr.: MIPS_TNE
MIPS_INS_ALIAS_RDHWR, // Real instr.: MIPS_RDHWR
MIPS_INS_ALIAS_SDBBP, // Real instr.: MIPS_SDBBP
MIPS_INS_ALIAS_SYNC, // Real instr.: MIPS_SYNC
MIPS_INS_ALIAS_HYPCALL, // Real instr.: MIPS_HYPCALL
MIPS_INS_ALIAS_NOR, // Real instr.: MIPS_NORImm
MIPS_INS_ALIAS_C_F_S, // Real instr.: MIPS_C_F_S
MIPS_INS_ALIAS_C_UN_S, // Real instr.: MIPS_C_UN_S
MIPS_INS_ALIAS_C_EQ_S, // Real instr.: MIPS_C_EQ_S
MIPS_INS_ALIAS_C_UEQ_S, // Real instr.: MIPS_C_UEQ_S
MIPS_INS_ALIAS_C_OLT_S, // Real instr.: MIPS_C_OLT_S
MIPS_INS_ALIAS_C_ULT_S, // Real instr.: MIPS_C_ULT_S
MIPS_INS_ALIAS_C_OLE_S, // Real instr.: MIPS_C_OLE_S
MIPS_INS_ALIAS_C_ULE_S, // Real instr.: MIPS_C_ULE_S
MIPS_INS_ALIAS_C_SF_S, // Real instr.: MIPS_C_SF_S
MIPS_INS_ALIAS_C_NGLE_S, // Real instr.: MIPS_C_NGLE_S
MIPS_INS_ALIAS_C_SEQ_S, // Real instr.: MIPS_C_SEQ_S
MIPS_INS_ALIAS_C_NGL_S, // Real instr.: MIPS_C_NGL_S
MIPS_INS_ALIAS_C_LT_S, // Real instr.: MIPS_C_LT_S
MIPS_INS_ALIAS_C_NGE_S, // Real instr.: MIPS_C_NGE_S
MIPS_INS_ALIAS_C_LE_S, // Real instr.: MIPS_C_LE_S
MIPS_INS_ALIAS_C_NGT_S, // Real instr.: MIPS_C_NGT_S
MIPS_INS_ALIAS_BC1T, // Real instr.: MIPS_BC1T
MIPS_INS_ALIAS_BC1F, // Real instr.: MIPS_BC1F
MIPS_INS_ALIAS_C_F_D, // Real instr.: MIPS_C_F_D32
MIPS_INS_ALIAS_C_UN_D, // Real instr.: MIPS_C_UN_D32
MIPS_INS_ALIAS_C_EQ_D, // Real instr.: MIPS_C_EQ_D32
MIPS_INS_ALIAS_C_UEQ_D, // Real instr.: MIPS_C_UEQ_D32
MIPS_INS_ALIAS_C_OLT_D, // Real instr.: MIPS_C_OLT_D32
MIPS_INS_ALIAS_C_ULT_D, // Real instr.: MIPS_C_ULT_D32
MIPS_INS_ALIAS_C_OLE_D, // Real instr.: MIPS_C_OLE_D32
MIPS_INS_ALIAS_C_ULE_D, // Real instr.: MIPS_C_ULE_D32
MIPS_INS_ALIAS_C_SF_D, // Real instr.: MIPS_C_SF_D32
MIPS_INS_ALIAS_C_NGLE_D, // Real instr.: MIPS_C_NGLE_D32
MIPS_INS_ALIAS_C_SEQ_D, // Real instr.: MIPS_C_SEQ_D32
MIPS_INS_ALIAS_C_NGL_D, // Real instr.: MIPS_C_NGL_D32
MIPS_INS_ALIAS_C_LT_D, // Real instr.: MIPS_C_LT_D32
MIPS_INS_ALIAS_C_NGE_D, // Real instr.: MIPS_C_NGE_D32
MIPS_INS_ALIAS_C_LE_D, // Real instr.: MIPS_C_LE_D32
MIPS_INS_ALIAS_C_NGT_D, // Real instr.: MIPS_C_NGT_D32
MIPS_INS_ALIAS_BC1TL, // Real instr.: MIPS_BC1TL
MIPS_INS_ALIAS_BC1FL, // Real instr.: MIPS_BC1FL
MIPS_INS_ALIAS_DNEG, // Real instr.: MIPS_DSUB
MIPS_INS_ALIAS_DNEGU, // Real instr.: MIPS_DSUBu
MIPS_INS_ALIAS_SLT, // Real instr.: MIPS_SLTImm64
MIPS_INS_ALIAS_SLTU, // Real instr.: MIPS_SLTUImm64
MIPS_INS_ALIAS_SIGRIE, // Real instr.: MIPS_SIGRIE
MIPS_INS_ALIAS_JR, // Real instr.: MIPS_JALR
MIPS_INS_ALIAS_JRC, // Real instr.: MIPS_JIC
MIPS_INS_ALIAS_JALRC, // Real instr.: MIPS_JIALC
MIPS_INS_ALIAS_DIV, // Real instr.: MIPS_DIV
MIPS_INS_ALIAS_DIVU, // Real instr.: MIPS_DIVU
MIPS_INS_ALIAS_LAPC, // Real instr.: MIPS_ADDIUPC
MIPS_INS_ALIAS_WRDSP, // Real instr.: MIPS_WRDSP
MIPS_INS_ALIAS_WAIT, // Real instr.: MIPS_WAIT_MM
MIPS_INS_ALIAS_SW, // Real instr.: MIPS_SWSP_MM
MIPS_INS_ALIAS_JALRC_HB, // Real instr.: MIPS_JALRC_HB_MMR6
MIPS_INS_ALIAS_ADDIU_B, // Real instr.: MIPS_ADDIUGPB_NM
MIPS_INS_ALIAS_ADDIU_W, // Real instr.: MIPS_ADDIUGPW_NM
MIPS_INS_ALIAS_JRC_HB, // Real instr.: MIPS_JALRCHB_NM
MIPS_INS_ALIAS_BEQC, // Real instr.: MIPS_BEQC16_NM
MIPS_INS_ALIAS_BNEC, // Real instr.: MIPS_BNEC16_NM
MIPS_INS_ALIAS_BEQZC, // Real instr.: MIPS_BEQC_NM
MIPS_INS_ALIAS_BNEZC, // Real instr.: MIPS_BNEC_NM
MIPS_INS_ALIAS_MFC0, // Real instr.: MIPS_MFC0_NM
MIPS_INS_ALIAS_MFHC0, // Real instr.: MIPS_MFHC0_NM
MIPS_INS_ALIAS_MTC0, // Real instr.: MIPS_MTC0_NM
MIPS_INS_ALIAS_MTHC0, // Real instr.: MIPS_MTHC0_NM
MIPS_INS_ALIAS_DMT, // Real instr.: MIPS_DMT
MIPS_INS_ALIAS_EMT, // Real instr.: MIPS_EMT
MIPS_INS_ALIAS_DVPE, // Real instr.: MIPS_DVPE
MIPS_INS_ALIAS_EVPE, // Real instr.: MIPS_EVPE
MIPS_INS_ALIAS_YIELD, // Real instr.: MIPS_YIELD
MIPS_INS_ALIAS_MFTC0, // Real instr.: MIPS_MFTC0
MIPS_INS_ALIAS_MFTLO, // Real instr.: MIPS_MFTLO
MIPS_INS_ALIAS_MFTHI, // Real instr.: MIPS_MFTHI
MIPS_INS_ALIAS_MFTACX, // Real instr.: MIPS_MFTACX
MIPS_INS_ALIAS_MTTC0, // Real instr.: MIPS_MTTC0
MIPS_INS_ALIAS_MTTLO, // Real instr.: MIPS_MTTLO
MIPS_INS_ALIAS_MTTHI, // Real instr.: MIPS_MTTHI
MIPS_INS_ALIAS_MTTACX, // Real instr.: MIPS_MTTACX
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