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00cc9309cb3a9e41afe5def8dcb9bf5b089b9a21
kaizen/external/capstone/arch/PowerPC/PPCGenRegisterInfo.inc
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd 
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

2832 lines
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#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
PPC_NoRegister,
PPC_BP = 1,
PPC_CARRY = 2,
PPC_CTR = 3,
PPC_FP = 4,
PPC_LR = 5,
PPC_RM = 6,
PPC_SPEFSCR = 7,
PPC_VRSAVE = 8,
PPC_XER = 9,
PPC_ZERO = 10,
PPC_ACC0 = 11,
PPC_ACC1 = 12,
PPC_ACC2 = 13,
PPC_ACC3 = 14,
PPC_ACC4 = 15,
PPC_ACC5 = 16,
PPC_ACC6 = 17,
PPC_ACC7 = 18,
PPC_BP8 = 19,
PPC_CR0 = 20,
PPC_CR1 = 21,
PPC_CR2 = 22,
PPC_CR3 = 23,
PPC_CR4 = 24,
PPC_CR5 = 25,
PPC_CR6 = 26,
PPC_CR7 = 27,
PPC_CTR8 = 28,
PPC_DMR0 = 29,
PPC_DMR1 = 30,
PPC_DMR2 = 31,
PPC_DMR3 = 32,
PPC_DMR4 = 33,
PPC_DMR5 = 34,
PPC_DMR6 = 35,
PPC_DMR7 = 36,
PPC_DMRROW0 = 37,
PPC_DMRROW1 = 38,
PPC_DMRROW2 = 39,
PPC_DMRROW3 = 40,
PPC_DMRROW4 = 41,
PPC_DMRROW5 = 42,
PPC_DMRROW6 = 43,
PPC_DMRROW7 = 44,
PPC_DMRROW8 = 45,
PPC_DMRROW9 = 46,
PPC_DMRROW10 = 47,
PPC_DMRROW11 = 48,
PPC_DMRROW12 = 49,
PPC_DMRROW13 = 50,
PPC_DMRROW14 = 51,
PPC_DMRROW15 = 52,
PPC_DMRROW16 = 53,
PPC_DMRROW17 = 54,
PPC_DMRROW18 = 55,
PPC_DMRROW19 = 56,
PPC_DMRROW20 = 57,
PPC_DMRROW21 = 58,
PPC_DMRROW22 = 59,
PPC_DMRROW23 = 60,
PPC_DMRROW24 = 61,
PPC_DMRROW25 = 62,
PPC_DMRROW26 = 63,
PPC_DMRROW27 = 64,
PPC_DMRROW28 = 65,
PPC_DMRROW29 = 66,
PPC_DMRROW30 = 67,
PPC_DMRROW31 = 68,
PPC_DMRROW32 = 69,
PPC_DMRROW33 = 70,
PPC_DMRROW34 = 71,
PPC_DMRROW35 = 72,
PPC_DMRROW36 = 73,
PPC_DMRROW37 = 74,
PPC_DMRROW38 = 75,
PPC_DMRROW39 = 76,
PPC_DMRROW40 = 77,
PPC_DMRROW41 = 78,
PPC_DMRROW42 = 79,
PPC_DMRROW43 = 80,
PPC_DMRROW44 = 81,
PPC_DMRROW45 = 82,
PPC_DMRROW46 = 83,
PPC_DMRROW47 = 84,
PPC_DMRROW48 = 85,
PPC_DMRROW49 = 86,
PPC_DMRROW50 = 87,
PPC_DMRROW51 = 88,
PPC_DMRROW52 = 89,
PPC_DMRROW53 = 90,
PPC_DMRROW54 = 91,
PPC_DMRROW55 = 92,
PPC_DMRROW56 = 93,
PPC_DMRROW57 = 94,
PPC_DMRROW58 = 95,
PPC_DMRROW59 = 96,
PPC_DMRROW60 = 97,
PPC_DMRROW61 = 98,
PPC_DMRROW62 = 99,
PPC_DMRROW63 = 100,
PPC_DMRROWp0 = 101,
PPC_DMRROWp1 = 102,
PPC_DMRROWp2 = 103,
PPC_DMRROWp3 = 104,
PPC_DMRROWp4 = 105,
PPC_DMRROWp5 = 106,
PPC_DMRROWp6 = 107,
PPC_DMRROWp7 = 108,
PPC_DMRROWp8 = 109,
PPC_DMRROWp9 = 110,
PPC_DMRROWp10 = 111,
PPC_DMRROWp11 = 112,
PPC_DMRROWp12 = 113,
PPC_DMRROWp13 = 114,
PPC_DMRROWp14 = 115,
PPC_DMRROWp15 = 116,
PPC_DMRROWp16 = 117,
PPC_DMRROWp17 = 118,
PPC_DMRROWp18 = 119,
PPC_DMRROWp19 = 120,
PPC_DMRROWp20 = 121,
PPC_DMRROWp21 = 122,
PPC_DMRROWp22 = 123,
PPC_DMRROWp23 = 124,
PPC_DMRROWp24 = 125,
PPC_DMRROWp25 = 126,
PPC_DMRROWp26 = 127,
PPC_DMRROWp27 = 128,
PPC_DMRROWp28 = 129,
PPC_DMRROWp29 = 130,
PPC_DMRROWp30 = 131,
PPC_DMRROWp31 = 132,
PPC_DMRp0 = 133,
PPC_DMRp1 = 134,
PPC_DMRp2 = 135,
PPC_DMRp3 = 136,
PPC_F0 = 137,
PPC_F1 = 138,
PPC_F2 = 139,
PPC_F3 = 140,
PPC_F4 = 141,
PPC_F5 = 142,
PPC_F6 = 143,
PPC_F7 = 144,
PPC_F8 = 145,
PPC_F9 = 146,
PPC_F10 = 147,
PPC_F11 = 148,
PPC_F12 = 149,
PPC_F13 = 150,
PPC_F14 = 151,
PPC_F15 = 152,
PPC_F16 = 153,
PPC_F17 = 154,
PPC_F18 = 155,
PPC_F19 = 156,
PPC_F20 = 157,
PPC_F21 = 158,
PPC_F22 = 159,
PPC_F23 = 160,
PPC_F24 = 161,
PPC_F25 = 162,
PPC_F26 = 163,
PPC_F27 = 164,
PPC_F28 = 165,
PPC_F29 = 166,
PPC_F30 = 167,
PPC_F31 = 168,
PPC_FP8 = 169,
PPC_Fpair0 = 170,
PPC_Fpair2 = 171,
PPC_Fpair4 = 172,
PPC_Fpair6 = 173,
PPC_Fpair8 = 174,
PPC_Fpair10 = 175,
PPC_Fpair12 = 176,
PPC_Fpair14 = 177,
PPC_Fpair16 = 178,
PPC_Fpair18 = 179,
PPC_Fpair20 = 180,
PPC_Fpair22 = 181,
PPC_Fpair24 = 182,
PPC_Fpair26 = 183,
PPC_Fpair28 = 184,
PPC_Fpair30 = 185,
PPC_H0 = 186,
PPC_H1 = 187,
PPC_H2 = 188,
PPC_H3 = 189,
PPC_H4 = 190,
PPC_H5 = 191,
PPC_H6 = 192,
PPC_H7 = 193,
PPC_H8 = 194,
PPC_H9 = 195,
PPC_H10 = 196,
PPC_H11 = 197,
PPC_H12 = 198,
PPC_H13 = 199,
PPC_H14 = 200,
PPC_H15 = 201,
PPC_H16 = 202,
PPC_H17 = 203,
PPC_H18 = 204,
PPC_H19 = 205,
PPC_H20 = 206,
PPC_H21 = 207,
PPC_H22 = 208,
PPC_H23 = 209,
PPC_H24 = 210,
PPC_H25 = 211,
PPC_H26 = 212,
PPC_H27 = 213,
PPC_H28 = 214,
PPC_H29 = 215,
PPC_H30 = 216,
PPC_H31 = 217,
PPC_LR8 = 218,
PPC_QF0 = 219,
PPC_QF1 = 220,
PPC_QF2 = 221,
PPC_QF3 = 222,
PPC_QF4 = 223,
PPC_QF5 = 224,
PPC_QF6 = 225,
PPC_QF7 = 226,
PPC_QF8 = 227,
PPC_QF9 = 228,
PPC_QF10 = 229,
PPC_QF11 = 230,
PPC_QF12 = 231,
PPC_QF13 = 232,
PPC_QF14 = 233,
PPC_QF15 = 234,
PPC_QF16 = 235,
PPC_QF17 = 236,
PPC_QF18 = 237,
PPC_QF19 = 238,
PPC_QF20 = 239,
PPC_QF21 = 240,
PPC_QF22 = 241,
PPC_QF23 = 242,
PPC_QF24 = 243,
PPC_QF25 = 244,
PPC_QF26 = 245,
PPC_QF27 = 246,
PPC_QF28 = 247,
PPC_QF29 = 248,
PPC_QF30 = 249,
PPC_QF31 = 250,
PPC_R0 = 251,
PPC_R1 = 252,
PPC_R2 = 253,
PPC_R3 = 254,
PPC_R4 = 255,
PPC_R5 = 256,
PPC_R6 = 257,
PPC_R7 = 258,
PPC_R8 = 259,
PPC_R9 = 260,
PPC_R10 = 261,
PPC_R11 = 262,
PPC_R12 = 263,
PPC_R13 = 264,
PPC_R14 = 265,
PPC_R15 = 266,
PPC_R16 = 267,
PPC_R17 = 268,
PPC_R18 = 269,
PPC_R19 = 270,
PPC_R20 = 271,
PPC_R21 = 272,
PPC_R22 = 273,
PPC_R23 = 274,
PPC_R24 = 275,
PPC_R25 = 276,
PPC_R26 = 277,
PPC_R27 = 278,
PPC_R28 = 279,
PPC_R29 = 280,
PPC_R30 = 281,
PPC_R31 = 282,
PPC_S0 = 283,
PPC_S1 = 284,
PPC_S2 = 285,
PPC_S3 = 286,
PPC_S4 = 287,
PPC_S5 = 288,
PPC_S6 = 289,
PPC_S7 = 290,
PPC_S8 = 291,
PPC_S9 = 292,
PPC_S10 = 293,
PPC_S11 = 294,
PPC_S12 = 295,
PPC_S13 = 296,
PPC_S14 = 297,
PPC_S15 = 298,
PPC_S16 = 299,
PPC_S17 = 300,
PPC_S18 = 301,
PPC_S19 = 302,
PPC_S20 = 303,
PPC_S21 = 304,
PPC_S22 = 305,
PPC_S23 = 306,
PPC_S24 = 307,
PPC_S25 = 308,
PPC_S26 = 309,
PPC_S27 = 310,
PPC_S28 = 311,
PPC_S29 = 312,
PPC_S30 = 313,
PPC_S31 = 314,
PPC_UACC0 = 315,
PPC_UACC1 = 316,
PPC_UACC2 = 317,
PPC_UACC3 = 318,
PPC_UACC4 = 319,
PPC_UACC5 = 320,
PPC_UACC6 = 321,
PPC_UACC7 = 322,
PPC_V0 = 323,
PPC_V1 = 324,
PPC_V2 = 325,
PPC_V3 = 326,
PPC_V4 = 327,
PPC_V5 = 328,
PPC_V6 = 329,
PPC_V7 = 330,
PPC_V8 = 331,
PPC_V9 = 332,
PPC_V10 = 333,
PPC_V11 = 334,
PPC_V12 = 335,
PPC_V13 = 336,
PPC_V14 = 337,
PPC_V15 = 338,
PPC_V16 = 339,
PPC_V17 = 340,
PPC_V18 = 341,
PPC_V19 = 342,
PPC_V20 = 343,
PPC_V21 = 344,
PPC_V22 = 345,
PPC_V23 = 346,
PPC_V24 = 347,
PPC_V25 = 348,
PPC_V26 = 349,
PPC_V27 = 350,
PPC_V28 = 351,
PPC_V29 = 352,
PPC_V30 = 353,
PPC_V31 = 354,
PPC_VF0 = 355,
PPC_VF1 = 356,
PPC_VF2 = 357,
PPC_VF3 = 358,
PPC_VF4 = 359,
PPC_VF5 = 360,
PPC_VF6 = 361,
PPC_VF7 = 362,
PPC_VF8 = 363,
PPC_VF9 = 364,
PPC_VF10 = 365,
PPC_VF11 = 366,
PPC_VF12 = 367,
PPC_VF13 = 368,
PPC_VF14 = 369,
PPC_VF15 = 370,
PPC_VF16 = 371,
PPC_VF17 = 372,
PPC_VF18 = 373,
PPC_VF19 = 374,
PPC_VF20 = 375,
PPC_VF21 = 376,
PPC_VF22 = 377,
PPC_VF23 = 378,
PPC_VF24 = 379,
PPC_VF25 = 380,
PPC_VF26 = 381,
PPC_VF27 = 382,
PPC_VF28 = 383,
PPC_VF29 = 384,
PPC_VF30 = 385,
PPC_VF31 = 386,
PPC_VSL0 = 387,
PPC_VSL1 = 388,
PPC_VSL2 = 389,
PPC_VSL3 = 390,
PPC_VSL4 = 391,
PPC_VSL5 = 392,
PPC_VSL6 = 393,
PPC_VSL7 = 394,
PPC_VSL8 = 395,
PPC_VSL9 = 396,
PPC_VSL10 = 397,
PPC_VSL11 = 398,
PPC_VSL12 = 399,
PPC_VSL13 = 400,
PPC_VSL14 = 401,
PPC_VSL15 = 402,
PPC_VSL16 = 403,
PPC_VSL17 = 404,
PPC_VSL18 = 405,
PPC_VSL19 = 406,
PPC_VSL20 = 407,
PPC_VSL21 = 408,
PPC_VSL22 = 409,
PPC_VSL23 = 410,
PPC_VSL24 = 411,
PPC_VSL25 = 412,
PPC_VSL26 = 413,
PPC_VSL27 = 414,
PPC_VSL28 = 415,
PPC_VSL29 = 416,
PPC_VSL30 = 417,
PPC_VSL31 = 418,
PPC_VSRp0 = 419,
PPC_VSRp1 = 420,
PPC_VSRp2 = 421,
PPC_VSRp3 = 422,
PPC_VSRp4 = 423,
PPC_VSRp5 = 424,
PPC_VSRp6 = 425,
PPC_VSRp7 = 426,
PPC_VSRp8 = 427,
PPC_VSRp9 = 428,
PPC_VSRp10 = 429,
PPC_VSRp11 = 430,
PPC_VSRp12 = 431,
PPC_VSRp13 = 432,
PPC_VSRp14 = 433,
PPC_VSRp15 = 434,
PPC_VSRp16 = 435,
PPC_VSRp17 = 436,
PPC_VSRp18 = 437,
PPC_VSRp19 = 438,
PPC_VSRp20 = 439,
PPC_VSRp21 = 440,
PPC_VSRp22 = 441,
PPC_VSRp23 = 442,
PPC_VSRp24 = 443,
PPC_VSRp25 = 444,
PPC_VSRp26 = 445,
PPC_VSRp27 = 446,
PPC_VSRp28 = 447,
PPC_VSRp29 = 448,
PPC_VSRp30 = 449,
PPC_VSRp31 = 450,
PPC_VSX32 = 451,
PPC_VSX33 = 452,
PPC_VSX34 = 453,
PPC_VSX35 = 454,
PPC_VSX36 = 455,
PPC_VSX37 = 456,
PPC_VSX38 = 457,
PPC_VSX39 = 458,
PPC_VSX40 = 459,
PPC_VSX41 = 460,
PPC_VSX42 = 461,
PPC_VSX43 = 462,
PPC_VSX44 = 463,
PPC_VSX45 = 464,
PPC_VSX46 = 465,
PPC_VSX47 = 466,
PPC_VSX48 = 467,
PPC_VSX49 = 468,
PPC_VSX50 = 469,
PPC_VSX51 = 470,
PPC_VSX52 = 471,
PPC_VSX53 = 472,
PPC_VSX54 = 473,
PPC_VSX55 = 474,
PPC_VSX56 = 475,
PPC_VSX57 = 476,
PPC_VSX58 = 477,
PPC_VSX59 = 478,
PPC_VSX60 = 479,
PPC_VSX61 = 480,
PPC_VSX62 = 481,
PPC_VSX63 = 482,
PPC_WACC0 = 483,
PPC_WACC1 = 484,
PPC_WACC2 = 485,
PPC_WACC3 = 486,
PPC_WACC4 = 487,
PPC_WACC5 = 488,
PPC_WACC6 = 489,
PPC_WACC7 = 490,
PPC_WACC_HI0 = 491,
PPC_WACC_HI1 = 492,
PPC_WACC_HI2 = 493,
PPC_WACC_HI3 = 494,
PPC_WACC_HI4 = 495,
PPC_WACC_HI5 = 496,
PPC_WACC_HI6 = 497,
PPC_WACC_HI7 = 498,
PPC_X0 = 499,
PPC_X1 = 500,
PPC_X2 = 501,
PPC_X3 = 502,
PPC_X4 = 503,
PPC_X5 = 504,
PPC_X6 = 505,
PPC_X7 = 506,
PPC_X8 = 507,
PPC_X9 = 508,
PPC_X10 = 509,
PPC_X11 = 510,
PPC_X12 = 511,
PPC_X13 = 512,
PPC_X14 = 513,
PPC_X15 = 514,
PPC_X16 = 515,
PPC_X17 = 516,
PPC_X18 = 517,
PPC_X19 = 518,
PPC_X20 = 519,
PPC_X21 = 520,
PPC_X22 = 521,
PPC_X23 = 522,
PPC_X24 = 523,
PPC_X25 = 524,
PPC_X26 = 525,
PPC_X27 = 526,
PPC_X28 = 527,
PPC_X29 = 528,
PPC_X30 = 529,
PPC_X31 = 530,
PPC_ZERO8 = 531,
PPC_CR0EQ = 532,
PPC_CR1EQ = 533,
PPC_CR2EQ = 534,
PPC_CR3EQ = 535,
PPC_CR4EQ = 536,
PPC_CR5EQ = 537,
PPC_CR6EQ = 538,
PPC_CR7EQ = 539,
PPC_CR0GT = 540,
PPC_CR1GT = 541,
PPC_CR2GT = 542,
PPC_CR3GT = 543,
PPC_CR4GT = 544,
PPC_CR5GT = 545,
PPC_CR6GT = 546,
PPC_CR7GT = 547,
PPC_CR0LT = 548,
PPC_CR1LT = 549,
PPC_CR2LT = 550,
PPC_CR3LT = 551,
PPC_CR4LT = 552,
PPC_CR5LT = 553,
PPC_CR6LT = 554,
PPC_CR7LT = 555,
PPC_CR0UN = 556,
PPC_CR1UN = 557,
PPC_CR2UN = 558,
PPC_CR3UN = 559,
PPC_CR4UN = 560,
PPC_CR5UN = 561,
PPC_CR6UN = 562,
PPC_CR7UN = 563,
PPC_G8p0 = 564,
PPC_G8p1 = 565,
PPC_G8p2 = 566,
PPC_G8p3 = 567,
PPC_G8p4 = 568,
PPC_G8p5 = 569,
PPC_G8p6 = 570,
PPC_G8p7 = 571,
PPC_G8p8 = 572,
PPC_G8p9 = 573,
PPC_G8p10 = 574,
PPC_G8p11 = 575,
PPC_G8p12 = 576,
PPC_G8p13 = 577,
PPC_G8p14 = 578,
PPC_G8p15 = 579,
NUM_TARGET_REGS // 580
};
// Register classes
enum {
PPC_VSSRCRegClassID = 0,
PPC_GPRCRegClassID = 1,
PPC_GPRC_NOR0RegClassID = 2,
PPC_GPRC_and_GPRC_NOR0RegClassID = 3,
PPC_CRBITRCRegClassID = 4,
PPC_F4RCRegClassID = 5,
PPC_GPRC32RegClassID = 6,
PPC_CRRCRegClassID = 7,
PPC_CARRYRCRegClassID = 8,
PPC_CTRRCRegClassID = 9,
PPC_LRRCRegClassID = 10,
PPC_VRSAVERCRegClassID = 11,
PPC_SPILLTOVSRRCRegClassID = 12,
PPC_VSFRCRegClassID = 13,
PPC_G8RCRegClassID = 14,
PPC_G8RC_NOX0RegClassID = 15,
PPC_SPILLTOVSRRC_and_VSFRCRegClassID = 16,
PPC_G8RC_and_G8RC_NOX0RegClassID = 17,
PPC_F8RCRegClassID = 18,
PPC_SPERCRegClassID = 19,
PPC_VFRCRegClassID = 20,
PPC_SPERC_with_sub_32_in_GPRC_NOR0RegClassID = 21,
PPC_SPILLTOVSRRC_and_VFRCRegClassID = 22,
PPC_SPILLTOVSRRC_and_F4RCRegClassID = 23,
PPC_CTRRC8RegClassID = 24,
PPC_LR8RCRegClassID = 25,
PPC_DMRROWRCRegClassID = 26,
PPC_VSRCRegClassID = 27,
PPC_VSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 28,
PPC_QSRCRegClassID = 29,
PPC_VRRCRegClassID = 30,
PPC_VSLRCRegClassID = 31,
PPC_VRRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 32,
PPC_FpRCRegClassID = 33,
PPC_G8pRCRegClassID = 34,
PPC_G8pRC_with_sub_32_in_GPRC_NOR0RegClassID = 35,
PPC_QSRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 36,
PPC_VSLRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 37,
PPC_FpRC_with_sub_fp0_in_SPILLTOVSRRCRegClassID = 38,
PPC_DMRROWpRCRegClassID = 39,
PPC_VSRpRCRegClassID = 40,
PPC_VSRpRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 41,
PPC_VSRpRC_with_sub_64_in_F4RCRegClassID = 42,
PPC_VSRpRC_with_sub_64_in_VFRCRegClassID = 43,
PPC_VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCRegClassID = 44,
PPC_VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCRegClassID = 45,
PPC_QBRCRegClassID = 46,
PPC_QFRCRegClassID = 47,
PPC_QBRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 48,
PPC_ACCRCRegClassID = 49,
PPC_UACCRCRegClassID = 50,
PPC_WACCRCRegClassID = 51,
PPC_WACC_HIRCRegClassID = 52,
PPC_ACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 53,
PPC_UACCRC_with_sub_64_in_SPILLTOVSRRCRegClassID = 54,
PPC_ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 55,
PPC_UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCRegClassID = 56,
PPC_DMRRCRegClassID = 57,
PPC_DMRpRCRegClassID = 58,
};
// Subregister indices
enum {
PPC_NoSubRegister,
PPC_sub_32, // 1
PPC_sub_32_hi_phony, // 2
PPC_sub_64, // 3
PPC_sub_dmr0, // 4
PPC_sub_dmr1, // 5
PPC_sub_dmrrow0, // 6
PPC_sub_dmrrow1, // 7
PPC_sub_dmrrowp0, // 8
PPC_sub_dmrrowp1, // 9
PPC_sub_eq, // 10
PPC_sub_fp0, // 11
PPC_sub_fp1, // 12
PPC_sub_gp8_x0, // 13
PPC_sub_gp8_x1, // 14
PPC_sub_gt, // 15
PPC_sub_lt, // 16
PPC_sub_pair0, // 17
PPC_sub_pair1, // 18
PPC_sub_un, // 19
PPC_sub_vsx0, // 20
PPC_sub_vsx1, // 21
PPC_sub_wacc_hi, // 22
PPC_sub_wacc_lo, // 23
PPC_sub_vsx1_then_sub_64, // 24
PPC_sub_pair1_then_sub_64, // 25
PPC_sub_pair1_then_sub_vsx0, // 26
PPC_sub_pair1_then_sub_vsx1, // 27
PPC_sub_pair1_then_sub_vsx1_then_sub_64, // 28
PPC_sub_dmrrowp1_then_sub_dmrrow0, // 29
PPC_sub_dmrrowp1_then_sub_dmrrow1, // 30
PPC_sub_wacc_hi_then_sub_dmrrow0, // 31
PPC_sub_wacc_hi_then_sub_dmrrow1, // 32
PPC_sub_wacc_hi_then_sub_dmrrowp0, // 33
PPC_sub_wacc_hi_then_sub_dmrrowp1, // 34
PPC_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 35
PPC_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 36
PPC_sub_dmr1_then_sub_dmrrow0, // 37
PPC_sub_dmr1_then_sub_dmrrow1, // 38
PPC_sub_dmr1_then_sub_dmrrowp0, // 39
PPC_sub_dmr1_then_sub_dmrrowp1, // 40
PPC_sub_dmr1_then_sub_wacc_hi, // 41
PPC_sub_dmr1_then_sub_wacc_lo, // 42
PPC_sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow0, // 43
PPC_sub_dmr1_then_sub_dmrrowp1_then_sub_dmrrow1, // 44
PPC_sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow0, // 45
PPC_sub_dmr1_then_sub_wacc_hi_then_sub_dmrrow1, // 46
PPC_sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp0, // 47
PPC_sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1, // 48
PPC_sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow0, // 49
PPC_sub_dmr1_then_sub_wacc_hi_then_sub_dmrrowp1_then_sub_dmrrow1, // 50
PPC_sub_gp8_x1_then_sub_32, // 51
PPC_NUM_TARGET_SUBREGS
};
#endif // GET_REGINFO_ENUM
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg PPCRegDiffLists[] = {
/* 0 */ -536, 0,
/* 2 */ -528, 0,
/* 4 */ -521, 0,
/* 6 */ -520, 0,
/* 8 */ -512, 0,
/* 10 */ -32, -250, 251, -250, 0,
/* 15 */ 104, -32, -250, 251, -250, 282, -31, -250, 251, -250, 0,
/* 26 */ 408, -32, -250, 251, -250, 282, -31, -250, 251, -250, 0,
/* 37 */ -30, -250, 251, -250, 0,
/* 42 */ 105, -30, -250, 251, -250, 280, -29, -250, 251, -250, 0,
/* 53 */ 409, -30, -250, 251, -250, 280, -29, -250, 251, -250, 0,
/* 64 */ -28, -250, 251, -250, 0,
/* 69 */ 106, -28, -250, 251, -250, 278, -27, -250, 251, -250, 0,
/* 80 */ 410, -28, -250, 251, -250, 278, -27, -250, 251, -250, 0,
/* 91 */ -26, -250, 251, -250, 0,
/* 96 */ 107, -26, -250, 251, -250, 276, -25, -250, 251, -250, 0,
/* 107 */ 411, -26, -250, 251, -250, 276, -25, -250, 251, -250, 0,
/* 118 */ -24, -250, 251, -250, 0,
/* 123 */ 108, -24, -250, 251, -250, 274, -23, -250, 251, -250, 0,
/* 134 */ 412, -24, -250, 251, -250, 274, -23, -250, 251, -250, 0,
/* 145 */ -22, -250, 251, -250, 0,
/* 150 */ 109, -22, -250, 251, -250, 272, -21, -250, 251, -250, 0,
/* 161 */ 413, -22, -250, 251, -250, 272, -21, -250, 251, -250, 0,
/* 172 */ -20, -250, 251, -250, 0,
/* 177 */ 110, -20, -250, 251, -250, 270, -19, -250, 251, -250, 0,
/* 188 */ 414, -20, -250, 251, -250, 270, -19, -250, 251, -250, 0,
/* 199 */ -18, -250, 251, -250, 0,
/* 204 */ 111, -18, -250, 251, -250, 268, -17, -250, 251, -250, 0,
/* 215 */ 415, -18, -250, 251, -250, 268, -17, -250, 251, -250, 0,
/* 226 */ -65, -248, 249, -248, 0,
/* 231 */ -64, -248, 249, -248, 0,
/* 236 */ -63, -248, 249, -248, 0,
/* 241 */ -62, -248, 249, -248, 0,
/* 246 */ -61, -248, 249, -248, 0,
/* 251 */ -60, -248, 249, -248, 0,
/* 256 */ -59, -248, 249, -248, 0,
/* 261 */ -58, -248, 249, -248, 0,
/* 266 */ -57, -248, 249, -248, 0,
/* 271 */ -56, -248, 249, -248, 0,
/* 276 */ -55, -248, 249, -248, 0,
/* 281 */ -54, -248, 249, -248, 0,
/* 286 */ -53, -248, 249, -248, 0,
/* 291 */ -52, -248, 249, -248, 0,
/* 296 */ -51, -248, 249, -248, 0,
/* 301 */ -50, -248, 249, -248, 0,
/* 306 */ -165, 0,
/* 308 */ -82, 0,
/* 310 */ -32, -65, 0,
/* 313 */ -18, 0,
/* 315 */ -64, 1, 0,
/* 318 */ -382, -64, 1, 64, -63, 1, 0,
/* 325 */ -62, 1, 0,
/* 328 */ 454, -382, -64, 1, 64, -63, 1, 451, -388, -62, 1, 62, -61, 1, 0,
/* 343 */ -60, 1, 0,
/* 346 */ -379, -60, 1, 60, -59, 1, 0,
/* 353 */ -58, 1, 0,
/* 356 */ -104, 454, -382, -64, 1, 64, -63, 1, 451, -388, -62, 1, 62, -61, 1, -14, 454, -379, -60, 1, 60, -59, 1, 444, -385, -58, 1, 58, -57, 1, 0,
/* 387 */ -56, 1, 0,
/* 390 */ -376, -56, 1, 56, -55, 1, 0,
/* 397 */ -54, 1, 0,
/* 400 */ 454, -376, -56, 1, 56, -55, 1, 437, -382, -54, 1, 54, -53, 1, 0,
/* 415 */ -52, 1, 0,
/* 418 */ -373, -52, 1, 52, -51, 1, 0,
/* 425 */ -50, 1, 0,
/* 428 */ -103, 454, -376, -56, 1, 56, -55, 1, 437, -382, -54, 1, 54, -53, 1, -28, 454, -373, -52, 1, 52, -51, 1, 430, -379, -50, 1, 50, -49, 1, 0,
/* 459 */ -48, 1, 0,
/* 462 */ -370, -48, 1, 48, -47, 1, 0,
/* 469 */ -46, 1, 0,
/* 472 */ 454, -370, -48, 1, 48, -47, 1, 423, -376, -46, 1, 46, -45, 1, 0,
/* 487 */ -44, 1, 0,
/* 490 */ -367, -44, 1, 44, -43, 1, 0,
/* 497 */ -42, 1, 0,
/* 500 */ -102, 454, -370, -48, 1, 48, -47, 1, 423, -376, -46, 1, 46, -45, 1, -42, 454, -367, -44, 1, 44, -43, 1, 416, -373, -42, 1, 42, -41, 1, 0,
/* 531 */ -40, 1, 0,
/* 534 */ -364, -40, 1, 40, -39, 1, 0,
/* 541 */ -38, 1, 0,
/* 544 */ 454, -364, -40, 1, 40, -39, 1, 409, -370, -38, 1, 38, -37, 1, 0,
/* 559 */ -36, 1, 0,
/* 562 */ -361, -36, 1, 36, -35, 1, 0,
/* 569 */ -34, 1, 0,
/* 572 */ -101, 454, -364, -40, 1, 40, -39, 1, 409, -370, -38, 1, 38, -37, 1, -56, 454, -361, -36, 1, 36, -35, 1, 402, -367, -34, 1, 34, -33, 1, 0,
/* 603 */ -32, 1, 0,
/* 606 */ -31, 1, 0,
/* 609 */ -30, 1, 0,
/* 612 */ -29, 1, 0,
/* 615 */ -28, 1, 0,
/* 618 */ -27, 1, 0,
/* 621 */ -26, 1, 0,
/* 624 */ -25, 1, 0,
/* 627 */ -24, 1, 0,
/* 630 */ -23, 1, 0,
/* 633 */ -22, 1, 0,
/* 636 */ -21, 1, 0,
/* 639 */ -20, 1, 0,
/* 642 */ -19, 1, 0,
/* 645 */ -18, 1, 0,
/* 648 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
/* 664 */ 18, 0,
/* 666 */ 528, -8, -8, 24, 0,
/* 671 */ -112, 32, -31, 32, 0,
/* 676 */ -111, 32, -31, 32, 0,
/* 681 */ -110, 32, -31, 32, 0,
/* 686 */ -109, 32, -31, 32, 0,
/* 691 */ -108, 32, -31, 32, 0,
/* 696 */ -107, 32, -31, 32, 0,
/* 701 */ -106, 32, -31, 32, 0,
/* 706 */ -105, 32, -31, 32, 0,
/* 711 */ -104, 32, -31, 32, 0,
/* 716 */ -103, 32, -31, 32, 0,
/* 721 */ -102, 32, -31, 32, 0,
/* 726 */ -101, 32, -31, 32, 0,
/* 731 */ -100, 32, -31, 32, 0,
/* 736 */ -99, 32, -31, 32, 0,
/* 741 */ -98, 32, -31, 32, 0,
/* 746 */ -97, 32, -31, 32, 0,
/* 751 */ 32, 216, 49, 0,
/* 755 */ 32, 216, 50, 0,
/* 759 */ 32, 216, 51, 0,
/* 763 */ 32, 216, 52, 0,
/* 767 */ 32, 216, 53, 0,
/* 771 */ 32, 216, 54, 0,
/* 775 */ 32, 216, 55, 0,
/* 779 */ 32, 216, 56, 0,
/* 783 */ 32, 216, 57, 0,
/* 787 */ 32, 216, 58, 0,
/* 791 */ 32, 216, 59, 0,
/* 795 */ 32, 216, 60, 0,
/* 799 */ 32, 216, 61, 0,
/* 803 */ 32, 216, 62, 0,
/* 807 */ 32, 216, 63, 0,
/* 811 */ 32, 216, 64, 0,
/* 815 */ 32, 216, 65, 0,
/* 819 */ 250, 16, -416, 167, 65, 72, 0,
/* 826 */ 250, 17, -416, 167, 64, 73, 0,
/* 833 */ 250, 17, -415, 166, 64, 74, 0,
/* 840 */ 250, 18, -415, 166, 63, 75, 0,
/* 847 */ 250, 19, -415, 166, 62, 76, 0,
/* 854 */ 250, 19, -414, 165, 62, 77, 0,
/* 861 */ 250, 20, -414, 165, 61, 78, 0,
/* 868 */ 250, 21, -414, 165, 60, 79, 0,
/* 875 */ 250, 21, -413, 164, 60, 80, 0,
/* 882 */ 250, 22, -413, 164, 59, 81, 0,
/* 889 */ 250, 23, -413, 164, 58, 82, 0,
/* 896 */ 250, 23, -412, 163, 58, 83, 0,
/* 903 */ 250, 24, -412, 163, 57, 84, 0,
/* 910 */ 250, 25, -412, 163, 56, 85, 0,
/* 917 */ 250, 25, -411, 162, 56, 86, 0,
/* 924 */ 250, 26, -411, 162, 55, 87, 0,
/* 931 */ 250, 27, -411, 162, 54, 88, 0,
/* 938 */ 250, 27, -410, 161, 54, 89, 0,
/* 945 */ 250, 28, -410, 161, 53, 90, 0,
/* 952 */ 250, 29, -410, 161, 52, 91, 0,
/* 959 */ 250, 29, -409, 160, 52, 92, 0,
/* 966 */ 250, 30, -409, 160, 51, 93, 0,
/* 973 */ 250, 31, -409, 160, 50, 94, 0,
/* 980 */ 250, 31, -408, 159, 50, 95, 0,
/* 987 */ -32, 96, 0,
/* 990 */ 250, 32, -408, 159, 49, 96, 0,
/* 997 */ -32, 97, 0,
/* 1000 */ -32, 98, 0,
/* 1003 */ -32, 99, 0,
/* 1006 */ 32, 366, -462, 100, 0,
/* 1011 */ 33, 366, -462, 100, 0,
/* 1016 */ 33, 367, -462, 100, 0,
/* 1021 */ 34, 367, -462, 100, 0,
/* 1026 */ 34, 360, -454, 100, 0,
/* 1031 */ 35, 360, -454, 100, 0,
/* 1036 */ 35, 361, -454, 100, 0,
/* 1041 */ 36, 361, -454, 100, 0,
/* 1046 */ -32, 100, 0,
/* 1049 */ 36, 369, -462, 101, 0,
/* 1054 */ 37, 369, -462, 101, 0,
/* 1059 */ 37, 370, -462, 101, 0,
/* 1064 */ 38, 370, -462, 101, 0,
/* 1069 */ 40, 372, -462, 101, 0,
/* 1074 */ 41, 372, -462, 101, 0,
/* 1079 */ 41, 373, -462, 101, 0,
/* 1084 */ 42, 373, -462, 101, 0,
/* 1089 */ 38, 363, -454, 101, 0,
/* 1094 */ 39, 363, -454, 101, 0,
/* 1099 */ 39, 364, -454, 101, 0,
/* 1104 */ 40, 364, -454, 101, 0,
/* 1109 */ 42, 366, -454, 101, 0,
/* 1114 */ 43, 366, -454, 101, 0,
/* 1119 */ 43, 367, -454, 101, 0,
/* 1124 */ 44, 367, -454, 101, 0,
/* 1129 */ -32, 101, 0,
/* 1132 */ 44, 375, -462, 102, 0,
/* 1137 */ 45, 375, -462, 102, 0,
/* 1142 */ 45, 376, -462, 102, 0,
/* 1147 */ 46, 376, -462, 102, 0,
/* 1152 */ 48, 378, -462, 102, 0,
/* 1157 */ 49, 378, -462, 102, 0,
/* 1162 */ 49, 379, -462, 102, 0,
/* 1167 */ 50, 379, -462, 102, 0,
/* 1172 */ 46, 369, -454, 102, 0,
/* 1177 */ 47, 369, -454, 102, 0,
/* 1182 */ 47, 370, -454, 102, 0,
/* 1187 */ 48, 370, -454, 102, 0,
/* 1192 */ 50, 372, -454, 102, 0,
/* 1197 */ 51, 372, -454, 102, 0,
/* 1202 */ 51, 373, -454, 102, 0,
/* 1207 */ 52, 373, -454, 102, 0,
/* 1212 */ -32, 102, 0,
/* 1215 */ 52, 381, -462, 103, 0,
/* 1220 */ 53, 381, -462, 103, 0,
/* 1225 */ 53, 382, -462, 103, 0,
/* 1230 */ 54, 382, -462, 103, 0,
/* 1235 */ 56, 384, -462, 103, 0,
/* 1240 */ 57, 384, -462, 103, 0,
/* 1245 */ 57, 385, -462, 103, 0,
/* 1250 */ 58, 385, -462, 103, 0,
/* 1255 */ 54, 375, -454, 103, 0,
/* 1260 */ 55, 375, -454, 103, 0,
/* 1265 */ 55, 376, -454, 103, 0,
/* 1270 */ 56, 376, -454, 103, 0,
/* 1275 */ 58, 378, -454, 103, 0,
/* 1280 */ 59, 378, -454, 103, 0,
/* 1285 */ 59, 379, -454, 103, 0,
/* 1290 */ 60, 379, -454, 103, 0,
/* 1295 */ -32, 103, 0,
/* 1298 */ 60, 387, -462, 104, 0,
/* 1303 */ 61, 387, -462, 104, 0,
/* 1308 */ 61, 388, -462, 104, 0,
/* 1313 */ 62, 388, -462, 104, 0,
/* 1318 */ 62, 381, -454, 104, 0,
/* 1323 */ 63, 381, -454, 104, 0,
/* 1328 */ 63, 382, -454, 104, 0,
/* 1333 */ 64, 382, -454, 104, 0,
/* 1338 */ -32, 104, 0,
/* 1341 */ -32, 105, 0,
/* 1344 */ -32, 106, 0,
/* 1347 */ -32, 107, 0,
/* 1350 */ -32, 108, 0,
/* 1353 */ -32, 109, 0,
/* 1356 */ -32, 110, 0,
/* 1359 */ -32, 111, 0,
/* 1362 */ -32, 112, 0,
/* 1365 */ 165, 0,
/* 1367 */ 16, -416, 304, 0,
/* 1371 */ 17, -416, 304, 0,
/* 1375 */ 17, -415, 304, 0,
/* 1379 */ 18, -415, 304, 0,
/* 1383 */ 19, -415, 304, 0,
/* 1387 */ 19, -414, 304, 0,
/* 1391 */ 20, -414, 304, 0,
/* 1395 */ 21, -414, 304, 0,
/* 1399 */ 21, -413, 304, 0,
/* 1403 */ 22, -413, 304, 0,
/* 1407 */ 23, -413, 304, 0,
/* 1411 */ 23, -412, 304, 0,
/* 1415 */ 24, -412, 304, 0,
/* 1419 */ 25, -412, 304, 0,
/* 1423 */ 25, -411, 304, 0,
/* 1427 */ 26, -411, 304, 0,
/* 1431 */ 27, -411, 304, 0,
/* 1435 */ 27, -410, 304, 0,
/* 1439 */ 28, -410, 304, 0,
/* 1443 */ 29, -410, 304, 0,
/* 1447 */ 29, -409, 304, 0,
/* 1451 */ 30, -409, 304, 0,
/* 1455 */ 31, -409, 304, 0,
/* 1459 */ 31, -408, 304, 0,
/* 1463 */ 32, -408, 304, 0,
/* 1467 */ 521, 0,
};
static const uint16_t PPCSubRegIdxLists[] = {
/* 0 */ 1, 0,
/* 2 */ 1, 2, 0,
/* 5 */ 3, 0,
/* 7 */ 6, 7, 0,
/* 10 */ 11, 12, 0,
/* 13 */ 16, 15, 10, 19, 0,
/* 18 */ 20, 3, 21, 24, 0,
/* 23 */ 17, 20, 3, 21, 24, 18, 26, 25, 27, 28, 0,
/* 34 */ 8, 6, 7, 9, 29, 30, 0,
/* 41 */ 23, 8, 6, 7, 9, 29, 30, 22, 33, 31, 32, 34, 35, 36, 0,
/* 56 */ 4, 23, 8, 6, 7, 9, 29, 30, 22, 33, 31, 32, 34, 35, 36, 5, 42, 39, 37, 38, 40, 43, 44, 41, 47, 45, 46, 48, 49, 50, 0,
/* 87 */ 13, 1, 14, 51, 0,
};
static const MCRegisterDesc PPCRegDesc[] = { // Descriptors
{ 4, 0, 0, 0, 0, 0 },
{ 2886, 1, 664, 1, 4096, 58 },
{ 3055, 1, 1, 1, 4097, 58 },
{ 2955, 1, 1, 1, 4098, 58 },
{ 2889, 1, 1365, 1, 4099, 58 },
{ 2952, 1, 1, 1, 4100, 58 },
{ 2830, 1, 1, 1, 4101, 58 },
{ 2940, 1, 1, 1, 4102, 58 },
{ 2823, 1, 1, 1, 4103, 58 },
{ 2948, 1, 1, 1, 4097, 58 },
{ 2881, 1, 1467, 1, 4104, 58 },
{ 262, 26, 1, 23, 2703369, 19 },
{ 595, 53, 1, 23, 2703373, 19 },
{ 890, 80, 1, 23, 2703377, 19 },
{ 1176, 107, 1, 23, 2703381, 19 },
{ 1456, 134, 1, 23, 2703385, 19 },
{ 1721, 161, 1, 23, 2703389, 19 },
{ 1989, 188, 1, 23, 2703393, 19 },
{ 2248, 215, 1, 23, 2703397, 19 },
{ 2537, 313, 1, 0, 4096, 1 },
{ 298, 666, 1, 13, 2703401, 11 },
{ 631, 666, 1, 13, 2703405, 11 },
{ 926, 666, 1, 13, 2703409, 11 },
{ 1212, 666, 1, 13, 2703413, 11 },
{ 1492, 666, 1, 13, 2703417, 11 },
{ 1757, 666, 1, 13, 2703421, 11 },
{ 2025, 666, 1, 13, 2703425, 11 },
{ 2284, 666, 1, 13, 2703429, 11 },
{ 2549, 1, 1, 1, 4098, 58 },
{ 302, 328, 1301, 41, 2687049, 29 },
{ 635, 372, 1218, 41, 2687057, 29 },
{ 930, 400, 1218, 41, 2687065, 29 },
{ 1216, 444, 1135, 41, 2687073, 29 },
{ 1496, 472, 1135, 41, 2687081, 29 },
{ 1761, 516, 1052, 41, 2687089, 29 },
{ 2029, 544, 1052, 41, 2687097, 29 },
{ 2288, 588, 1009, 41, 2687105, 29 },
{ 313, 1, 1333, 1, 4169, 58 },
{ 646, 1, 1328, 1, 4170, 58 },
{ 941, 1, 1323, 1, 4171, 58 },
{ 1227, 1, 1318, 1, 4172, 58 },
{ 1507, 1, 1313, 1, 4173, 58 },
{ 1772, 1, 1308, 1, 4174, 58 },
{ 2040, 1, 1303, 1, 4175, 58 },
{ 2299, 1, 1298, 1, 4176, 58 },
{ 2560, 1, 1290, 1, 4177, 58 },
{ 2792, 1, 1285, 1, 4178, 58 },
{ 32, 1, 1280, 1, 4179, 58 },
{ 389, 1, 1275, 1, 4180, 58 },
{ 715, 1, 1250, 1, 4181, 58 },
{ 1017, 1, 1245, 1, 4182, 58 },
{ 1296, 1, 1240, 1, 4183, 58 },
{ 1577, 1, 1235, 1, 4184, 58 },
{ 1835, 1, 1270, 1, 4185, 58 },
{ 2110, 1, 1265, 1, 4186, 58 },
{ 2362, 1, 1260, 1, 4187, 58 },
{ 2630, 1, 1255, 1, 4188, 58 },
{ 108, 1, 1230, 1, 4189, 58 },
{ 457, 1, 1225, 1, 4190, 58 },
{ 791, 1, 1220, 1, 4191, 58 },
{ 1085, 1, 1215, 1, 4192, 58 },
{ 1372, 1, 1207, 1, 4193, 58 },
{ 1645, 1, 1202, 1, 4194, 58 },
{ 1905, 1, 1197, 1, 4195, 58 },
{ 2172, 1, 1192, 1, 4196, 58 },
{ 2432, 1, 1167, 1, 4197, 58 },
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{ 1094, 229, 769, 0, 4288, 1 },
{ 1381, 229, 769, 0, 4289, 1 },
{ 1654, 229, 765, 0, 4290, 1 },
{ 1914, 229, 765, 0, 4291, 1 },
{ 2181, 229, 761, 0, 4292, 1 },
{ 2441, 229, 761, 0, 4293, 1 },
{ 2701, 229, 757, 0, 4294, 1 },
{ 187, 229, 757, 0, 4295, 1 },
{ 528, 229, 753, 0, 4296, 1 },
{ 2531, 4, 1, 0, 4104, 1 },
{ 2892, 1, 8, 1, 4139, 58 },
{ 2898, 1, 8, 1, 4143, 58 },
{ 2904, 1, 8, 1, 4147, 58 },
{ 2910, 1, 8, 1, 4151, 58 },
{ 2916, 1, 8, 1, 4155, 58 },
{ 2922, 1, 8, 1, 4159, 58 },
{ 2928, 1, 8, 1, 4163, 58 },
{ 2934, 1, 8, 1, 4167, 58 },
{ 2959, 1, 6, 1, 4138, 58 },
{ 2965, 1, 6, 1, 4142, 58 },
{ 2971, 1, 6, 1, 4146, 58 },
{ 2977, 1, 6, 1, 4150, 58 },
{ 2983, 1, 6, 1, 4154, 58 },
{ 2989, 1, 6, 1, 4158, 58 },
{ 2995, 1, 6, 1, 4162, 58 },
{ 3001, 1, 6, 1, 4166, 58 },
{ 3007, 1, 2, 1, 4137, 58 },
{ 3013, 1, 2, 1, 4141, 58 },
{ 3019, 1, 2, 1, 4145, 58 },
{ 3025, 1, 2, 1, 4149, 58 },
{ 3031, 1, 2, 1, 4153, 58 },
{ 3037, 1, 2, 1, 4157, 58 },
{ 3043, 1, 2, 1, 4161, 58 },
{ 3049, 1, 2, 1, 4165, 58 },
{ 2833, 1, 0, 1, 4140, 58 },
{ 2839, 1, 0, 1, 4144, 58 },
{ 2845, 1, 0, 1, 4148, 58 },
{ 2851, 1, 0, 1, 4152, 58 },
{ 2857, 1, 0, 1, 4156, 58 },
{ 2863, 1, 0, 1, 4160, 58 },
{ 2869, 1, 0, 1, 4164, 58 },
{ 2875, 1, 0, 1, 4168, 58 },
{ 324, 226, 1, 87, 1294505, 55 },
{ 657, 231, 1, 87, 1294507, 55 },
{ 952, 236, 1, 87, 1294509, 55 },
{ 1238, 241, 1, 87, 1294511, 55 },
{ 1518, 246, 1, 87, 1294513, 55 },
{ 1783, 251, 1, 87, 1294515, 55 },
{ 2051, 256, 1, 87, 1294517, 55 },
{ 2310, 261, 1, 87, 1294519, 55 },
{ 2571, 266, 1, 87, 1294521, 55 },
{ 2803, 271, 1, 87, 1294523, 55 },
{ 45, 276, 1, 87, 1294525, 55 },
{ 402, 281, 1, 87, 1294527, 55 },
{ 728, 286, 1, 87, 1294529, 55 },
{ 1030, 291, 1, 87, 1294531, 55 },
{ 1309, 296, 1, 87, 1294533, 55 },
{ 1590, 301, 1, 87, 1294535, 55 },
};
// VSSRC Register Class...
static const MCPhysReg VSSRC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20,
};
// VSSRC Bit set.
static const uint8_t VSSRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// GPRC Register Class...
static const MCPhysReg GPRC[] = {
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R0, PPC_R1, PPC_FP, PPC_BP,
};
// GPRC Bit set.
static const uint8_t GPRCBits[] = {
0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// GPRC_NOR0 Register Class...
static const MCPhysReg GPRC_NOR0[] = {
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP, PPC_ZERO,
};
// GPRC_NOR0 Bit set.
static const uint8_t GPRC_NOR0Bits[] = {
0x12, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// GPRC_and_GPRC_NOR0 Register Class...
static const MCPhysReg GPRC_and_GPRC_NOR0[] = {
PPC_R2, PPC_R3, PPC_R4, PPC_R5, PPC_R6, PPC_R7, PPC_R8, PPC_R9, PPC_R10, PPC_R11, PPC_R12, PPC_R30, PPC_R29, PPC_R28, PPC_R27, PPC_R26, PPC_R25, PPC_R24, PPC_R23, PPC_R22, PPC_R21, PPC_R20, PPC_R19, PPC_R18, PPC_R17, PPC_R16, PPC_R15, PPC_R14, PPC_R13, PPC_R31, PPC_R1, PPC_FP, PPC_BP,
};
// GPRC_and_GPRC_NOR0 Bit set.
static const uint8_t GPRC_and_GPRC_NOR0Bits[] = {
0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// CRBITRC Register Class...
static const MCPhysReg CRBITRC[] = {
PPC_CR2LT, PPC_CR2GT, PPC_CR2EQ, PPC_CR2UN, PPC_CR3LT, PPC_CR3GT, PPC_CR3EQ, PPC_CR3UN, PPC_CR4LT, PPC_CR4GT, PPC_CR4EQ, PPC_CR4UN, PPC_CR5LT, PPC_CR5GT, PPC_CR5EQ, PPC_CR5UN, PPC_CR6LT, PPC_CR6GT, PPC_CR6EQ, PPC_CR6UN, PPC_CR7LT, PPC_CR7GT, PPC_CR7EQ, PPC_CR7UN, PPC_CR1LT, PPC_CR1GT, PPC_CR1EQ, PPC_CR1UN, PPC_CR0LT, PPC_CR0GT, PPC_CR0EQ, PPC_CR0UN,
};
// CRBITRC Bit set.
static const uint8_t CRBITRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// F4RC Register Class...
static const MCPhysReg F4RC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14,
};
// F4RC Bit set.
static const uint8_t F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
};
// GPRC32 Register Class...
static const MCPhysReg GPRC32[] = {
PPC_H2, PPC_H3, PPC_H4, PPC_H5, PPC_H6, PPC_H7, PPC_H8, PPC_H9, PPC_H10, PPC_H11, PPC_H12, PPC_H30, PPC_H29, PPC_H28, PPC_H27, PPC_H26, PPC_H25, PPC_H24, PPC_H23, PPC_H22, PPC_H21, PPC_H20, PPC_H19, PPC_H18, PPC_H17, PPC_H16, PPC_H15, PPC_H14, PPC_H13, PPC_H31, PPC_H0, PPC_H1,
};
// GPRC32 Bit set.
static const uint8_t GPRC32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0xff, 0xff, 0x03,
};
// CRRC Register Class...
static const MCPhysReg CRRC[] = {
PPC_CR0, PPC_CR1, PPC_CR5, PPC_CR6, PPC_CR7, PPC_CR2, PPC_CR3, PPC_CR4,
};
// CRRC Bit set.
static const uint8_t CRRCBits[] = {
0x00, 0x00, 0xf0, 0x0f,
};
// CARRYRC Register Class...
static const MCPhysReg CARRYRC[] = {
PPC_CARRY, PPC_XER,
};
// CARRYRC Bit set.
static const uint8_t CARRYRCBits[] = {
0x04, 0x02,
};
// CTRRC Register Class...
static const MCPhysReg CTRRC[] = {
PPC_CTR,
};
// CTRRC Bit set.
static const uint8_t CTRRCBits[] = {
0x08,
};
// LRRC Register Class...
static const MCPhysReg LRRC[] = {
PPC_LR,
};
// LRRC Bit set.
static const uint8_t LRRCBits[] = {
0x20,
};
// VRSAVERC Register Class...
static const MCPhysReg VRSAVERC[] = {
PPC_VRSAVE,
};
// VRSAVERC Bit set.
static const uint8_t VRSAVERCBits[] = {
0x00, 0x01,
};
// SPILLTOVSRRC Register Class...
static const MCPhysReg SPILLTOVSRRC[] = {
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8, PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
};
// SPILLTOVSRRC Bit set.
static const uint8_t SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSFRC Register Class...
static const MCPhysReg VSFRC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20,
};
// VSFRC Bit set.
static const uint8_t VSFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// G8RC Register Class...
static const MCPhysReg G8RC[] = {
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X0, PPC_X1, PPC_FP8, PPC_BP8,
};
// G8RC Bit set.
static const uint8_t G8RCBits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// G8RC_NOX0 Register Class...
static const MCPhysReg G8RC_NOX0[] = {
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8, PPC_ZERO8,
};
// G8RC_NOX0 Bit set.
static const uint8_t G8RC_NOX0Bits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
};
// SPILLTOVSRRC_and_VSFRC Register Class...
static const MCPhysReg SPILLTOVSRRC_and_VSFRC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
};
// SPILLTOVSRRC_and_VSFRC Bit set.
static const uint8_t SPILLTOVSRRC_and_VSFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
};
// G8RC_and_G8RC_NOX0 Register Class...
static const MCPhysReg G8RC_and_G8RC_NOX0[] = {
PPC_X2, PPC_X3, PPC_X4, PPC_X5, PPC_X6, PPC_X7, PPC_X8, PPC_X9, PPC_X10, PPC_X11, PPC_X12, PPC_X30, PPC_X29, PPC_X28, PPC_X27, PPC_X26, PPC_X25, PPC_X24, PPC_X23, PPC_X22, PPC_X21, PPC_X20, PPC_X19, PPC_X18, PPC_X17, PPC_X16, PPC_X15, PPC_X14, PPC_X31, PPC_X13, PPC_X1, PPC_FP8, PPC_BP8,
};
// G8RC_and_G8RC_NOX0 Bit set.
static const uint8_t G8RC_and_G8RC_NOX0Bits[] = {
0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// F8RC Register Class...
static const MCPhysReg F8RC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13, PPC_F31, PPC_F30, PPC_F29, PPC_F28, PPC_F27, PPC_F26, PPC_F25, PPC_F24, PPC_F23, PPC_F22, PPC_F21, PPC_F20, PPC_F19, PPC_F18, PPC_F17, PPC_F16, PPC_F15, PPC_F14,
};
// F8RC Bit set.
static const uint8_t F8RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0xff, 0xff, 0x01,
};
// SPERC Register Class...
static const MCPhysReg SPERC[] = {
PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S30, PPC_S29, PPC_S28, PPC_S27, PPC_S26, PPC_S25, PPC_S24, PPC_S23, PPC_S22, PPC_S21, PPC_S20, PPC_S19, PPC_S18, PPC_S17, PPC_S16, PPC_S15, PPC_S14, PPC_S13, PPC_S31, PPC_S0, PPC_S1,
};
// SPERC Bit set.
static const uint8_t SPERCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VFRC Register Class...
static const MCPhysReg VFRC[] = {
PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19, PPC_VF31, PPC_VF30, PPC_VF29, PPC_VF28, PPC_VF27, PPC_VF26, PPC_VF25, PPC_VF24, PPC_VF23, PPC_VF22, PPC_VF21, PPC_VF20,
};
// VFRC Bit set.
static const uint8_t VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// SPERC_with_sub_32_in_GPRC_NOR0 Register Class...
static const MCPhysReg SPERC_with_sub_32_in_GPRC_NOR0[] = {
PPC_S2, PPC_S3, PPC_S4, PPC_S5, PPC_S6, PPC_S7, PPC_S8, PPC_S9, PPC_S10, PPC_S11, PPC_S12, PPC_S30, PPC_S29, PPC_S28, PPC_S27, PPC_S26, PPC_S25, PPC_S24, PPC_S23, PPC_S22, PPC_S21, PPC_S20, PPC_S19, PPC_S18, PPC_S17, PPC_S16, PPC_S15, PPC_S14, PPC_S13, PPC_S31, PPC_S1,
};
// SPERC_with_sub_32_in_GPRC_NOR0 Bit set.
static const uint8_t SPERC_with_sub_32_in_GPRC_NOR0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x07,
};
// SPILLTOVSRRC_and_VFRC Register Class...
static const MCPhysReg SPILLTOVSRRC_and_VFRC[] = {
PPC_VF2, PPC_VF3, PPC_VF4, PPC_VF5, PPC_VF0, PPC_VF1, PPC_VF6, PPC_VF7, PPC_VF8, PPC_VF9, PPC_VF10, PPC_VF11, PPC_VF12, PPC_VF13, PPC_VF14, PPC_VF15, PPC_VF16, PPC_VF17, PPC_VF18, PPC_VF19,
};
// SPILLTOVSRRC_and_VFRC Bit set.
static const uint8_t SPILLTOVSRRC_and_VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
};
// SPILLTOVSRRC_and_F4RC Register Class...
static const MCPhysReg SPILLTOVSRRC_and_F4RC[] = {
PPC_F0, PPC_F1, PPC_F2, PPC_F3, PPC_F4, PPC_F5, PPC_F6, PPC_F7, PPC_F8, PPC_F9, PPC_F10, PPC_F11, PPC_F12, PPC_F13,
};
// SPILLTOVSRRC_and_F4RC Bit set.
static const uint8_t SPILLTOVSRRC_and_F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x7f,
};
// CTRRC8 Register Class...
static const MCPhysReg CTRRC8[] = {
PPC_CTR8,
};
// CTRRC8 Bit set.
static const uint8_t CTRRC8Bits[] = {
0x00, 0x00, 0x00, 0x10,
};
// LR8RC Register Class...
static const MCPhysReg LR8RC[] = {
PPC_LR8,
};
// LR8RC Bit set.
static const uint8_t LR8RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04,
};
// DMRROWRC Register Class...
static const MCPhysReg DMRROWRC[] = {
PPC_DMRROW0, PPC_DMRROW1, PPC_DMRROW2, PPC_DMRROW3, PPC_DMRROW4, PPC_DMRROW5, PPC_DMRROW6, PPC_DMRROW7, PPC_DMRROW8, PPC_DMRROW9, PPC_DMRROW10, PPC_DMRROW11, PPC_DMRROW12, PPC_DMRROW13, PPC_DMRROW14, PPC_DMRROW15, PPC_DMRROW16, PPC_DMRROW17, PPC_DMRROW18, PPC_DMRROW19, PPC_DMRROW20, PPC_DMRROW21, PPC_DMRROW22, PPC_DMRROW23, PPC_DMRROW24, PPC_DMRROW25, PPC_DMRROW26, PPC_DMRROW27, PPC_DMRROW28, PPC_DMRROW29, PPC_DMRROW30, PPC_DMRROW31, PPC_DMRROW32, PPC_DMRROW33, PPC_DMRROW34, PPC_DMRROW35, PPC_DMRROW36, PPC_DMRROW37, PPC_DMRROW38, PPC_DMRROW39, PPC_DMRROW40, PPC_DMRROW41, PPC_DMRROW42, PPC_DMRROW43, PPC_DMRROW44, PPC_DMRROW45, PPC_DMRROW46, PPC_DMRROW47, PPC_DMRROW48, PPC_DMRROW49, PPC_DMRROW50, PPC_DMRROW51, PPC_DMRROW52, PPC_DMRROW53, PPC_DMRROW54, PPC_DMRROW55, PPC_DMRROW56, PPC_DMRROW57, PPC_DMRROW58, PPC_DMRROW59, PPC_DMRROW60, PPC_DMRROW61, PPC_DMRROW62, PPC_DMRROW63,
};
// DMRROWRC Bit set.
static const uint8_t DMRROWRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x1f,
};
// VSRC Register Class...
static const MCPhysReg VSRC[] = {
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20,
};
// VSRC Bit set.
static const uint8_t VSRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg VSRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19,
};
// VSRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t VSRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
// QSRC Register Class...
static const MCPhysReg QSRC[] = {
PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14,
};
// QSRC Bit set.
static const uint8_t QSRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VRRC Register Class...
static const MCPhysReg VRRC[] = {
PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19, PPC_V31, PPC_V30, PPC_V29, PPC_V28, PPC_V27, PPC_V26, PPC_V25, PPC_V24, PPC_V23, PPC_V22, PPC_V21, PPC_V20,
};
// VRRC Bit set.
static const uint8_t VRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSLRC Register Class...
static const MCPhysReg VSLRC[] = {
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13, PPC_VSL31, PPC_VSL30, PPC_VSL29, PPC_VSL28, PPC_VSL27, PPC_VSL26, PPC_VSL25, PPC_VSL24, PPC_VSL23, PPC_VSL22, PPC_VSL21, PPC_VSL20, PPC_VSL19, PPC_VSL18, PPC_VSL17, PPC_VSL16, PPC_VSL15, PPC_VSL14,
};
// VSLRC Bit set.
static const uint8_t VSLRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VRRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg VRRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_V2, PPC_V3, PPC_V4, PPC_V5, PPC_V0, PPC_V1, PPC_V6, PPC_V7, PPC_V8, PPC_V9, PPC_V10, PPC_V11, PPC_V12, PPC_V13, PPC_V14, PPC_V15, PPC_V16, PPC_V17, PPC_V18, PPC_V19,
};
// VRRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t VRRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x7f,
};
// FpRC Register Class...
static const MCPhysReg FpRC[] = {
PPC_Fpair0, PPC_Fpair2, PPC_Fpair4, PPC_Fpair6, PPC_Fpair8, PPC_Fpair10, PPC_Fpair12, PPC_Fpair14, PPC_Fpair16, PPC_Fpair18, PPC_Fpair20, PPC_Fpair22, PPC_Fpair24, PPC_Fpair26, PPC_Fpair28, PPC_Fpair30,
};
// FpRC Bit set.
static const uint8_t FpRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x03,
};
// G8pRC Register Class...
static const MCPhysReg G8pRC[] = {
PPC_G8p1, PPC_G8p2, PPC_G8p3, PPC_G8p4, PPC_G8p5, PPC_G8p14, PPC_G8p13, PPC_G8p12, PPC_G8p11, PPC_G8p10, PPC_G8p9, PPC_G8p8, PPC_G8p7, PPC_G8p15, PPC_G8p6, PPC_G8p0,
};
// G8pRC Bit set.
static const uint8_t G8pRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x0f,
};
// G8pRC_with_sub_32_in_GPRC_NOR0 Register Class...
static const MCPhysReg G8pRC_with_sub_32_in_GPRC_NOR0[] = {
PPC_G8p1, PPC_G8p2, PPC_G8p3, PPC_G8p4, PPC_G8p5, PPC_G8p14, PPC_G8p13, PPC_G8p12, PPC_G8p11, PPC_G8p10, PPC_G8p9, PPC_G8p8, PPC_G8p7, PPC_G8p15, PPC_G8p6,
};
// G8pRC_with_sub_32_in_GPRC_NOR0 Bit set.
static const uint8_t G8pRC_with_sub_32_in_GPRC_NOR0Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x0f,
};
// QSRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg QSRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13,
};
// QSRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t QSRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
// VSLRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg VSLRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_VSL0, PPC_VSL1, PPC_VSL2, PPC_VSL3, PPC_VSL4, PPC_VSL5, PPC_VSL6, PPC_VSL7, PPC_VSL8, PPC_VSL9, PPC_VSL10, PPC_VSL11, PPC_VSL12, PPC_VSL13,
};
// VSLRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t VSLRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
// FpRC_with_sub_fp0_in_SPILLTOVSRRC Register Class...
static const MCPhysReg FpRC_with_sub_fp0_in_SPILLTOVSRRC[] = {
PPC_Fpair0, PPC_Fpair2, PPC_Fpair4, PPC_Fpair6, PPC_Fpair8, PPC_Fpair10, PPC_Fpair12,
};
// FpRC_with_sub_fp0_in_SPILLTOVSRRC Bit set.
static const uint8_t FpRC_with_sub_fp0_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
};
// DMRROWpRC Register Class...
static const MCPhysReg DMRROWpRC[] = {
PPC_DMRROWp0, PPC_DMRROWp1, PPC_DMRROWp2, PPC_DMRROWp3, PPC_DMRROWp4, PPC_DMRROWp5, PPC_DMRROWp6, PPC_DMRROWp7, PPC_DMRROWp8, PPC_DMRROWp9, PPC_DMRROWp10, PPC_DMRROWp11, PPC_DMRROWp12, PPC_DMRROWp13, PPC_DMRROWp14, PPC_DMRROWp15, PPC_DMRROWp16, PPC_DMRROWp17, PPC_DMRROWp18, PPC_DMRROWp19, PPC_DMRROWp20, PPC_DMRROWp21, PPC_DMRROWp22, PPC_DMRROWp23, PPC_DMRROWp24, PPC_DMRROWp25, PPC_DMRROWp26, PPC_DMRROWp27, PPC_DMRROWp28, PPC_DMRROWp29, PPC_DMRROWp30, PPC_DMRROWp31,
};
// DMRROWpRC Bit set.
static const uint8_t DMRROWpRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x1f,
};
// VSRpRC Register Class...
static const MCPhysReg VSRpRC[] = {
PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25, PPC_VSRp31, PPC_VSRp30, PPC_VSRp29, PPC_VSRp28, PPC_VSRp27, PPC_VSRp26, PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6, PPC_VSRp15, PPC_VSRp14, PPC_VSRp13, PPC_VSRp12, PPC_VSRp11, PPC_VSRp10, PPC_VSRp9, PPC_VSRp8, PPC_VSRp7,
};
// VSRpRC Bit set.
static const uint8_t VSRpRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25, PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03, 0xf8, 0x1f,
};
// VSRpRC_with_sub_64_in_F4RC Register Class...
static const MCPhysReg VSRpRC_with_sub_64_in_F4RC[] = {
PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6, PPC_VSRp15, PPC_VSRp14, PPC_VSRp13, PPC_VSRp12, PPC_VSRp11, PPC_VSRp10, PPC_VSRp9, PPC_VSRp8, PPC_VSRp7,
};
// VSRpRC_with_sub_64_in_F4RC Bit set.
static const uint8_t VSRpRC_with_sub_64_in_F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
};
// VSRpRC_with_sub_64_in_VFRC Register Class...
static const MCPhysReg VSRpRC_with_sub_64_in_VFRC[] = {
PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25, PPC_VSRp31, PPC_VSRp30, PPC_VSRp29, PPC_VSRp28, PPC_VSRp27, PPC_VSRp26,
};
// VSRpRC_with_sub_64_in_VFRC Bit set.
static const uint8_t VSRpRC_with_sub_64_in_VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Register Class...
static const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC[] = {
PPC_VSRp17, PPC_VSRp18, PPC_VSRp16, PPC_VSRp19, PPC_VSRp20, PPC_VSRp21, PPC_VSRp22, PPC_VSRp23, PPC_VSRp24, PPC_VSRp25,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC Bit set.
static const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x1f,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Register Class...
static const MCPhysReg VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC[] = {
PPC_VSRp0, PPC_VSRp1, PPC_VSRp2, PPC_VSRp3, PPC_VSRp4, PPC_VSRp5, PPC_VSRp6,
};
// VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC Bit set.
static const uint8_t VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
};
// QBRC Register Class...
static const MCPhysReg QBRC[] = {
PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14,
};
// QBRC Bit set.
static const uint8_t QBRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// QFRC Register Class...
static const MCPhysReg QFRC[] = {
PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13, PPC_QF31, PPC_QF30, PPC_QF29, PPC_QF28, PPC_QF27, PPC_QF26, PPC_QF25, PPC_QF24, PPC_QF23, PPC_QF22, PPC_QF21, PPC_QF20, PPC_QF19, PPC_QF18, PPC_QF17, PPC_QF16, PPC_QF15, PPC_QF14,
};
// QFRC Bit set.
static const uint8_t QFRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
};
// QBRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg QBRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_QF0, PPC_QF1, PPC_QF2, PPC_QF3, PPC_QF4, PPC_QF5, PPC_QF6, PPC_QF7, PPC_QF8, PPC_QF9, PPC_QF10, PPC_QF11, PPC_QF12, PPC_QF13,
};
// QBRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t QBRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x01,
};
// ACCRC Register Class...
static const MCPhysReg ACCRC[] = {
PPC_ACC0, PPC_ACC1, PPC_ACC2, PPC_ACC3, PPC_ACC4, PPC_ACC5, PPC_ACC6, PPC_ACC7,
};
// ACCRC Bit set.
static const uint8_t ACCRCBits[] = {
0x00, 0xf8, 0x07,
};
// UACCRC Register Class...
static const MCPhysReg UACCRC[] = {
PPC_UACC0, PPC_UACC1, PPC_UACC2, PPC_UACC3, PPC_UACC4, PPC_UACC5, PPC_UACC6, PPC_UACC7,
};
// UACCRC Bit set.
static const uint8_t UACCRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
// WACCRC Register Class...
static const MCPhysReg WACCRC[] = {
PPC_WACC0, PPC_WACC1, PPC_WACC2, PPC_WACC3, PPC_WACC4, PPC_WACC5, PPC_WACC6, PPC_WACC7,
};
// WACCRC Bit set.
static const uint8_t WACCRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
// WACC_HIRC Register Class...
static const MCPhysReg WACC_HIRC[] = {
PPC_WACC_HI0, PPC_WACC_HI1, PPC_WACC_HI2, PPC_WACC_HI3, PPC_WACC_HI4, PPC_WACC_HI5, PPC_WACC_HI6, PPC_WACC_HI7,
};
// WACC_HIRC Bit set.
static const uint8_t WACC_HIRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
};
// ACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg ACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_ACC0, PPC_ACC1, PPC_ACC2, PPC_ACC3,
};
// ACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t ACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x78,
};
// UACCRC_with_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg UACCRC_with_sub_64_in_SPILLTOVSRRC[] = {
PPC_UACC0, PPC_UACC1, PPC_UACC2, PPC_UACC3,
};
// UACCRC_with_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t UACCRC_with_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
};
// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
PPC_ACC0, PPC_ACC1, PPC_ACC2,
};
// ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x38,
};
// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Register Class...
static const MCPhysReg UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC[] = {
PPC_UACC0, PPC_UACC1, PPC_UACC2,
};
// UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC Bit set.
static const uint8_t UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
};
// DMRRC Register Class...
static const MCPhysReg DMRRC[] = {
PPC_DMR0, PPC_DMR1, PPC_DMR2, PPC_DMR3, PPC_DMR4, PPC_DMR5, PPC_DMR6, PPC_DMR7,
};
// DMRRC Bit set.
static const uint8_t DMRRCBits[] = {
0x00, 0x00, 0x00, 0xe0, 0x1f,
};
// DMRpRC Register Class...
static const MCPhysReg DMRpRC[] = {
PPC_DMRp0, PPC_DMRp1, PPC_DMRp2, PPC_DMRp3,
};
// DMRpRC Bit set.
static const uint8_t DMRpRCBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
};
static const MCRegisterClass PPCMCRegisterClasses[] = {
{ VSSRC, VSSRCBits, sizeof(VSSRCBits) },
{ GPRC, GPRCBits, sizeof(GPRCBits) },
{ GPRC_NOR0, GPRC_NOR0Bits, sizeof(GPRC_NOR0Bits) },
{ GPRC_and_GPRC_NOR0, GPRC_and_GPRC_NOR0Bits, sizeof(GPRC_and_GPRC_NOR0Bits) },
{ CRBITRC, CRBITRCBits, sizeof(CRBITRCBits) },
{ F4RC, F4RCBits, sizeof(F4RCBits) },
{ GPRC32, GPRC32Bits, sizeof(GPRC32Bits) },
{ CRRC, CRRCBits, sizeof(CRRCBits) },
{ CARRYRC, CARRYRCBits, sizeof(CARRYRCBits) },
{ CTRRC, CTRRCBits, sizeof(CTRRCBits) },
{ LRRC, LRRCBits, sizeof(LRRCBits) },
{ VRSAVERC, VRSAVERCBits, sizeof(VRSAVERCBits) },
{ SPILLTOVSRRC, SPILLTOVSRRCBits, sizeof(SPILLTOVSRRCBits) },
{ VSFRC, VSFRCBits, sizeof(VSFRCBits) },
{ G8RC, G8RCBits, sizeof(G8RCBits) },
{ G8RC_NOX0, G8RC_NOX0Bits, sizeof(G8RC_NOX0Bits) },
{ SPILLTOVSRRC_and_VSFRC, SPILLTOVSRRC_and_VSFRCBits, sizeof(SPILLTOVSRRC_and_VSFRCBits) },
{ G8RC_and_G8RC_NOX0, G8RC_and_G8RC_NOX0Bits, sizeof(G8RC_and_G8RC_NOX0Bits) },
{ F8RC, F8RCBits, sizeof(F8RCBits) },
{ SPERC, SPERCBits, sizeof(SPERCBits) },
{ VFRC, VFRCBits, sizeof(VFRCBits) },
{ SPERC_with_sub_32_in_GPRC_NOR0, SPERC_with_sub_32_in_GPRC_NOR0Bits, sizeof(SPERC_with_sub_32_in_GPRC_NOR0Bits) },
{ SPILLTOVSRRC_and_VFRC, SPILLTOVSRRC_and_VFRCBits, sizeof(SPILLTOVSRRC_and_VFRCBits) },
{ SPILLTOVSRRC_and_F4RC, SPILLTOVSRRC_and_F4RCBits, sizeof(SPILLTOVSRRC_and_F4RCBits) },
{ CTRRC8, CTRRC8Bits, sizeof(CTRRC8Bits) },
{ LR8RC, LR8RCBits, sizeof(LR8RCBits) },
{ DMRROWRC, DMRROWRCBits, sizeof(DMRROWRCBits) },
{ VSRC, VSRCBits, sizeof(VSRCBits) },
{ VSRC_with_sub_64_in_SPILLTOVSRRC, VSRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ QSRC, QSRCBits, sizeof(QSRCBits) },
{ VRRC, VRRCBits, sizeof(VRRCBits) },
{ VSLRC, VSLRCBits, sizeof(VSLRCBits) },
{ VRRC_with_sub_64_in_SPILLTOVSRRC, VRRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VRRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ FpRC, FpRCBits, sizeof(FpRCBits) },
{ G8pRC, G8pRCBits, sizeof(G8pRCBits) },
{ G8pRC_with_sub_32_in_GPRC_NOR0, G8pRC_with_sub_32_in_GPRC_NOR0Bits, sizeof(G8pRC_with_sub_32_in_GPRC_NOR0Bits) },
{ QSRC_with_sub_64_in_SPILLTOVSRRC, QSRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(QSRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ VSLRC_with_sub_64_in_SPILLTOVSRRC, VSLRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSLRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ FpRC_with_sub_fp0_in_SPILLTOVSRRC, FpRC_with_sub_fp0_in_SPILLTOVSRRCBits, sizeof(FpRC_with_sub_fp0_in_SPILLTOVSRRCBits) },
{ DMRROWpRC, DMRROWpRCBits, sizeof(DMRROWpRCBits) },
{ VSRpRC, VSRpRCBits, sizeof(VSRpRCBits) },
{ VSRpRC_with_sub_64_in_SPILLTOVSRRC, VSRpRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ VSRpRC_with_sub_64_in_F4RC, VSRpRC_with_sub_64_in_F4RCBits, sizeof(VSRpRC_with_sub_64_in_F4RCBits) },
{ VSRpRC_with_sub_64_in_VFRC, VSRpRC_with_sub_64_in_VFRCBits, sizeof(VSRpRC_with_sub_64_in_VFRCBits) },
{ VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_VFRCBits) },
{ VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RC, VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits, sizeof(VSRpRC_with_sub_64_in_SPILLTOVSRRC_and_F4RCBits) },
{ QBRC, QBRCBits, sizeof(QBRCBits) },
{ QFRC, QFRCBits, sizeof(QFRCBits) },
{ QBRC_with_sub_64_in_SPILLTOVSRRC, QBRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(QBRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ ACCRC, ACCRCBits, sizeof(ACCRCBits) },
{ UACCRC, UACCRCBits, sizeof(UACCRCBits) },
{ WACCRC, WACCRCBits, sizeof(WACCRCBits) },
{ WACC_HIRC, WACC_HIRCBits, sizeof(WACC_HIRCBits) },
{ ACCRC_with_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(ACCRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ UACCRC_with_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_64_in_SPILLTOVSRRCBits, sizeof(UACCRC_with_sub_64_in_SPILLTOVSRRCBits) },
{ ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, sizeof(ACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits) },
{ UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRC, UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits, sizeof(UACCRC_with_sub_pair1_then_sub_64_in_SPILLTOVSRRCBits) },
{ DMRRC, DMRRCBits, sizeof(DMRRCBits) },
{ DMRpRC, DMRpRCBits, sizeof(DMRpRCBits) },
};
static const uint16_t PPCRegEncodingTable[] = {
0,
0,
1,
9,
0,
8,
0,
512,
256,
1,
0,
0,
1,
2,
3,
4,
5,
6,
7,
0,
0,
1,
2,
3,
4,
5,
6,
7,
9,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
0,
2,
4,
6,
8,
10,
12,
14,
16,
18,
20,
22,
24,
26,
28,
30,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
31,
8,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
32,
33,
34,
35,
36,
37,
38,
39,
40,
41,
42,
43,
44,
45,
46,
47,
48,
49,
50,
51,
52,
53,
54,
55,
56,
57,
58,
59,
60,
61,
62,
63,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
0,
1,
2,
3,
4,
5,
6,
7,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
31,
0,
2,
6,
10,
14,
18,
22,
26,
30,
1,
5,
9,
13,
17,
21,
25,
29,
0,
4,
8,
12,
16,
20,
24,
28,
3,
7,
11,
15,
19,
23,
27,
31,
0,
2,
4,
6,
8,
10,
12,
14,
16,
18,
20,
22,
24,
26,
28,
30,
};
#endif // GET_REGINFO_MC_DESC
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