iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
465 lines
15 KiB
C
465 lines
15 KiB
C
//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
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Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
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#ifdef CAPSTONE_HAS_RISCV
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#include <stdio.h> // DEBUG
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#include <stdlib.h>
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#include <string.h>
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCDisassembler.h"
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#include "../../MathExtras.h"
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#include "../../Mapping.h"
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#include "RISCVBaseInfo.h"
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#include "RISCVDisassembler.h"
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/* Need the feature infos define in
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RISCVGenSubtargetInfo.inc. */
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#define GET_SUBTARGETINFO_ENUM
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#include "RISCVGenSubtargetInfo.inc"
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/* When we specify the RISCV64 mode, It means It is RV64IMAFD.
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Similar, RISCV32 means RV32IMAFD.
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*/
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static uint64_t getFeatureBits(int mode)
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{
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uint64_t ret = RISCV_FeatureStdExtM | RISCV_FeatureStdExtA |
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RISCV_FeatureStdExtF | RISCV_FeatureStdExtD ;
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if (mode & CS_MODE_RISCV64)
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ret |= RISCV_Feature64Bit;
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if (mode & CS_MODE_RISCVC)
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ret |= RISCV_FeatureStdExtC;
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return ret;
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}
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_MC_DESC
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#include "RISCVGenRegisterInfo.inc"
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#define GET_INSTRINFO_ENUM
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#include "RISCVGenInstrInfo.inc"
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static const unsigned GPRDecoderTable[] = {
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RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3,
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RISCV_X4, RISCV_X5, RISCV_X6, RISCV_X7,
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RISCV_X8, RISCV_X9, RISCV_X10, RISCV_X11,
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RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15,
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RISCV_X16, RISCV_X17, RISCV_X18, RISCV_X19,
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RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23,
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RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27,
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RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31
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};
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static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg = 0;
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if (RegNo >= ARR_SIZE(GPRDecoderTable))
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return MCDisassembler_Fail;
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// We must define our own mapping from RegNo to register identifier.
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// Accessing index RegNo in the register class will work in the case that
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// registers were added in ascending order, but not in general.
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Reg = GPRDecoderTable[RegNo];
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//Inst.addOperand(MCOperand::createReg(Reg));
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static const unsigned FPR32DecoderTable[] = {
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RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32,
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RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32,
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RISCV_F8_32, RISCV_F9_32, RISCV_F10_32, RISCV_F11_32,
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RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32,
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RISCV_F16_32, RISCV_F17_32, RISCV_F18_32, RISCV_F19_32,
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RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32,
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RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32,
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RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32
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};
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static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg = 0;
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if (RegNo >= ARR_SIZE(FPR32DecoderTable))
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return MCDisassembler_Fail;
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// We must define our own mapping from RegNo to register identifier.
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// Accessing index RegNo in the register class will work in the case that
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// registers were added in ascending order, but not in general.
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Reg = FPR32DecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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unsigned Reg = 0;
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if (RegNo > 8)
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return MCDisassembler_Fail;
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Reg = FPR32DecoderTable[RegNo + 8];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static const unsigned FPR64DecoderTable[] = {
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RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64,
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RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64,
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RISCV_F8_64, RISCV_F9_64, RISCV_F10_64, RISCV_F11_64,
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RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64,
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RISCV_F16_64, RISCV_F17_64, RISCV_F18_64, RISCV_F19_64,
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RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64,
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RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64,
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RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64
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};
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static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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unsigned Reg = 0;
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if (RegNo >= ARR_SIZE(FPR64DecoderTable))
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return MCDisassembler_Fail;
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// We must define our own mapping from RegNo to register identifier.
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// Accessing index RegNo in the register class will work in the case that
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// registers were added in ascending order, but not in general.
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Reg = FPR64DecoderTable[RegNo];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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unsigned Reg = 0;
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if (RegNo > 8)
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return MCDisassembler_Fail;
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Reg = FPR64DecoderTable[RegNo + 8];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo == 0)
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return MCDisassembler_Fail;
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo == 2)
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return MCDisassembler_Fail;
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return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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unsigned Reg = 0;
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if (RegNo > 8)
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return MCDisassembler_Fail;
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Reg = GPRDecoderTable[RegNo + 8];
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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// Add implied SP operand for instructions *SP compressed instructions. The SP
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// operand isn't explicitly encoded in the instruction.
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static void addImplySP(MCInst *Inst, int64_t Address, const void *Decoder)
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{
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if (MCInst_getOpcode(Inst) == RISCV_C_LWSP ||
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MCInst_getOpcode(Inst) == RISCV_C_SWSP ||
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MCInst_getOpcode(Inst) == RISCV_C_LDSP ||
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MCInst_getOpcode(Inst) == RISCV_C_SDSP ||
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MCInst_getOpcode(Inst) == RISCV_C_FLWSP ||
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MCInst_getOpcode(Inst) == RISCV_C_FSWSP ||
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MCInst_getOpcode(Inst) == RISCV_C_FLDSP ||
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MCInst_getOpcode(Inst) == RISCV_C_FSDSP ||
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MCInst_getOpcode(Inst) == RISCV_C_ADDI4SPN) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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if (MCInst_getOpcode(Inst) == RISCV_C_ADDI16SP) {
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
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}
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}
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static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address, const void *Decoder,
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unsigned N)
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{
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//CS_ASSERT(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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//Inst.addOperand(MCOperand::createImm(Imm));
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MCOperand_CreateImm0(Inst, Imm);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeUImmNonZeroOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder,
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unsigned N)
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{
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if (Imm == 0)
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return MCDisassembler_Fail;
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return decodeUImmOperand(Inst, Imm, Address, Decoder, N);
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}
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static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address, const void *Decoder,
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unsigned N)
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{
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//CS_ASSERT(isUInt<N>(Imm) && "Invalid immediate");
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addImplySP(Inst, Address, Decoder);
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// Sign-extend the number in the bottom N bits of Imm
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//Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
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MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeSImmNonZeroOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder,
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unsigned N)
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{
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if (Imm == 0)
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return MCDisassembler_Fail;
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return decodeSImmOperand(Inst, Imm, Address, Decoder, N);
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}
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static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder,
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unsigned N)
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{
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//CS_ASSERT(isUInt<N>(Imm) && "Invalid immediate");
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// Sign-extend the number in the bottom N bits of Imm after accounting for
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// the fact that the N bit immediate is stored in N-1 bits (the LSB is
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// always zero)
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//Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
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MCOperand_CreateImm0(Inst, SignExtend64(Imm << 1, N));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder)
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{
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//CS_ASSERT(isUInt<6>(Imm) && "Invalid immediate");
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if (Imm > 31) {
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Imm = (SignExtend64(Imm, 6) & 0xfffff);
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}
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//Inst.addOperand(MCOperand::createImm(Imm));
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MCOperand_CreateImm0(Inst, Imm);
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm,
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int64_t Address,
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const void *Decoder)
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{
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//CS_ASSERT(isUInt<3>(Imm) && "Invalid immediate");
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if (!RISCVFPRndMode_isValidRoundingMode(Imm))
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return MCDisassembler_Fail;
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//Inst.addOperand(MCOperand::createImm(Imm));
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MCOperand_CreateImm0(Inst, Imm);
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return MCDisassembler_Success;
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}
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#include "RISCVGenDisassemblerTables.inc"
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static void init_MI_insn_detail(MCInst *MI)
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{
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if (MI->flat_insn->detail) {
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memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
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}
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return;
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}
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// mark the load/store instructions through the opcode.
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static void markLSInsn(MCInst *MI, uint32_t in)
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{
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/*
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I ld 0000011 = 0x03
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st 0100011 = 0x23
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F/D ld 0000111 = 0x07
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st 0100111 = 0x27
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st 0101111 = 0x2f
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*/
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#define MASK_LS_INSN 0x0000007f
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uint32_t opcode = in & MASK_LS_INSN;
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if (0 == (opcode ^ 0x03) || 0 == (opcode ^ 0x07) ||
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0 == (opcode ^ 0x23) || 0 == (opcode ^ 0x27) ||
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0 == (opcode ^ 0x2f))
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MI->flat_insn->detail->riscv.need_effective_addr = true;
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#undef MASK_LS_INSN
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return;
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}
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static void markCLSInsn(MCInst *MI, uint32_t in)
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{
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// Unfortunately there is no obvious pattern in terms of RISC-V C instructions
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// Thus, we compare the instruction IDs to see if it is a load/store instruction
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unsigned id = MCInst_getOpcode(MI);
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if (id == RISCV_C_FLD || id == RISCV_C_LW ||
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id == RISCV_C_FLW || id == RISCV_C_LD ||
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id == RISCV_C_FSD || id == RISCV_C_SW ||
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id == RISCV_C_FSW || id == RISCV_C_SD ||
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id == RISCV_C_FLDSP || id == RISCV_C_LWSP ||
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id == RISCV_C_FLWSP || id == RISCV_C_LDSP ||
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id == RISCV_C_FSDSP || id == RISCV_C_SWSP ||
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id == RISCV_C_FSWSP || id == RISCV_C_SDSP) {
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RISCV_get_detail(MI)->need_effective_addr = true;
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}
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return;
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}
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static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI,
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const uint8_t *code, size_t code_len,
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uint16_t *Size, uint64_t Address,
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MCRegisterInfo *MRI)
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{
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// TODO: This will need modification when supporting instruction set
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// extensions with instructions > 32-bits (up to 176 bits wide).
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uint32_t Inst = 0;
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DecodeStatus Result;
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// It's a 32 bit instruction if bit 0 and 1 are 1.
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if ((code[0] & 0x3) == 0x3) {
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if (code_len < 4) {
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*Size = 0;
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return MCDisassembler_Fail;
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}
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*Size = 4;
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// Get the four bytes of the instruction.
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//Encoded as little endian 32 bits.
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Inst = code[0] | (code[1] << 8) | (code[2] << 16) | ((uint32_t)code[3] << 24);
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init_MI_insn_detail(MI);
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// Now we need mark what instruction need fix effective address output.
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if (MI->csh->detail_opt)
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markLSInsn(MI, Inst);
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Result = decodeInstruction(DecoderTable32, MI, Inst, Address, MRI, mode);
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} else {
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if (code_len < 2) {
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*Size = 0;
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return MCDisassembler_Fail;
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}
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// If not b4bit.
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if (! (getFeatureBits(mode) & ((uint64_t)RISCV_Feature64Bit))) {
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// Trying RISCV32Only_16 table (16-bit Instruction)
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Inst = code[0] | (code[1] << 8);
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init_MI_insn_detail(MI);
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Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Inst, Address,
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MRI, mode);
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if (Result != MCDisassembler_Fail) {
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*Size = 2;
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return Result;
|
|
}
|
|
}
|
|
|
|
// Trying RISCV_C table (16-bit Instruction)
|
|
Inst = code[0] | (code[1] << 8);
|
|
init_MI_insn_detail(MI);
|
|
// Calling the auto-generated decoder function.
|
|
Result = decodeInstruction(DecoderTable16, MI, Inst, Address, MRI, mode);
|
|
// Now we need mark what instruction need fix effective address output.
|
|
// Note that we mark it AFTER the instruction is decoded
|
|
// This is because there is no obvious pattern in terms of RISC-V C instructions
|
|
// So we compare the instruction IDs one by one
|
|
if (detail_is_set(MI))
|
|
markCLSInsn(MI, Inst);
|
|
*Size = 2;
|
|
}
|
|
|
|
return Result;
|
|
}
|
|
|
|
bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len,
|
|
MCInst *instr, uint16_t *size, uint64_t address,
|
|
void *info)
|
|
{
|
|
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
|
|
|
|
DecodeStatus Result =
|
|
RISCVDisassembler_getInstruction(handle->mode, instr,
|
|
code, code_len,
|
|
size, address,
|
|
(MCRegisterInfo *)info);
|
|
if (Result == MCDisassembler_SoftFail) {
|
|
MCInst_setSoftFail(instr);
|
|
}
|
|
return Result != MCDisassembler_Fail;
|
|
|
|
}
|
|
|
|
void RISCV_init(MCRegisterInfo * MRI)
|
|
{
|
|
/*
|
|
InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC,
|
|
RISCVMCRegisterClasses, 11,
|
|
RISCVRegUnitRoots,
|
|
64,
|
|
RISCVRegDiffLists,
|
|
RISCVLaneMaskLists,
|
|
RISCVRegStrings,
|
|
RISCVRegClassStrings,
|
|
RISCVSubRegIdxLists,
|
|
2,
|
|
RISCVSubRegIdxRanges,
|
|
RISCVRegEncodingTable);
|
|
*/
|
|
|
|
MCRegisterInfo_InitMCRegisterInfo(MRI, RISCVRegDesc, 97, 0, 0,
|
|
RISCVMCRegisterClasses, 11,
|
|
0,
|
|
0,
|
|
RISCVRegDiffLists,
|
|
0,
|
|
RISCVSubRegIdxLists,
|
|
2,
|
|
0);
|
|
}
|
|
|
|
#endif
|