iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
954 lines
26 KiB
C
954 lines
26 KiB
C
#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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enum {
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SystemZ_NoRegister,
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SystemZ_CC = 1,
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SystemZ_FPC = 2,
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SystemZ_A0 = 3,
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SystemZ_A1 = 4,
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SystemZ_A2 = 5,
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SystemZ_A3 = 6,
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SystemZ_A4 = 7,
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SystemZ_A5 = 8,
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SystemZ_A6 = 9,
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SystemZ_A7 = 10,
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SystemZ_A8 = 11,
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SystemZ_A9 = 12,
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SystemZ_A10 = 13,
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SystemZ_A11 = 14,
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SystemZ_A12 = 15,
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SystemZ_A13 = 16,
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SystemZ_A14 = 17,
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SystemZ_A15 = 18,
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SystemZ_C0 = 19,
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SystemZ_C1 = 20,
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SystemZ_C2 = 21,
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SystemZ_C3 = 22,
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SystemZ_C4 = 23,
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SystemZ_C5 = 24,
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SystemZ_C6 = 25,
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SystemZ_C7 = 26,
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SystemZ_C8 = 27,
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SystemZ_C9 = 28,
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SystemZ_C10 = 29,
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SystemZ_C11 = 30,
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SystemZ_C12 = 31,
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SystemZ_C13 = 32,
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SystemZ_C14 = 33,
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SystemZ_C15 = 34,
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SystemZ_V0 = 35,
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SystemZ_V1 = 36,
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SystemZ_V2 = 37,
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SystemZ_V3 = 38,
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SystemZ_V4 = 39,
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SystemZ_V5 = 40,
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SystemZ_V6 = 41,
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SystemZ_V7 = 42,
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SystemZ_V8 = 43,
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SystemZ_V9 = 44,
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SystemZ_V10 = 45,
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SystemZ_V11 = 46,
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SystemZ_V12 = 47,
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SystemZ_V13 = 48,
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SystemZ_V14 = 49,
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SystemZ_V15 = 50,
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SystemZ_V16 = 51,
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SystemZ_V17 = 52,
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SystemZ_V18 = 53,
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SystemZ_V19 = 54,
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SystemZ_V20 = 55,
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SystemZ_V21 = 56,
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SystemZ_V22 = 57,
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SystemZ_V23 = 58,
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SystemZ_V24 = 59,
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SystemZ_V25 = 60,
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SystemZ_V26 = 61,
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SystemZ_V27 = 62,
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SystemZ_V28 = 63,
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SystemZ_V29 = 64,
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SystemZ_V30 = 65,
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SystemZ_V31 = 66,
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SystemZ_F0D = 67,
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SystemZ_F1D = 68,
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SystemZ_F2D = 69,
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SystemZ_F3D = 70,
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SystemZ_F4D = 71,
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SystemZ_F5D = 72,
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SystemZ_F6D = 73,
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SystemZ_F7D = 74,
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SystemZ_F8D = 75,
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SystemZ_F9D = 76,
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SystemZ_F10D = 77,
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SystemZ_F11D = 78,
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SystemZ_F12D = 79,
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SystemZ_F13D = 80,
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SystemZ_F14D = 81,
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SystemZ_F15D = 82,
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SystemZ_F16D = 83,
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SystemZ_F17D = 84,
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SystemZ_F18D = 85,
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SystemZ_F19D = 86,
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SystemZ_F20D = 87,
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SystemZ_F21D = 88,
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SystemZ_F22D = 89,
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SystemZ_F23D = 90,
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SystemZ_F24D = 91,
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SystemZ_F25D = 92,
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SystemZ_F26D = 93,
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SystemZ_F27D = 94,
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SystemZ_F28D = 95,
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SystemZ_F29D = 96,
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SystemZ_F30D = 97,
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SystemZ_F31D = 98,
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SystemZ_F0Q = 99,
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SystemZ_F1Q = 100,
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SystemZ_F4Q = 101,
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SystemZ_F5Q = 102,
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SystemZ_F8Q = 103,
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SystemZ_F9Q = 104,
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SystemZ_F12Q = 105,
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SystemZ_F13Q = 106,
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SystemZ_F0S = 107,
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SystemZ_F1S = 108,
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SystemZ_F2S = 109,
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SystemZ_F3S = 110,
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SystemZ_F4S = 111,
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SystemZ_F5S = 112,
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SystemZ_F6S = 113,
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SystemZ_F7S = 114,
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SystemZ_F8S = 115,
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SystemZ_F9S = 116,
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SystemZ_F10S = 117,
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SystemZ_F11S = 118,
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SystemZ_F12S = 119,
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SystemZ_F13S = 120,
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SystemZ_F14S = 121,
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SystemZ_F15S = 122,
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SystemZ_F16S = 123,
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SystemZ_F17S = 124,
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SystemZ_F18S = 125,
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SystemZ_F19S = 126,
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SystemZ_F20S = 127,
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SystemZ_F21S = 128,
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SystemZ_F22S = 129,
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SystemZ_F23S = 130,
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SystemZ_F24S = 131,
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SystemZ_F25S = 132,
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SystemZ_F26S = 133,
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SystemZ_F27S = 134,
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SystemZ_F28S = 135,
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SystemZ_F29S = 136,
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SystemZ_F30S = 137,
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SystemZ_F31S = 138,
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SystemZ_R0D = 139,
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SystemZ_R1D = 140,
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SystemZ_R2D = 141,
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SystemZ_R3D = 142,
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SystemZ_R4D = 143,
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SystemZ_R5D = 144,
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SystemZ_R6D = 145,
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SystemZ_R7D = 146,
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SystemZ_R8D = 147,
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SystemZ_R9D = 148,
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SystemZ_R10D = 149,
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SystemZ_R11D = 150,
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SystemZ_R12D = 151,
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SystemZ_R13D = 152,
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SystemZ_R14D = 153,
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SystemZ_R15D = 154,
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SystemZ_R0H = 155,
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SystemZ_R1H = 156,
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SystemZ_R2H = 157,
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SystemZ_R3H = 158,
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SystemZ_R4H = 159,
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SystemZ_R5H = 160,
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SystemZ_R6H = 161,
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SystemZ_R7H = 162,
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SystemZ_R8H = 163,
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SystemZ_R9H = 164,
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SystemZ_R10H = 165,
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SystemZ_R11H = 166,
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SystemZ_R12H = 167,
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SystemZ_R13H = 168,
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SystemZ_R14H = 169,
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SystemZ_R15H = 170,
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SystemZ_R0L = 171,
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SystemZ_R1L = 172,
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SystemZ_R2L = 173,
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SystemZ_R3L = 174,
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SystemZ_R4L = 175,
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SystemZ_R5L = 176,
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SystemZ_R6L = 177,
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SystemZ_R7L = 178,
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SystemZ_R8L = 179,
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SystemZ_R9L = 180,
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SystemZ_R10L = 181,
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SystemZ_R11L = 182,
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SystemZ_R12L = 183,
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SystemZ_R13L = 184,
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SystemZ_R14L = 185,
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SystemZ_R15L = 186,
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SystemZ_R0Q = 187,
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SystemZ_R2Q = 188,
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SystemZ_R4Q = 189,
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SystemZ_R6Q = 190,
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SystemZ_R8Q = 191,
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SystemZ_R10Q = 192,
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SystemZ_R12Q = 193,
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SystemZ_R14Q = 194,
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NUM_TARGET_REGS // 195
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};
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// Register classes
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enum {
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SystemZ_GRX32BitRegClassID = 0,
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SystemZ_VR32BitRegClassID = 1,
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SystemZ_AR32BitRegClassID = 2,
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SystemZ_FP32BitRegClassID = 3,
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SystemZ_GR32BitRegClassID = 4,
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SystemZ_GRH32BitRegClassID = 5,
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SystemZ_ADDR32BitRegClassID = 6,
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SystemZ_CCRRegClassID = 7,
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SystemZ_FPCRegsRegClassID = 8,
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SystemZ_AnyRegBitRegClassID = 9,
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SystemZ_AnyRegBit_with_subreg_h32_in_FP32BitRegClassID = 10,
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SystemZ_VR64BitRegClassID = 11,
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SystemZ_AnyRegBit_with_subreg_h64RegClassID = 12,
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SystemZ_CR64BitRegClassID = 13,
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SystemZ_FP64BitRegClassID = 14,
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SystemZ_GR64BitRegClassID = 15,
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SystemZ_ADDR64BitRegClassID = 16,
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SystemZ_VR128BitRegClassID = 17,
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SystemZ_VF128BitRegClassID = 18,
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SystemZ_FP128BitRegClassID = 19,
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SystemZ_GR128BitRegClassID = 20,
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SystemZ_ADDR128BitRegClassID = 21,
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};
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// Subregister indices
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enum {
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SystemZ_NoSubRegister,
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SystemZ_subreg_h32, // 1
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SystemZ_subreg_h64, // 2
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SystemZ_subreg_l32, // 3
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SystemZ_subreg_l64, // 4
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SystemZ_subreg_lh32, // 5
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SystemZ_subreg_ll32, // 6
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SystemZ_NUM_TARGET_SUBREGS
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};
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#endif // GET_REGINFO_ENUM
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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static const MCPhysReg SystemZRegDiffLists[] = {
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/* 0 */ -40, -32, 0,
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/* 3 */ -48, 32, -16, -15, 32, -16, 0,
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/* 10 */ -47, 32, -16, -15, 32, -16, 0,
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/* 17 */ -46, 32, -16, -15, 32, -16, 0,
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/* 24 */ -45, 32, -16, -15, 32, -16, 0,
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/* 31 */ -44, 32, -16, -15, 32, -16, 0,
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/* 38 */ -43, 32, -16, -15, 32, -16, 0,
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/* 45 */ -42, 32, -16, -15, 32, -16, 0,
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/* 52 */ -41, 32, -16, -15, 32, -16, 0,
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/* 59 */ 1, 1, 1, 0,
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/* 63 */ 2, 0,
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/* 65 */ -32, 40, -38, 40, 0,
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/* 70 */ -30, 40, -38, 40, 0,
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/* 75 */ -28, 40, -38, 40, 0,
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/* 80 */ -26, 40, -38, 40, 0,
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/* 85 */ -32, 40, 0,
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/* 88 */ -16, 40, 0,
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/* 91 */ 32, 40, 0,
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/* 94 */ -32, 41, 0,
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/* 97 */ -16, 41, 0,
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/* 100 */ -32, 42, 0,
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/* 103 */ -16, 42, 0,
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/* 106 */ -32, 43, 0,
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/* 109 */ -16, 43, 0,
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/* 112 */ -32, 44, 0,
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/* 115 */ -16, 44, 0,
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/* 118 */ -32, 45, 0,
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/* 121 */ -16, 45, 0,
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/* 124 */ -32, 46, 0,
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/* 127 */ -16, 46, 0,
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/* 130 */ -32, 47, 0,
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/* 133 */ -16, 47, 0,
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/* 136 */ -32, 48, 0,
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/* 139 */ -16, 48, 0,
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/* 142 */ -40, -32, 56, 0,
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/* 146 */ -40, -32, 58, 0,
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/* 150 */ -40, -32, 60, 0,
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/* 154 */ -40, -32, 62, 0,
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/* 158 */ -40, -32, 64, 0,
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};
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static const uint16_t SystemZSubRegIdxLists[] = {
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/* 0 */ 2, 1, 0,
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/* 3 */ 3, 1, 0,
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/* 6 */ 2, 1, 4, 5, 0,
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/* 11 */ 2, 3, 1, 4, 6, 5, 0,
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};
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static const MCRegisterDesc SystemZRegDesc[] = { // Descriptors
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{ 3, 0, 0, 0, 0, 0 },
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{ 226, 2, 2, 2, 8192, 11 },
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{ 229, 2, 2, 2, 8193, 11 },
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{ 20, 2, 2, 2, 8194, 11 },
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{ 49, 2, 2, 2, 8195, 11 },
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{ 74, 2, 2, 2, 8196, 11 },
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{ 99, 2, 2, 2, 8197, 11 },
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{ 124, 2, 2, 2, 8198, 11 },
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{ 149, 2, 2, 2, 8199, 11 },
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{ 166, 2, 2, 2, 8200, 11 },
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{ 183, 2, 2, 2, 8201, 11 },
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{ 200, 2, 2, 2, 8202, 11 },
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{ 217, 2, 2, 2, 8203, 11 },
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{ 0, 2, 2, 2, 8204, 11 },
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{ 29, 2, 2, 2, 8205, 11 },
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{ 58, 2, 2, 2, 8206, 11 },
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{ 83, 2, 2, 2, 8207, 11 },
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{ 108, 2, 2, 2, 8208, 11 },
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{ 133, 2, 2, 2, 8209, 11 },
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{ 23, 2, 2, 2, 8210, 11 },
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{ 52, 2, 2, 2, 8211, 11 },
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{ 77, 2, 2, 2, 8212, 11 },
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{ 102, 2, 2, 2, 8213, 11 },
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{ 127, 2, 2, 2, 8214, 11 },
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{ 152, 2, 2, 2, 8215, 11 },
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{ 169, 2, 2, 2, 8216, 11 },
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{ 186, 2, 2, 2, 8217, 11 },
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{ 203, 2, 2, 2, 8218, 11 },
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{ 220, 2, 2, 2, 8219, 11 },
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{ 4, 2, 2, 2, 8220, 11 },
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{ 33, 2, 2, 2, 8221, 11 },
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{ 62, 2, 2, 2, 8222, 11 },
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{ 87, 2, 2, 2, 8223, 11 },
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{ 112, 2, 2, 2, 8224, 11 },
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{ 137, 2, 2, 2, 8225, 11 },
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{ 26, 91, 2, 0, 8226, 1 },
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{ 55, 91, 2, 0, 8227, 1 },
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{ 80, 91, 2, 0, 8228, 1 },
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{ 105, 91, 2, 0, 8229, 1 },
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{ 130, 91, 2, 0, 8230, 1 },
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{ 155, 91, 2, 0, 8231, 1 },
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{ 172, 91, 2, 0, 8232, 1 },
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{ 189, 91, 2, 0, 8233, 1 },
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{ 206, 91, 2, 0, 8234, 1 },
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{ 223, 91, 2, 0, 8235, 1 },
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{ 8, 91, 2, 0, 8236, 1 },
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{ 37, 91, 2, 0, 8237, 1 },
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{ 66, 91, 2, 0, 8238, 1 },
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{ 91, 91, 2, 0, 8239, 1 },
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{ 116, 91, 2, 0, 8240, 1 },
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{ 141, 91, 2, 0, 8241, 1 },
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{ 158, 91, 2, 0, 8242, 1 },
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{ 175, 91, 2, 0, 8243, 1 },
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{ 192, 91, 2, 0, 8244, 1 },
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{ 209, 91, 2, 0, 8245, 1 },
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{ 12, 91, 2, 0, 8246, 1 },
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{ 41, 91, 2, 0, 8247, 1 },
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{ 70, 91, 2, 0, 8248, 1 },
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{ 95, 91, 2, 0, 8249, 1 },
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{ 120, 91, 2, 0, 8250, 1 },
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{ 145, 91, 2, 0, 8251, 1 },
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{ 162, 91, 2, 0, 8252, 1 },
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{ 179, 91, 2, 0, 8253, 1 },
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{ 196, 91, 2, 0, 8254, 1 },
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{ 213, 91, 2, 0, 8255, 1 },
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{ 16, 91, 2, 0, 8256, 1 },
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{ 45, 91, 2, 0, 8257, 1 },
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{ 253, 68, 159, 1, 8226, 1 },
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{ 281, 68, 159, 1, 8227, 1 },
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{ 304, 68, 155, 1, 8228, 1 },
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{ 327, 68, 155, 1, 8229, 1 },
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{ 350, 68, 155, 1, 8230, 1 },
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{ 373, 68, 155, 1, 8231, 1 },
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{ 391, 68, 151, 1, 8232, 1 },
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{ 409, 68, 151, 1, 8233, 1 },
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{ 427, 68, 151, 1, 8234, 1 },
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{ 445, 68, 151, 1, 8235, 1 },
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{ 233, 68, 147, 1, 8236, 1 },
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{ 261, 68, 147, 1, 8237, 1 },
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{ 289, 68, 147, 1, 8238, 1 },
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{ 312, 68, 147, 1, 8239, 1 },
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{ 335, 68, 143, 1, 8240, 1 },
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{ 358, 68, 143, 1, 8241, 1 },
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{ 381, 68, 1, 1, 8242, 1 },
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{ 399, 68, 1, 1, 8243, 1 },
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{ 417, 68, 1, 1, 8244, 1 },
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{ 435, 68, 1, 1, 8245, 1 },
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{ 243, 68, 1, 1, 8246, 1 },
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{ 271, 68, 1, 1, 8247, 1 },
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{ 299, 68, 1, 1, 8248, 1 },
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{ 322, 68, 1, 1, 8249, 1 },
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{ 345, 68, 1, 1, 8250, 1 },
|
|
{ 368, 68, 1, 1, 8251, 1 },
|
|
{ 386, 68, 1, 1, 8252, 1 },
|
|
{ 404, 68, 1, 1, 8253, 1 },
|
|
{ 422, 68, 1, 1, 8254, 1 },
|
|
{ 440, 68, 1, 1, 8255, 1 },
|
|
{ 248, 68, 1, 1, 8256, 1 },
|
|
{ 276, 68, 1, 1, 8257, 1 },
|
|
{ 598, 65, 2, 6, 258082, 3 },
|
|
{ 606, 65, 2, 6, 258083, 3 },
|
|
{ 634, 70, 2, 6, 258086, 3 },
|
|
{ 642, 70, 2, 6, 258087, 3 },
|
|
{ 650, 75, 2, 6, 258090, 3 },
|
|
{ 658, 75, 2, 6, 258091, 3 },
|
|
{ 610, 80, 2, 6, 258094, 3 },
|
|
{ 624, 80, 2, 6, 258095, 3 },
|
|
{ 677, 2, 158, 2, 8226, 11 },
|
|
{ 696, 2, 158, 2, 8227, 11 },
|
|
{ 710, 2, 154, 2, 8228, 11 },
|
|
{ 724, 2, 154, 2, 8229, 11 },
|
|
{ 738, 2, 154, 2, 8230, 11 },
|
|
{ 752, 2, 154, 2, 8231, 11 },
|
|
{ 766, 2, 150, 2, 8232, 11 },
|
|
{ 780, 2, 150, 2, 8233, 11 },
|
|
{ 794, 2, 150, 2, 8234, 11 },
|
|
{ 808, 2, 150, 2, 8235, 11 },
|
|
{ 662, 2, 146, 2, 8236, 11 },
|
|
{ 681, 2, 146, 2, 8237, 11 },
|
|
{ 700, 2, 146, 2, 8238, 11 },
|
|
{ 714, 2, 146, 2, 8239, 11 },
|
|
{ 728, 2, 142, 2, 8240, 11 },
|
|
{ 742, 2, 142, 2, 8241, 11 },
|
|
{ 756, 2, 0, 2, 8242, 11 },
|
|
{ 770, 2, 0, 2, 8243, 11 },
|
|
{ 784, 2, 0, 2, 8244, 11 },
|
|
{ 798, 2, 0, 2, 8245, 11 },
|
|
{ 667, 2, 0, 2, 8246, 11 },
|
|
{ 686, 2, 0, 2, 8247, 11 },
|
|
{ 705, 2, 0, 2, 8248, 11 },
|
|
{ 719, 2, 0, 2, 8249, 11 },
|
|
{ 733, 2, 0, 2, 8250, 11 },
|
|
{ 747, 2, 0, 2, 8251, 11 },
|
|
{ 761, 2, 0, 2, 8252, 11 },
|
|
{ 775, 2, 0, 2, 8253, 11 },
|
|
{ 789, 2, 0, 2, 8254, 11 },
|
|
{ 803, 2, 0, 2, 8255, 11 },
|
|
{ 672, 2, 0, 2, 8256, 11 },
|
|
{ 691, 2, 0, 2, 8257, 11 },
|
|
{ 257, 7, 137, 3, 249922, 0 },
|
|
{ 285, 7, 131, 3, 249924, 0 },
|
|
{ 308, 7, 131, 3, 249926, 0 },
|
|
{ 331, 7, 125, 3, 249928, 0 },
|
|
{ 354, 7, 125, 3, 249930, 0 },
|
|
{ 377, 7, 119, 3, 249932, 0 },
|
|
{ 395, 7, 119, 3, 249934, 0 },
|
|
{ 413, 7, 113, 3, 249936, 0 },
|
|
{ 431, 7, 113, 3, 249938, 0 },
|
|
{ 449, 7, 107, 3, 249940, 0 },
|
|
{ 238, 7, 107, 3, 249942, 0 },
|
|
{ 266, 7, 101, 3, 249944, 0 },
|
|
{ 294, 7, 101, 3, 249946, 0 },
|
|
{ 317, 7, 95, 3, 249948, 0 },
|
|
{ 340, 7, 95, 3, 249950, 0 },
|
|
{ 363, 7, 68, 3, 249952, 0 },
|
|
{ 458, 2, 139, 2, 8259, 11 },
|
|
{ 467, 2, 133, 2, 8261, 11 },
|
|
{ 476, 2, 133, 2, 8263, 11 },
|
|
{ 485, 2, 127, 2, 8265, 11 },
|
|
{ 494, 2, 127, 2, 8267, 11 },
|
|
{ 503, 2, 121, 2, 8269, 11 },
|
|
{ 507, 2, 121, 2, 8271, 11 },
|
|
{ 511, 2, 115, 2, 8273, 11 },
|
|
{ 515, 2, 115, 2, 8275, 11 },
|
|
{ 519, 2, 109, 2, 8277, 11 },
|
|
{ 453, 2, 109, 2, 8279, 11 },
|
|
{ 462, 2, 103, 2, 8281, 11 },
|
|
{ 471, 2, 103, 2, 8283, 11 },
|
|
{ 480, 2, 97, 2, 8285, 11 },
|
|
{ 489, 2, 97, 2, 8287, 11 },
|
|
{ 498, 2, 88, 2, 8289, 11 },
|
|
{ 528, 2, 136, 2, 8258, 11 },
|
|
{ 537, 2, 130, 2, 8260, 11 },
|
|
{ 546, 2, 130, 2, 8262, 11 },
|
|
{ 555, 2, 124, 2, 8264, 11 },
|
|
{ 564, 2, 124, 2, 8266, 11 },
|
|
{ 573, 2, 118, 2, 8268, 11 },
|
|
{ 577, 2, 118, 2, 8270, 11 },
|
|
{ 581, 2, 112, 2, 8272, 11 },
|
|
{ 585, 2, 112, 2, 8274, 11 },
|
|
{ 589, 2, 106, 2, 8276, 11 },
|
|
{ 523, 2, 106, 2, 8278, 11 },
|
|
{ 532, 2, 100, 2, 8280, 11 },
|
|
{ 541, 2, 100, 2, 8282, 11 },
|
|
{ 550, 2, 94, 2, 8284, 11 },
|
|
{ 559, 2, 94, 2, 8286, 11 },
|
|
{ 568, 2, 85, 2, 8288, 11 },
|
|
{ 602, 3, 2, 11, 241730, 6 },
|
|
{ 620, 10, 2, 11, 241734, 6 },
|
|
{ 638, 17, 2, 11, 241738, 6 },
|
|
{ 646, 24, 2, 11, 241742, 6 },
|
|
{ 654, 31, 2, 11, 241746, 6 },
|
|
{ 593, 38, 2, 11, 241750, 6 },
|
|
{ 615, 45, 2, 11, 241754, 6 },
|
|
{ 629, 52, 2, 11, 241758, 6 },
|
|
};
|
|
|
|
// GRX32Bit Register Class...
|
|
static const MCPhysReg GRX32Bit[] = {
|
|
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15L, SystemZ_R15H, SystemZ_R14L, SystemZ_R14H, SystemZ_R13L, SystemZ_R13H, SystemZ_R12L, SystemZ_R12H, SystemZ_R11L, SystemZ_R11H, SystemZ_R10L, SystemZ_R10H, SystemZ_R9L, SystemZ_R9H, SystemZ_R8L, SystemZ_R8H, SystemZ_R7L, SystemZ_R7H, SystemZ_R6L, SystemZ_R6H,
|
|
};
|
|
|
|
// GRX32Bit Bit set.
|
|
static const uint8_t GRX32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
|
};
|
|
|
|
// VR32Bit Register Class...
|
|
static const MCPhysReg VR32Bit[] = {
|
|
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F16S, SystemZ_F17S, SystemZ_F18S, SystemZ_F19S, SystemZ_F20S, SystemZ_F21S, SystemZ_F22S, SystemZ_F23S, SystemZ_F24S, SystemZ_F25S, SystemZ_F26S, SystemZ_F27S, SystemZ_F28S, SystemZ_F29S, SystemZ_F30S, SystemZ_F31S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
|
|
};
|
|
|
|
// VR32Bit Bit set.
|
|
static const uint8_t VR32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
|
};
|
|
|
|
// AR32Bit Register Class...
|
|
static const MCPhysReg AR32Bit[] = {
|
|
SystemZ_A0, SystemZ_A1, SystemZ_A2, SystemZ_A3, SystemZ_A4, SystemZ_A5, SystemZ_A6, SystemZ_A7, SystemZ_A8, SystemZ_A9, SystemZ_A10, SystemZ_A11, SystemZ_A12, SystemZ_A13, SystemZ_A14, SystemZ_A15,
|
|
};
|
|
|
|
// AR32Bit Bit set.
|
|
static const uint8_t AR32BitBits[] = {
|
|
0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// FP32Bit Register Class...
|
|
static const MCPhysReg FP32Bit[] = {
|
|
SystemZ_F0S, SystemZ_F1S, SystemZ_F2S, SystemZ_F3S, SystemZ_F4S, SystemZ_F5S, SystemZ_F6S, SystemZ_F7S, SystemZ_F8S, SystemZ_F9S, SystemZ_F10S, SystemZ_F11S, SystemZ_F12S, SystemZ_F13S, SystemZ_F14S, SystemZ_F15S,
|
|
};
|
|
|
|
// FP32Bit Bit set.
|
|
static const uint8_t FP32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// GR32Bit Register Class...
|
|
static const MCPhysReg GR32Bit[] = {
|
|
SystemZ_R0L, SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
|
|
};
|
|
|
|
// GR32Bit Bit set.
|
|
static const uint8_t GR32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// GRH32Bit Register Class...
|
|
static const MCPhysReg GRH32Bit[] = {
|
|
SystemZ_R0H, SystemZ_R1H, SystemZ_R2H, SystemZ_R3H, SystemZ_R4H, SystemZ_R5H, SystemZ_R15H, SystemZ_R14H, SystemZ_R13H, SystemZ_R12H, SystemZ_R11H, SystemZ_R10H, SystemZ_R9H, SystemZ_R8H, SystemZ_R7H, SystemZ_R6H,
|
|
};
|
|
|
|
// GRH32Bit Bit set.
|
|
static const uint8_t GRH32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// ADDR32Bit Register Class...
|
|
static const MCPhysReg ADDR32Bit[] = {
|
|
SystemZ_R1L, SystemZ_R2L, SystemZ_R3L, SystemZ_R4L, SystemZ_R5L, SystemZ_R15L, SystemZ_R14L, SystemZ_R13L, SystemZ_R12L, SystemZ_R11L, SystemZ_R10L, SystemZ_R9L, SystemZ_R8L, SystemZ_R7L, SystemZ_R6L,
|
|
};
|
|
|
|
// ADDR32Bit Bit set.
|
|
static const uint8_t ADDR32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
|
};
|
|
|
|
// CCR Register Class...
|
|
static const MCPhysReg CCR[] = {
|
|
SystemZ_CC,
|
|
};
|
|
|
|
// CCR Bit set.
|
|
static const uint8_t CCRBits[] = {
|
|
0x02,
|
|
};
|
|
|
|
// FPCRegs Register Class...
|
|
static const MCPhysReg FPCRegs[] = {
|
|
SystemZ_FPC,
|
|
};
|
|
|
|
// FPCRegs Bit set.
|
|
static const uint8_t FPCRegsBits[] = {
|
|
0x04,
|
|
};
|
|
|
|
// AnyRegBit Register Class...
|
|
static const MCPhysReg AnyRegBit[] = {
|
|
SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R6D, SystemZ_R7D, SystemZ_R8D, SystemZ_R9D, SystemZ_R10D, SystemZ_R11D, SystemZ_R12D, SystemZ_R13D, SystemZ_R14D, SystemZ_R15D, SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
|
};
|
|
|
|
// AnyRegBit Bit set.
|
|
static const uint8_t AnyRegBitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// AnyRegBit_with_subreg_h32_in_FP32Bit Register Class...
|
|
static const MCPhysReg AnyRegBit_with_subreg_h32_in_FP32Bit[] = {
|
|
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D, SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
|
};
|
|
|
|
// AnyRegBit_with_subreg_h32_in_FP32Bit Bit set.
|
|
static const uint8_t AnyRegBit_with_subreg_h32_in_FP32BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// VR64Bit Register Class...
|
|
static const MCPhysReg VR64Bit[] = {
|
|
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F16D, SystemZ_F17D, SystemZ_F18D, SystemZ_F19D, SystemZ_F20D, SystemZ_F21D, SystemZ_F22D, SystemZ_F23D, SystemZ_F24D, SystemZ_F25D, SystemZ_F26D, SystemZ_F27D, SystemZ_F28D, SystemZ_F29D, SystemZ_F30D, SystemZ_F31D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
|
|
};
|
|
|
|
// VR64Bit Bit set.
|
|
static const uint8_t VR64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
|
};
|
|
|
|
// AnyRegBit_with_subreg_h64 Register Class...
|
|
static const MCPhysReg AnyRegBit_with_subreg_h64[] = {
|
|
SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
|
};
|
|
|
|
// AnyRegBit_with_subreg_h64 Bit set.
|
|
static const uint8_t AnyRegBit_with_subreg_h64Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// CR64Bit Register Class...
|
|
static const MCPhysReg CR64Bit[] = {
|
|
SystemZ_C0, SystemZ_C1, SystemZ_C2, SystemZ_C3, SystemZ_C4, SystemZ_C5, SystemZ_C6, SystemZ_C7, SystemZ_C8, SystemZ_C9, SystemZ_C10, SystemZ_C11, SystemZ_C12, SystemZ_C13, SystemZ_C14, SystemZ_C15,
|
|
};
|
|
|
|
// CR64Bit Bit set.
|
|
static const uint8_t CR64BitBits[] = {
|
|
0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// FP64Bit Register Class...
|
|
static const MCPhysReg FP64Bit[] = {
|
|
SystemZ_F0D, SystemZ_F1D, SystemZ_F2D, SystemZ_F3D, SystemZ_F4D, SystemZ_F5D, SystemZ_F6D, SystemZ_F7D, SystemZ_F8D, SystemZ_F9D, SystemZ_F10D, SystemZ_F11D, SystemZ_F12D, SystemZ_F13D, SystemZ_F14D, SystemZ_F15D,
|
|
};
|
|
|
|
// FP64Bit Bit set.
|
|
static const uint8_t FP64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// GR64Bit Register Class...
|
|
static const MCPhysReg GR64Bit[] = {
|
|
SystemZ_R0D, SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
|
|
};
|
|
|
|
// GR64Bit Bit set.
|
|
static const uint8_t GR64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// ADDR64Bit Register Class...
|
|
static const MCPhysReg ADDR64Bit[] = {
|
|
SystemZ_R1D, SystemZ_R2D, SystemZ_R3D, SystemZ_R4D, SystemZ_R5D, SystemZ_R15D, SystemZ_R14D, SystemZ_R13D, SystemZ_R12D, SystemZ_R11D, SystemZ_R10D, SystemZ_R9D, SystemZ_R8D, SystemZ_R7D, SystemZ_R6D,
|
|
};
|
|
|
|
// ADDR64Bit Bit set.
|
|
static const uint8_t ADDR64BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
|
};
|
|
|
|
// VR128Bit Register Class...
|
|
static const MCPhysReg VR128Bit[] = {
|
|
SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V16, SystemZ_V17, SystemZ_V18, SystemZ_V19, SystemZ_V20, SystemZ_V21, SystemZ_V22, SystemZ_V23, SystemZ_V24, SystemZ_V25, SystemZ_V26, SystemZ_V27, SystemZ_V28, SystemZ_V29, SystemZ_V30, SystemZ_V31, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
|
};
|
|
|
|
// VR128Bit Bit set.
|
|
static const uint8_t VR128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0xff, 0xff, 0x07,
|
|
};
|
|
|
|
// VF128Bit Register Class...
|
|
static const MCPhysReg VF128Bit[] = {
|
|
SystemZ_V0, SystemZ_V1, SystemZ_V2, SystemZ_V3, SystemZ_V4, SystemZ_V5, SystemZ_V6, SystemZ_V7, SystemZ_V8, SystemZ_V9, SystemZ_V10, SystemZ_V11, SystemZ_V12, SystemZ_V13, SystemZ_V14, SystemZ_V15,
|
|
};
|
|
|
|
// VF128Bit Bit set.
|
|
static const uint8_t VF128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x07,
|
|
};
|
|
|
|
// FP128Bit Register Class...
|
|
static const MCPhysReg FP128Bit[] = {
|
|
SystemZ_F0Q, SystemZ_F1Q, SystemZ_F4Q, SystemZ_F5Q, SystemZ_F8Q, SystemZ_F9Q, SystemZ_F12Q, SystemZ_F13Q,
|
|
};
|
|
|
|
// FP128Bit Bit set.
|
|
static const uint8_t FP128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
|
};
|
|
|
|
// GR128Bit Register Class...
|
|
static const MCPhysReg GR128Bit[] = {
|
|
SystemZ_R0Q, SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
|
|
};
|
|
|
|
// GR128Bit Bit set.
|
|
static const uint8_t GR128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
|
};
|
|
|
|
// ADDR128Bit Register Class...
|
|
static const MCPhysReg ADDR128Bit[] = {
|
|
SystemZ_R2Q, SystemZ_R4Q, SystemZ_R12Q, SystemZ_R10Q, SystemZ_R8Q, SystemZ_R6Q, SystemZ_R14Q,
|
|
};
|
|
|
|
// ADDR128Bit Bit set.
|
|
static const uint8_t ADDR128BitBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
|
|
};
|
|
|
|
static const MCRegisterClass SystemZMCRegisterClasses[] = {
|
|
{ GRX32Bit, GRX32BitBits, sizeof(GRX32BitBits) },
|
|
{ VR32Bit, VR32BitBits, sizeof(VR32BitBits) },
|
|
{ AR32Bit, AR32BitBits, sizeof(AR32BitBits) },
|
|
{ FP32Bit, FP32BitBits, sizeof(FP32BitBits) },
|
|
{ GR32Bit, GR32BitBits, sizeof(GR32BitBits) },
|
|
{ GRH32Bit, GRH32BitBits, sizeof(GRH32BitBits) },
|
|
{ ADDR32Bit, ADDR32BitBits, sizeof(ADDR32BitBits) },
|
|
{ CCR, CCRBits, sizeof(CCRBits) },
|
|
{ FPCRegs, FPCRegsBits, sizeof(FPCRegsBits) },
|
|
{ AnyRegBit, AnyRegBitBits, sizeof(AnyRegBitBits) },
|
|
{ AnyRegBit_with_subreg_h32_in_FP32Bit, AnyRegBit_with_subreg_h32_in_FP32BitBits, sizeof(AnyRegBit_with_subreg_h32_in_FP32BitBits) },
|
|
{ VR64Bit, VR64BitBits, sizeof(VR64BitBits) },
|
|
{ AnyRegBit_with_subreg_h64, AnyRegBit_with_subreg_h64Bits, sizeof(AnyRegBit_with_subreg_h64Bits) },
|
|
{ CR64Bit, CR64BitBits, sizeof(CR64BitBits) },
|
|
{ FP64Bit, FP64BitBits, sizeof(FP64BitBits) },
|
|
{ GR64Bit, GR64BitBits, sizeof(GR64BitBits) },
|
|
{ ADDR64Bit, ADDR64BitBits, sizeof(ADDR64BitBits) },
|
|
{ VR128Bit, VR128BitBits, sizeof(VR128BitBits) },
|
|
{ VF128Bit, VF128BitBits, sizeof(VF128BitBits) },
|
|
{ FP128Bit, FP128BitBits, sizeof(FP128BitBits) },
|
|
{ GR128Bit, GR128BitBits, sizeof(GR128BitBits) },
|
|
{ ADDR128Bit, ADDR128BitBits, sizeof(ADDR128BitBits) },
|
|
};
|
|
|
|
static const uint16_t SystemZRegEncodingTable[] = {
|
|
0,
|
|
0,
|
|
0,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
4,
|
|
5,
|
|
8,
|
|
9,
|
|
12,
|
|
13,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
0,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
14,
|
|
};
|
|
#endif // GET_REGINFO_MC_DESC
|
|
|
|
|
|
|