00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
369 lines
11 KiB
C
369 lines
11 KiB
C
/* Capstone Disassembly Engine */
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/* By Rot127 <unisono@quyllur.org> 2022-2023 */
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#ifdef CAPSTONE_HAS_SYSTEMZ
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#include <stdio.h> // debug
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#include <string.h>
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#include "../../Mapping.h"
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#include "../../utils.h"
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#include "../../cs_simple_types.h"
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#include <capstone/cs_operand.h>
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#include "SystemZMCTargetDesc.h"
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#include "SystemZMapping.h"
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#include "SystemZLinkage.h"
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#ifndef CAPSTONE_DIET
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static const char *const insn_name_maps[] = {
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#include "SystemZGenCSMappingInsnName.inc"
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};
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static const name_map insn_alias_mnem_map[] = {
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#include "SystemZGenCSAliasMnemMap.inc"
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{ SYSTEMZ_INS_ALIAS_END, NULL },
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};
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static const map_insn_ops insn_operands[] = {
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#include "SystemZGenCSMappingInsnOp.inc"
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};
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#endif
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#define GET_REGINFO_MC_DESC
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#include "SystemZGenRegisterInfo.inc"
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const insn_map systemz_insns[] = {
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#include "SystemZGenCSMappingInsn.inc"
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};
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void SystemZ_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen)
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{
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map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns));
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map_implicit_reads(MI, systemz_insns);
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map_implicit_writes(MI, systemz_insns);
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map_groups(MI, systemz_insns);
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const systemz_suppl_info *suppl_info =
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map_get_suppl_info(MI, systemz_insns);
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if (suppl_info) {
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SystemZ_get_detail(MI)->format = suppl_info->form;
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}
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}
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void SystemZ_init_mri(MCRegisterInfo *MRI)
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{
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MCRegisterInfo_InitMCRegisterInfo(
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MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0,
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SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0,
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0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists,
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ARR_SIZE(SystemZSubRegIdxLists), 0);
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}
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const char *SystemZ_reg_name(csh handle, unsigned int reg)
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{
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return SystemZ_LLVM_getRegisterName(reg);
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}
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void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
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{
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MI->MRI = (MCRegisterInfo *)info;
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MI->fillDetailOps = detail_is_set(MI);
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SystemZ_LLVM_printInstruction(MI, "", O);
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#ifndef CAPSTONE_DIET
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map_set_alias_id(MI, O, insn_alias_mnem_map,
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ARR_SIZE(insn_alias_mnem_map));
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#endif
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}
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void SystemZ_init_cs_detail(MCInst *MI) {
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if (!detail_is_set(MI)) {
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return;
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}
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memset(get_detail(MI), 0, sizeof(cs_detail));
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if (detail_is_set(MI)) {
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SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID;
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}
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}
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bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
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MCInst *MI, uint16_t *size, uint64_t address,
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void *info)
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{
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SystemZ_init_cs_detail(MI);
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MI->MRI = (MCRegisterInfo *)info;
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DecodeStatus Result = SystemZ_LLVM_getInstruction(
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handle, bytes, bytes_len, MI, size, address, info);
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SystemZ_set_instr_map_data(MI, bytes, bytes_len);
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if (Result == MCDisassembler_SoftFail) {
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MCInst_setSoftFail(MI);
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}
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return Result != MCDisassembler_Fail;
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}
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// given internal insn id, return public instruction info
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void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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// We do this after Instruction disassembly.
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}
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const char *SystemZ_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) {
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if (id - SYSTEMZ_INS_ALIAS_BEGIN >=
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ARR_SIZE(insn_alias_mnem_map))
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return NULL;
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return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1]
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.name;
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}
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if (id >= SYSTEMZ_INS_ENDING)
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return NULL;
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if (id < ARR_SIZE(insn_name_maps))
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return insn_name_maps[id];
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// not found
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return NULL;
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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// generic groups
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{ SYSTEMZ_GRP_INVALID, NULL },
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{ SYSTEMZ_GRP_JUMP, "jump" },
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{ SYSTEMZ_GRP_CALL, "call" },
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{ SYSTEMZ_GRP_RET, "return" },
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{ SYSTEMZ_GRP_INT, "int" },
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{ SYSTEMZ_GRP_IRET, "iret" },
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{ SYSTEMZ_GRP_PRIVILEGE, "privilege" },
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{ SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" },
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#include "SystemZGenCSFeatureName.inc"
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};
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#endif
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const char *SystemZ_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
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#else
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return NULL;
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#endif
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}
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void SystemZ_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
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va_list args)
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{
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#ifndef CAPSTONE_DIET
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if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
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return;
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unsigned op_num = va_arg(args, unsigned);
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switch (op_group) {
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default:
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printf("Operand group %d not handled\n", op_group);
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break;
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case SystemZ_OP_GROUP_Operand: {
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cs_op_type secondary_op_type = map_get_op_type(MI, op_num) &
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~(CS_OP_MEM | CS_OP_BOUND);
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if (secondary_op_type == CS_OP_IMM) {
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 0);
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} else if (secondary_op_type == CS_OP_REG) {
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SystemZ_set_detail_op_reg(MI, op_num,
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MCInst_getOpVal(MI, op_num));
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} else {
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CS_ASSERT_RET(0 && "Op type not handled.");
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}
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break;
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}
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case SystemZ_OP_GROUP_Cond4Operand: {
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systemz_cc cc = MCInst_getOpVal(MI, op_num);
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SystemZ_get_detail(MI)->cc = cc;
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break;
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}
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case SystemZ_OP_GROUP_BDAddrOperand:
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CS_ASSERT_RET(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT_RET(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT_RET(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT_RET(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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0,
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0,
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SYSTEMZ_AM_BD
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);
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break;
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case SystemZ_OP_GROUP_BDVAddrOperand:
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case SystemZ_OP_GROUP_BDXAddrOperand: {
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CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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0,
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MCInst_getOpVal(MI, (op_num + 2)),
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(op_group == SystemZ_OP_GROUP_BDXAddrOperand ? SYSTEMZ_AM_BDX : SYSTEMZ_AM_BDV)
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);
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break;
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}
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case SystemZ_OP_GROUP_BDLAddrOperand:
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CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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MCInst_getOpVal(MI, (op_num + 2)),
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0,
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SYSTEMZ_AM_BDL
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);
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break;
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case SystemZ_OP_GROUP_BDRAddrOperand:
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CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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MCInst_getOpVal(MI, (op_num + 2)),
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0,
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SYSTEMZ_AM_BDL
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);
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break;
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case SystemZ_OP_GROUP_PCRelOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 0);
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break;
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case SystemZ_OP_GROUP_U1ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 1);
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break;
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case SystemZ_OP_GROUP_U2ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 2);
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break;
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case SystemZ_OP_GROUP_U3ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 3);
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break;
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case SystemZ_OP_GROUP_U4ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 4);
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break;
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case SystemZ_OP_GROUP_U8ImmOperand:
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case SystemZ_OP_GROUP_S8ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 8);
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break;
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case SystemZ_OP_GROUP_U12ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 12);
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break;
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case SystemZ_OP_GROUP_U16ImmOperand:
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case SystemZ_OP_GROUP_S16ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 16);
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break;
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case SystemZ_OP_GROUP_U32ImmOperand:
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case SystemZ_OP_GROUP_S32ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 32);
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break;
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case SystemZ_OP_GROUP_U48ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 48);
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break;
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}
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#endif
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}
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#ifndef CAPSTONE_DIET
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void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm, size_t width)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM);
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SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
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SystemZ_get_detail_op(MI, 0)->imm = Imm;
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SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
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SystemZ_get_detail_op(MI, 0)->imm_width = width;
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SystemZ_inc_op_count(MI);
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}
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void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG);
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SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG;
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SystemZ_get_detail_op(MI, 0)->reg = Reg;
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SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
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SystemZ_inc_op_count(MI);
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}
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void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am)
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{
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if (!detail_is_set(MI))
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return;
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SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM;
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SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
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SystemZ_get_detail_op(MI, 0)->mem.am = am;
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switch(am) {
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default:
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CS_ASSERT(0 && "Address mode not handled\n");
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break;
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case SYSTEMZ_AM_BD:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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break;
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case SYSTEMZ_AM_BDX:
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case SYSTEMZ_AM_BDV:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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SystemZ_get_detail_op(MI, 0)->mem.index = index;
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break;
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case SYSTEMZ_AM_BDL:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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SystemZ_get_detail_op(MI, 0)->mem.length = length;
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break;
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case SYSTEMZ_AM_BDR:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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SystemZ_get_detail_op(MI, 0)->mem.length = length;
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break;
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}
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SystemZ_inc_op_count(MI);
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}
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#endif
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#endif
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