iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
629 lines
16 KiB
C
629 lines
16 KiB
C
/* Capstone Disassembly Engine */
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/* TMS320C64x Backend by Fotis Loukos <me@fotisl.com> 2016 */
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#ifdef CAPSTONE_HAS_TMS320C64X
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#include <string.h>
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "TMS320C64xDisassembler.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCDisassembler.h"
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#include "../../MathExtras.h"
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static uint64_t getFeatureBits(int mode);
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static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder);
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#include "TMS320C64xGenDisassemblerTables.inc"
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_MC_DESC
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#include "TMS320C64xGenRegisterInfo.inc"
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static const unsigned GPRegsDecoderTable[] = {
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TMS320C64x_A0, TMS320C64x_A1, TMS320C64x_A2, TMS320C64x_A3,
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TMS320C64x_A4, TMS320C64x_A5, TMS320C64x_A6, TMS320C64x_A7,
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TMS320C64x_A8, TMS320C64x_A9, TMS320C64x_A10, TMS320C64x_A11,
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TMS320C64x_A12, TMS320C64x_A13, TMS320C64x_A14, TMS320C64x_A15,
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TMS320C64x_A16, TMS320C64x_A17, TMS320C64x_A18, TMS320C64x_A19,
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TMS320C64x_A20, TMS320C64x_A21, TMS320C64x_A22, TMS320C64x_A23,
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TMS320C64x_A24, TMS320C64x_A25, TMS320C64x_A26, TMS320C64x_A27,
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TMS320C64x_A28, TMS320C64x_A29, TMS320C64x_A30, TMS320C64x_A31
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};
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static const unsigned ControlRegsDecoderTable[] = {
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TMS320C64x_AMR, TMS320C64x_CSR, TMS320C64x_ISR, TMS320C64x_ICR,
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TMS320C64x_IER, TMS320C64x_ISTP, TMS320C64x_IRP, TMS320C64x_NRP,
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~0U, ~0U, TMS320C64x_TSCL, TMS320C64x_TSCH,
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~0U, TMS320C64x_ILC, TMS320C64x_RILC, TMS320C64x_REP,
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TMS320C64x_PCE1, TMS320C64x_DNUM, ~0U, ~0U,
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~0U, TMS320C64x_SSR, TMS320C64x_GPLYA, TMS320C64x_GPLYB,
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TMS320C64x_GFPGFR, TMS320C64x_DIER, TMS320C64x_TSR, TMS320C64x_ITSR,
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TMS320C64x_NTSR, TMS320C64x_ECR, ~0U, TMS320C64x_IERR
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};
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static uint64_t getFeatureBits(int mode)
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{
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// support everything
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return (uint64_t)-1;
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}
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static unsigned getReg(const unsigned *RegTable, unsigned RegNo)
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{
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if(RegNo > 31)
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return ~0U;
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return RegTable[RegNo];
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}
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static DecodeStatus DecodeGPRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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unsigned Reg;
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if(RegNo > 31)
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return MCDisassembler_Fail;
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Reg = getReg(GPRegsDecoderTable, RegNo);
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if(Reg == ~0U)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeControlRegsRegisterClass(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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unsigned Reg;
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if(RegNo > 31)
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return MCDisassembler_Fail;
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Reg = getReg(ControlRegsDecoderTable, RegNo);
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if(Reg == ~0U)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeScst5(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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int32_t imm;
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imm = Val;
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/* Sign extend 5 bit value */
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if(imm & (1 << (5 - 1)))
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imm |= ~((1 << 5) - 1);
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MCOperand_CreateImm0(Inst, imm);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeScst16(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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int32_t imm;
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imm = Val;
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/* Sign extend 16 bit value */
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if(imm & (1 << (16 - 1)))
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imm |= ~((1 << 16) - 1);
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MCOperand_CreateImm0(Inst, imm);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodePCRelScst7(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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int32_t imm;
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imm = Val;
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/* Sign extend 7 bit value */
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if(imm & (1 << (7 - 1)))
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imm |= ~((1 << 7) - 1);
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/* Address is relative to the address of the first instruction in the fetch packet */
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MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodePCRelScst10(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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int32_t imm;
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imm = Val;
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/* Sign extend 10 bit value */
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if(imm & (1 << (10 - 1)))
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imm |= ~((1 << 10) - 1);
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/* Address is relative to the address of the first instruction in the fetch packet */
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MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodePCRelScst12(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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int32_t imm;
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imm = Val;
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/* Sign extend 12 bit value */
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if(imm & (1 << (12 - 1)))
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imm |= ~((1 << 12) - 1);
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/* Address is relative to the address of the first instruction in the fetch packet */
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MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodePCRelScst21(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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int32_t imm;
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imm = Val;
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/* Sign extend 21 bit value */
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if(imm & (1 << (21 - 1)))
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imm |= ~((1 << 21) - 1);
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/* Address is relative to the address of the first instruction in the fetch packet */
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MCOperand_CreateImm0(Inst, (Address & ~31) + (imm * 4));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeMemOperand(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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return DecodeMemOperandSc(Inst, Val | (1 << 15), Address, Decoder);
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}
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static DecodeStatus DecodeMemOperandSc(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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uint8_t scaled, base, offset, mode, unit;
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unsigned basereg, offsetreg;
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scaled = (Val >> 15) & 1;
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base = (Val >> 10) & 0x1f;
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offset = (Val >> 5) & 0x1f;
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mode = (Val >> 1) & 0xf;
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unit = Val & 1;
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if((base >= TMS320C64X_REG_A0) && (base <= TMS320C64X_REG_A31))
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base = (base - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
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// base cannot be a B register, because it was ANDed above with 0x1f.
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// And the TMS320C64X_REG_B0 > 31
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basereg = getReg(GPRegsDecoderTable, base);
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if (basereg == ~0U)
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return MCDisassembler_Fail;
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switch(mode) {
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case 0:
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case 1:
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case 8:
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case 9:
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case 10:
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case 11:
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MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offset << 5) | (mode << 1) | unit);
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break;
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case 4:
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case 5:
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case 12:
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case 13:
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case 14:
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case 15:
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if((offset >= TMS320C64X_REG_A0) && (offset <= TMS320C64X_REG_A31))
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offset = (offset - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
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// offset cannot be a B register, because it was ANDed above with 0x1f.
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// And the TMS320C64X_REG_B0 > 31
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offsetreg = getReg(GPRegsDecoderTable, offset);
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if (offsetreg == ~0U)
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return MCDisassembler_Fail;
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MCOperand_CreateImm0(Inst, (scaled << 19) | (basereg << 12) | (offsetreg << 5) | (mode << 1) | unit);
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break;
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default:
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return MCDisassembler_Fail;
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}
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeMemOperand2(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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uint16_t offset;
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unsigned basereg;
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if(Val & 1)
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basereg = TMS320C64X_REG_B15;
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else
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basereg = TMS320C64X_REG_B14;
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offset = (Val >> 1) & 0x7fff;
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MCOperand_CreateImm0(Inst, (offset << 7) | basereg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeRegPair5(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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unsigned Reg;
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if(RegNo > 31)
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return MCDisassembler_Fail;
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Reg = getReg(GPRegsDecoderTable, RegNo);
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeRegPair4(MCInst *Inst, unsigned RegNo,
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uint64_t Address, void *Decoder)
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{
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unsigned Reg;
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if(RegNo > 15)
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return MCDisassembler_Fail;
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Reg = getReg(GPRegsDecoderTable, RegNo << 1);
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeCondRegister(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus ret = MCDisassembler_Success;
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if(!Inst->flat_insn->detail)
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return MCDisassembler_Success;
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switch(Val) {
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case 0:
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case 7:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID;
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break;
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case 1:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B0;
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break;
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case 2:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B1;
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break;
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case 3:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_B2;
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break;
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case 4:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A1;
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break;
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case 5:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A2;
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break;
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case 6:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_A0;
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break;
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default:
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Inst->flat_insn->detail->tms320c64x.condition.reg = TMS320C64X_REG_INVALID;
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ret = MCDisassembler_Fail;
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break;
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}
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return ret;
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}
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static DecodeStatus DecodeCondRegisterZero(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus ret = MCDisassembler_Success;
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if(!Inst->flat_insn->detail)
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return MCDisassembler_Success;
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switch(Val) {
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case 0:
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Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
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break;
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case 1:
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Inst->flat_insn->detail->tms320c64x.condition.zero = 1;
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break;
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default:
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Inst->flat_insn->detail->tms320c64x.condition.zero = 0;
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ret = MCDisassembler_Fail;
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break;
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}
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return ret;
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}
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static DecodeStatus DecodeSide(MCInst *Inst, unsigned Val,
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uint64_t Address, void *Decoder)
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{
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DecodeStatus ret = MCDisassembler_Success;
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MCOperand *op;
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int i;
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/* This is pretty messy, probably we should find a better way */
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if(Val == 1) {
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for(i = 0; i < Inst->size; i++) {
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op = &Inst->Operands[i];
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if(op->Kind == kRegister) {
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if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
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op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
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else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
|
|
op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
|
|
}
|
|
}
|
|
}
|
|
|
|
if(!Inst->flat_insn->detail)
|
|
return MCDisassembler_Success;
|
|
|
|
switch(Val) {
|
|
case 0:
|
|
Inst->flat_insn->detail->tms320c64x.funit.side = 1;
|
|
break;
|
|
case 1:
|
|
Inst->flat_insn->detail->tms320c64x.funit.side = 2;
|
|
break;
|
|
default:
|
|
Inst->flat_insn->detail->tms320c64x.funit.side = 0;
|
|
ret = MCDisassembler_Fail;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static DecodeStatus DecodeParallel(MCInst *Inst, unsigned Val,
|
|
uint64_t Address, void *Decoder)
|
|
{
|
|
DecodeStatus ret = MCDisassembler_Success;
|
|
|
|
if(!Inst->flat_insn->detail)
|
|
return MCDisassembler_Success;
|
|
|
|
switch(Val) {
|
|
case 0:
|
|
Inst->flat_insn->detail->tms320c64x.parallel = 0;
|
|
break;
|
|
case 1:
|
|
Inst->flat_insn->detail->tms320c64x.parallel = 1;
|
|
break;
|
|
default:
|
|
Inst->flat_insn->detail->tms320c64x.parallel = -1;
|
|
ret = MCDisassembler_Fail;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static DecodeStatus DecodeCrosspathX1(MCInst *Inst, unsigned Val,
|
|
uint64_t Address, void *Decoder)
|
|
{
|
|
DecodeStatus ret = MCDisassembler_Success;
|
|
MCOperand *op;
|
|
|
|
if(!Inst->flat_insn->detail)
|
|
return MCDisassembler_Success;
|
|
|
|
switch(Val) {
|
|
case 0:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
|
|
break;
|
|
case 1:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
|
|
op = &Inst->Operands[0];
|
|
if(op->Kind == kRegister) {
|
|
if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
|
|
op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
|
|
else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
|
|
op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
|
|
}
|
|
break;
|
|
default:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
|
|
ret = MCDisassembler_Fail;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static DecodeStatus DecodeCrosspathX2(MCInst *Inst, unsigned Val,
|
|
uint64_t Address, void *Decoder)
|
|
{
|
|
DecodeStatus ret = MCDisassembler_Success;
|
|
MCOperand *op;
|
|
|
|
if(!Inst->flat_insn->detail)
|
|
return MCDisassembler_Success;
|
|
|
|
switch(Val) {
|
|
case 0:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
|
|
break;
|
|
case 1:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = 1;
|
|
op = &Inst->Operands[1];
|
|
if(op->Kind == kRegister) {
|
|
if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
|
|
op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
|
|
else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
|
|
op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
|
|
}
|
|
break;
|
|
default:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
|
|
ret = MCDisassembler_Fail;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static DecodeStatus DecodeCrosspathX3(MCInst *Inst, unsigned Val,
|
|
uint64_t Address, void *Decoder)
|
|
{
|
|
DecodeStatus ret = MCDisassembler_Success;
|
|
MCOperand *op;
|
|
|
|
if(!Inst->flat_insn->detail)
|
|
return MCDisassembler_Success;
|
|
|
|
switch(Val) {
|
|
case 0:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = 0;
|
|
break;
|
|
case 1:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = 2;
|
|
op = &Inst->Operands[2];
|
|
if(op->Kind == kRegister) {
|
|
if((op->RegVal >= TMS320C64X_REG_A0) && (op->RegVal <= TMS320C64X_REG_A31))
|
|
op->RegVal = (op->RegVal - TMS320C64X_REG_A0 + TMS320C64X_REG_B0);
|
|
else if((op->RegVal >= TMS320C64X_REG_B0) && (op->RegVal <= TMS320C64X_REG_B31))
|
|
op->RegVal = (op->RegVal - TMS320C64X_REG_B0 + TMS320C64X_REG_A0);
|
|
}
|
|
break;
|
|
default:
|
|
Inst->flat_insn->detail->tms320c64x.funit.crosspath = -1;
|
|
ret = MCDisassembler_Fail;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
|
|
static DecodeStatus DecodeNop(MCInst *Inst, unsigned Val,
|
|
uint64_t Address, void *Decoder)
|
|
{
|
|
MCOperand_CreateImm0(Inst, Val + 1);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
#define GET_INSTRINFO_ENUM
|
|
#include "TMS320C64xGenInstrInfo.inc"
|
|
|
|
bool TMS320C64x_getInstruction(csh ud, const uint8_t *code, size_t code_len,
|
|
MCInst *MI, uint16_t *size, uint64_t address, void *info)
|
|
{
|
|
uint32_t insn;
|
|
DecodeStatus result;
|
|
|
|
if(code_len < 4) {
|
|
*size = 0;
|
|
return MCDisassembler_Fail;
|
|
}
|
|
|
|
if(MI->flat_insn->detail)
|
|
memset(MI->flat_insn->detail, 0, offsetof(cs_detail, tms320c64x)+sizeof(cs_tms320c64x));
|
|
|
|
insn = readBytes32(MI, code);
|
|
result = decodeInstruction_4(DecoderTable32, MI, insn, address, info, 0);
|
|
|
|
if(result == MCDisassembler_Success) {
|
|
*size = 4;
|
|
return true;
|
|
}
|
|
|
|
MCInst_clear(MI);
|
|
*size = 0;
|
|
return false;
|
|
}
|
|
|
|
void TMS320C64x_init(MCRegisterInfo *MRI)
|
|
{
|
|
MCRegisterInfo_InitMCRegisterInfo(MRI, TMS320C64xRegDesc, 90,
|
|
0, 0,
|
|
TMS320C64xMCRegisterClasses, 7,
|
|
0, 0,
|
|
TMS320C64xRegDiffLists,
|
|
0,
|
|
TMS320C64xSubRegIdxLists, 1,
|
|
0);
|
|
}
|
|
|
|
#endif
|