iris/kaizen
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
00cc9309cb3a9e41afe5def8dcb9bf5b089b9a21
kaizen/external/capstone/arch/Xtensa/XtensaInstPrinter.c
T
iris 00cc9309cb Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd 
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
2026-06-15 11:56:38 +02:00

701 lines
21 KiB
C
Raw Blame History

/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===- XtensaInstPrinter.cpp - Convert Xtensa MCInst to asm syntax --------===//
//
// The LLVM Compiler Infrastructure
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an Xtensa MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInstPrinter.h"
#include "../../SStream.h"
#include "./priv.h"
#include "../../Mapping.h"
#include "XtensaMapping.h"
#include "../../MathExtras.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "asm-printer"
static MnemonicBitsInfo getMnemonic(MCInst *MI, SStream *O);
static const char *getRegisterName(unsigned RegNo);
typedef MCRegister Register;
static void printRegName(SStream *O, MCRegister Reg)
{
SStream_concat0(O, getRegisterName(Reg));
}
static void printOp(MCInst *MI, MCOperand *MC, SStream *O)
{
if (MCOperand_isReg(MC))
SStream_concat0(O, getRegisterName(MCOperand_getReg(MC)));
else if (MCOperand_isImm(MC))
printInt64(O, MCOperand_getImm(MC));
else if (MCOperand_isExpr(MC))
printExpr(MCOperand_getExpr(MC), O);
else
CS_ASSERT("Invalid operand");
}
static void printOperand(MCInst *MI, const int op_num, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Operand, op_num);
printOp(MI, MCInst_getOperand(MI, op_num), O);
}
static inline void printMemOperand(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_MemOperand, OpNum);
SStream_concat0(OS, getRegisterName(MCOperand_getReg(
MCInst_getOperand(MI, (OpNum)))));
SStream_concat0(OS, ", ");
printOp(MI, MCInst_getOperand(MI, OpNum + 1), OS);
}
static inline void printBranchTarget(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_BranchTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printLoopTarget(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_LoopTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printJumpTarget(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_JumpTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
;
}
static inline void printCallOperand(MCInst *MI, int OpNum, SStream *OS)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_CallOperand, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
int64_t Val = MCOperand_getImm(MC) + 4;
SStream_concat0(OS, ". ");
if (Val > 0)
SStream_concat0(OS, "+");
printInt64(OS, Val);
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printL32RTarget(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_L32RTarget, OpNum);
MCOperand *MC = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MC)) {
SStream_concat0(O, ". ");
printInt64(O, Xtensa_L32R_Value(MI, OpNum));
} else if (MCOperand_isExpr(MC))
CS_ASSERT_RET(0 && "unimplemented expr printing");
else
CS_ASSERT(0 && "Invalid operand");
}
static inline void printImm8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
isIntN(8, Value) &&
"Invalid argument, value must be in ranges [-128,127]");
printInt64(O, Value);
} else {
printOperand(MI, OpNum, O);
}
}
static inline void printImm8_sh8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8_sh8_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(isIntN(16, Value) && ((Value & 0xFF) == 0)) &&
"Invalid argument, value must be multiples of 256 in range "
"[-32768,32512]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm12_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -2048 && Value <= 2047) &&
"Invalid argument, value must be in ranges [-2048,2047]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm12m_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm12m_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -2048 && Value <= 2047) &&
"Invalid argument, value must be in ranges [-2048,2047]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printUimm4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm4_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 15) && "Invalid argument");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printUimm5_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Uimm5_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 31) && "Invalid argument");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printShimm1_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm1_31_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 1 && Value <= 31) &&
"Invalid argument, value must be in range [1,31]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printShimm0_31_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Shimm0_31_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 31) &&
"Invalid argument, value must be in range [0,31]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm1_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1_16_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 1 && Value <= 16) &&
"Invalid argument, value must be in range [1,16]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm1n_15_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm1n_15_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -1 && (Value != 0) && Value <= 15) &&
"Invalid argument, value must be in ranges <-1,-1> or <1,15>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm32n_95_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm32n_95_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= -32 && Value <= 95) &&
"Invalid argument, value must be in ranges <-32,95>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm8n_7_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm8n_7_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= -8 && Value <= 7) &&
"Invalid argument, value must be in ranges <-8,7>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm64n_4n_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm64n_4n_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= -64 && Value <= -4) &
((Value & 0x3) == 0) &&
"Invalid argument, value must be in ranges <-64,-4>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset8m32_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset8m32_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= 0 && Value <= 1020 && ((Value & 0x3) == 0)) &&
"Invalid argument, value must be multiples of four in range [0,1020]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printEntry_Imm12_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Entry_Imm12_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= 0 && Value <= 32760) &&
"Invalid argument, value must be multiples of eight in range "
"<0,32760>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printB4const_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4const_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
switch (Value) {
case -1:
case 1:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 10:
case 12:
case 16:
case 32:
case 64:
case 128:
case 256:
break;
default:
CS_ASSERT((0) && "Invalid B4const argument");
}
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printB4constu_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_B4constu_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
switch (Value) {
case 32768:
case 65536:
case 2:
case 3:
case 4:
case 5:
case 6:
case 7:
case 8:
case 10:
case 12:
case 16:
case 32:
case 64:
case 128:
case 256:
break;
default:
CS_ASSERT((0) && "Invalid B4constu argument");
}
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printImm7_22_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Imm7_22_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 7 && Value <= 22) &&
"Invalid argument, value must be in range <7,22>");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_2_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_2_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 1) &&
"Invalid argument, value must be in range [0,1]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_4_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_4_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 3) &&
"Invalid argument, value must be in range [0,3]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_8_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_8_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 7) &&
"Invalid argument, value must be in range [0,7]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_16_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_16_AsmOperand, OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 15) &&
"Invalid argument, value must be in range [0,15]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printSelect_256_AsmOperand(MCInst *MI, int OpNum, SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Select_256_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 255) &&
"Invalid argument, value must be in range [0,255]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_16_16_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_16_16_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -128 && Value <= 112 && (Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-128,112], first 4 bits "
"should be zero");
printInt64(O, Value);
} else {
printOperand(MI, OpNum, O);
}
}
static inline void printOffset_256_8_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_8_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -1024 && Value <= 1016 &&
(Value & 0x7) == 0) &&
"Invalid argument, value must be in range [-1024,1016], first 3 "
"bits should be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_256_16_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_16_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -2048 && Value <= 2032 &&
(Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-2048,2032], first 4 "
"bits should be zero");
printInt64(O, Value);
} else {
printOperand(MI, OpNum, O);
}
}
static inline void printOffset_256_4_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_256_4_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -512 && Value <= 508 && (Value & 0x3) == 0) &&
"Invalid argument, value must be in range [-512,508], first 2 bits "
"should be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_128_2_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_2_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= 0 && Value <= 254 && (Value & 0x1) == 0) &&
"Invalid argument, value must be in range [0,254], first bit should "
"be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_128_1_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_128_1_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT((Value >= 0 && Value <= 127) &&
"Invalid argument, value must be in range [0,127]");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
static inline void printOffset_64_16_AsmOperand(MCInst *MI, int OpNum,
SStream *O)
{
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_Offset_64_16_AsmOperand,
OpNum);
if (MCOperand_isImm(MCInst_getOperand(MI, (OpNum)))) {
int64_t Value =
MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
CS_ASSERT(
(Value >= -512 && Value <= 496 && (Value & 0xf) == 0) &&
"Invalid argument, value must be in range [-512,496], first 4 bits "
"should be zero");
printInt64(O, Value);
} else
printOperand(MI, OpNum, O);
}
#define IMPL_printImmOperand(N, L, H, S) \
static void printImmOperand_##N(MCInst *MI, int OpNum, SStream *O) \
{ \
Xtensa_add_cs_detail_0(MI, Xtensa_OP_GROUP_ImmOperand_##N, \
OpNum); \
MCOperand *MC = MCInst_getOperand(MI, (OpNum)); \
if (MCOperand_isImm(MC)) { \
int64_t Value = MCOperand_getImm(MC); \
CS_ASSERT((Value >= L && Value <= H && \
((Value % S) == 0)) && \
"Invalid argument"); \
printInt64(O, Value); \
} else { \
printOperand(MI, OpNum, O); \
} \
}
IMPL_printImmOperand(minus64_56_8, -64, 56, 8);
IMPL_printImmOperand(minus32_28_4, -32, 28, 4);
IMPL_printImmOperand(minus16_47_1, -16, 47, 1);
IMPL_printImmOperand(minus16_14_2, -16, 14, 2);
IMPL_printImmOperand(0_56_8, 0, 56, 8);
IMPL_printImmOperand(0_3_1, 0, 3, 1);
IMPL_printImmOperand(0_63_1, 0, 63, 1);
#include "XtensaGenAsmWriter.inc"
static void printInst(MCInst *MI, uint64_t Address, const char *Annot,
SStream *O)
{
unsigned Opcode = MCInst_getOpcode(MI);
switch (Opcode) {
case Xtensa_WSR: {
// INTERRUPT mnemonic is read-only, so use INTSET mnemonic instead
Register SR = MCOperand_getReg(MCInst_getOperand(MI, (0)));
if (SR == Xtensa_INTERRUPT) {
Register Reg =
MCOperand_getReg(MCInst_getOperand(MI, (1)));
SStream_concat1(O, '\t');
SStream_concat(O, "%s", "wsr");
SStream_concat0(O, "\t");
printRegName(O, Reg);
SStream_concat(O, "%s", ", ");
SStream_concat0(O, "intset");
;
return;
}
}
}
printInstruction(MI, Address, O);
}
void Xtensa_LLVM_printInstruction(MCInst *MI, uint64_t Address, SStream *O)
{
printInst(MI, Address, NULL, O);
}
const char *Xtensa_LLVM_getRegisterName(unsigned RegNo)
{
return getRegisterName(RegNo);
}
Reference in New Issue View Git Blame Copy Permalink