00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
2183 lines
64 KiB
OCaml
2183 lines
64 KiB
OCaml
(* For Capstone Engine. AUTO-GENERATED FILE, DO NOT EDIT [mips_const.ml] *)
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let _MIPS_OP_INVALID = _CS_OP_INVALID;;
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let _MIPS_OP_REG = _CS_OP_REG;;
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let _MIPS_OP_IMM = _CS_OP_IMM;;
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let _MIPS_OP_MEM = _CS_OP_MEM;;
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let _MIPS_REG_INVALID = 0;;
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let _MIPS_REG_AT = 1;;
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let _MIPS_REG_AT_NM = 2;;
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let _MIPS_REG_DSPCCOND = 3;;
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let _MIPS_REG_DSPCARRY = 4;;
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let _MIPS_REG_DSPEFI = 5;;
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let _MIPS_REG_DSPOUTFLAG = 6;;
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let _MIPS_REG_DSPPOS = 7;;
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let _MIPS_REG_DSPSCOUNT = 8;;
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let _MIPS_REG_FP = 9;;
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let _MIPS_REG_FP_NM = 10;;
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let _MIPS_REG_GP = 11;;
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let _MIPS_REG_GP_NM = 12;;
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let _MIPS_REG_MSAACCESS = 13;;
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let _MIPS_REG_MSACSR = 14;;
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let _MIPS_REG_MSAIR = 15;;
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let _MIPS_REG_MSAMAP = 16;;
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let _MIPS_REG_MSAMODIFY = 17;;
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let _MIPS_REG_MSAREQUEST = 18;;
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let _MIPS_REG_MSASAVE = 19;;
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let _MIPS_REG_MSAUNMAP = 20;;
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let _MIPS_REG_PC = 21;;
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let _MIPS_REG_RA = 22;;
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let _MIPS_REG_RA_NM = 23;;
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let _MIPS_REG_SP = 24;;
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let _MIPS_REG_SP_NM = 25;;
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let _MIPS_REG_ZERO = 26;;
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let _MIPS_REG_ZERO_NM = 27;;
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let _MIPS_REG_A0 = 28;;
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let _MIPS_REG_A1 = 29;;
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let _MIPS_REG_A2 = 30;;
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let _MIPS_REG_A3 = 31;;
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let _MIPS_REG_AC0 = 32;;
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let _MIPS_REG_AC1 = 33;;
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let _MIPS_REG_AC2 = 34;;
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let _MIPS_REG_AC3 = 35;;
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let _MIPS_REG_AT_64 = 36;;
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let _MIPS_REG_COP00 = 37;;
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let _MIPS_REG_COP01 = 38;;
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let _MIPS_REG_COP02 = 39;;
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let _MIPS_REG_COP03 = 40;;
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let _MIPS_REG_COP04 = 41;;
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let _MIPS_REG_COP05 = 42;;
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let _MIPS_REG_COP06 = 43;;
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let _MIPS_REG_COP07 = 44;;
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let _MIPS_REG_COP08 = 45;;
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let _MIPS_REG_COP09 = 46;;
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let _MIPS_REG_COP20 = 47;;
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let _MIPS_REG_COP21 = 48;;
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let _MIPS_REG_COP22 = 49;;
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let _MIPS_REG_COP23 = 50;;
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let _MIPS_REG_COP24 = 51;;
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let _MIPS_REG_COP25 = 52;;
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let _MIPS_REG_COP26 = 53;;
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let _MIPS_REG_COP27 = 54;;
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let _MIPS_REG_COP28 = 55;;
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let _MIPS_REG_COP29 = 56;;
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let _MIPS_REG_COP30 = 57;;
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let _MIPS_REG_COP31 = 58;;
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let _MIPS_REG_COP32 = 59;;
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let _MIPS_REG_COP33 = 60;;
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let _MIPS_REG_COP34 = 61;;
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let _MIPS_REG_COP35 = 62;;
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let _MIPS_REG_COP36 = 63;;
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let _MIPS_REG_COP37 = 64;;
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let _MIPS_REG_COP38 = 65;;
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let _MIPS_REG_COP39 = 66;;
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let _MIPS_REG_COP010 = 67;;
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let _MIPS_REG_COP011 = 68;;
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let _MIPS_REG_COP012 = 69;;
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let _MIPS_REG_COP013 = 70;;
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let _MIPS_REG_COP014 = 71;;
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let _MIPS_REG_COP015 = 72;;
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let _MIPS_REG_COP016 = 73;;
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let _MIPS_REG_COP017 = 74;;
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let _MIPS_REG_COP018 = 75;;
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let _MIPS_REG_COP019 = 76;;
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let _MIPS_REG_COP020 = 77;;
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let _MIPS_REG_COP021 = 78;;
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let _MIPS_REG_COP022 = 79;;
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let _MIPS_REG_COP023 = 80;;
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let _MIPS_REG_COP024 = 81;;
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let _MIPS_REG_COP025 = 82;;
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let _MIPS_REG_COP026 = 83;;
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let _MIPS_REG_COP027 = 84;;
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let _MIPS_REG_COP028 = 85;;
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let _MIPS_REG_COP029 = 86;;
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let _MIPS_REG_COP030 = 87;;
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let _MIPS_REG_COP031 = 88;;
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let _MIPS_REG_COP210 = 89;;
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let _MIPS_REG_COP211 = 90;;
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let _MIPS_REG_COP212 = 91;;
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let _MIPS_REG_COP213 = 92;;
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let _MIPS_REG_COP214 = 93;;
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let _MIPS_REG_COP215 = 94;;
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let _MIPS_REG_COP216 = 95;;
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let _MIPS_REG_COP217 = 96;;
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let _MIPS_REG_COP218 = 97;;
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let _MIPS_REG_COP219 = 98;;
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let _MIPS_REG_COP220 = 99;;
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let _MIPS_REG_COP221 = 100;;
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let _MIPS_REG_COP222 = 101;;
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let _MIPS_REG_COP223 = 102;;
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let _MIPS_REG_COP224 = 103;;
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let _MIPS_REG_COP225 = 104;;
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let _MIPS_REG_COP226 = 105;;
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let _MIPS_REG_COP227 = 106;;
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let _MIPS_REG_COP228 = 107;;
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let _MIPS_REG_COP229 = 108;;
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let _MIPS_REG_COP230 = 109;;
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let _MIPS_REG_COP231 = 110;;
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let _MIPS_REG_COP310 = 111;;
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let _MIPS_REG_COP311 = 112;;
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let _MIPS_REG_COP312 = 113;;
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let _MIPS_REG_COP313 = 114;;
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let _MIPS_REG_COP314 = 115;;
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let _MIPS_REG_COP315 = 116;;
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let _MIPS_REG_COP316 = 117;;
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let _MIPS_REG_COP317 = 118;;
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let _MIPS_REG_COP318 = 119;;
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let _MIPS_REG_COP319 = 120;;
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let _MIPS_REG_COP320 = 121;;
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let _MIPS_REG_COP321 = 122;;
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let _MIPS_REG_COP322 = 123;;
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let _MIPS_REG_COP323 = 124;;
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let _MIPS_REG_COP324 = 125;;
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let _MIPS_REG_COP325 = 126;;
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let _MIPS_REG_COP326 = 127;;
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let _MIPS_REG_COP327 = 128;;
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let _MIPS_REG_COP328 = 129;;
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let _MIPS_REG_COP329 = 130;;
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let _MIPS_REG_COP330 = 131;;
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let _MIPS_REG_COP331 = 132;;
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let _MIPS_REG_D0 = 133;;
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let _MIPS_REG_D1 = 134;;
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let _MIPS_REG_D2 = 135;;
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let _MIPS_REG_D3 = 136;;
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let _MIPS_REG_D4 = 137;;
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let _MIPS_REG_D5 = 138;;
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let _MIPS_REG_D6 = 139;;
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let _MIPS_REG_D7 = 140;;
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let _MIPS_REG_D8 = 141;;
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let _MIPS_REG_D9 = 142;;
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let _MIPS_REG_D10 = 143;;
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let _MIPS_REG_D11 = 144;;
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let _MIPS_REG_D12 = 145;;
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let _MIPS_REG_D13 = 146;;
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let _MIPS_REG_D14 = 147;;
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let _MIPS_REG_D15 = 148;;
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let _MIPS_REG_DSPOUTFLAG20 = 149;;
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let _MIPS_REG_DSPOUTFLAG21 = 150;;
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let _MIPS_REG_DSPOUTFLAG22 = 151;;
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let _MIPS_REG_DSPOUTFLAG23 = 152;;
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let _MIPS_REG_F0 = 153;;
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let _MIPS_REG_F1 = 154;;
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let _MIPS_REG_F2 = 155;;
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let _MIPS_REG_F3 = 156;;
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let _MIPS_REG_F4 = 157;;
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let _MIPS_REG_F5 = 158;;
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let _MIPS_REG_F6 = 159;;
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let _MIPS_REG_F7 = 160;;
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let _MIPS_REG_F8 = 161;;
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let _MIPS_REG_F9 = 162;;
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let _MIPS_REG_F10 = 163;;
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let _MIPS_REG_F11 = 164;;
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let _MIPS_REG_F12 = 165;;
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let _MIPS_REG_F13 = 166;;
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let _MIPS_REG_F14 = 167;;
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let _MIPS_REG_F15 = 168;;
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let _MIPS_REG_F16 = 169;;
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let _MIPS_REG_F17 = 170;;
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let _MIPS_REG_F18 = 171;;
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let _MIPS_REG_F19 = 172;;
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let _MIPS_REG_F20 = 173;;
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let _MIPS_REG_F21 = 174;;
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let _MIPS_REG_F22 = 175;;
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let _MIPS_REG_F23 = 176;;
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let _MIPS_REG_F24 = 177;;
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let _MIPS_REG_F25 = 178;;
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let _MIPS_REG_F26 = 179;;
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let _MIPS_REG_F27 = 180;;
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let _MIPS_REG_F28 = 181;;
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let _MIPS_REG_F29 = 182;;
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let _MIPS_REG_F30 = 183;;
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let _MIPS_REG_F31 = 184;;
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let _MIPS_REG_FCC0 = 185;;
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let _MIPS_REG_FCC1 = 186;;
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let _MIPS_REG_FCC2 = 187;;
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let _MIPS_REG_FCC3 = 188;;
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let _MIPS_REG_FCC4 = 189;;
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let _MIPS_REG_FCC5 = 190;;
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let _MIPS_REG_FCC6 = 191;;
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let _MIPS_REG_FCC7 = 192;;
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let _MIPS_REG_FCR0 = 193;;
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let _MIPS_REG_FCR1 = 194;;
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let _MIPS_REG_FCR2 = 195;;
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let _MIPS_REG_FCR3 = 196;;
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let _MIPS_REG_FCR4 = 197;;
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let _MIPS_REG_FCR5 = 198;;
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let _MIPS_REG_FCR6 = 199;;
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let _MIPS_REG_FCR7 = 200;;
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let _MIPS_REG_FCR8 = 201;;
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let _MIPS_REG_FCR9 = 202;;
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let _MIPS_REG_FCR10 = 203;;
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let _MIPS_REG_FCR11 = 204;;
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let _MIPS_REG_FCR12 = 205;;
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let _MIPS_REG_FCR13 = 206;;
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let _MIPS_REG_FCR14 = 207;;
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let _MIPS_REG_FCR15 = 208;;
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let _MIPS_REG_FCR16 = 209;;
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let _MIPS_REG_FCR17 = 210;;
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let _MIPS_REG_FCR18 = 211;;
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let _MIPS_REG_FCR19 = 212;;
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let _MIPS_REG_FCR20 = 213;;
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let _MIPS_REG_FCR21 = 214;;
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let _MIPS_REG_FCR22 = 215;;
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let _MIPS_REG_FCR23 = 216;;
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let _MIPS_REG_FCR24 = 217;;
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let _MIPS_REG_FCR25 = 218;;
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let _MIPS_REG_FCR26 = 219;;
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let _MIPS_REG_FCR27 = 220;;
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let _MIPS_REG_FCR28 = 221;;
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let _MIPS_REG_FCR29 = 222;;
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let _MIPS_REG_FCR30 = 223;;
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let _MIPS_REG_FCR31 = 224;;
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let _MIPS_REG_FP_64 = 225;;
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let _MIPS_REG_F_HI0 = 226;;
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let _MIPS_REG_F_HI1 = 227;;
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let _MIPS_REG_F_HI2 = 228;;
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let _MIPS_REG_F_HI3 = 229;;
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let _MIPS_REG_F_HI4 = 230;;
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let _MIPS_REG_F_HI5 = 231;;
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let _MIPS_REG_F_HI6 = 232;;
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let _MIPS_REG_F_HI7 = 233;;
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let _MIPS_REG_F_HI8 = 234;;
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let _MIPS_REG_F_HI9 = 235;;
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let _MIPS_REG_F_HI10 = 236;;
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let _MIPS_REG_F_HI11 = 237;;
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let _MIPS_REG_F_HI12 = 238;;
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let _MIPS_REG_F_HI13 = 239;;
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let _MIPS_REG_F_HI14 = 240;;
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let _MIPS_REG_F_HI15 = 241;;
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let _MIPS_REG_F_HI16 = 242;;
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let _MIPS_REG_F_HI17 = 243;;
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let _MIPS_REG_F_HI18 = 244;;
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let _MIPS_REG_F_HI19 = 245;;
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let _MIPS_REG_F_HI20 = 246;;
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let _MIPS_REG_F_HI21 = 247;;
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let _MIPS_REG_F_HI22 = 248;;
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let _MIPS_REG_F_HI23 = 249;;
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let _MIPS_REG_F_HI24 = 250;;
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let _MIPS_REG_F_HI25 = 251;;
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let _MIPS_REG_F_HI26 = 252;;
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let _MIPS_REG_F_HI27 = 253;;
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let _MIPS_REG_F_HI28 = 254;;
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let _MIPS_REG_F_HI29 = 255;;
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let _MIPS_REG_F_HI30 = 256;;
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let _MIPS_REG_F_HI31 = 257;;
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let _MIPS_REG_GP_64 = 258;;
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let _MIPS_REG_HI0 = 259;;
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let _MIPS_REG_HI1 = 260;;
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let _MIPS_REG_HI2 = 261;;
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let _MIPS_REG_HI3 = 262;;
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let _MIPS_REG_HWR0 = 263;;
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let _MIPS_REG_HWR1 = 264;;
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let _MIPS_REG_HWR2 = 265;;
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let _MIPS_REG_HWR3 = 266;;
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let _MIPS_REG_HWR4 = 267;;
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let _MIPS_REG_HWR5 = 268;;
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let _MIPS_REG_HWR6 = 269;;
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let _MIPS_REG_HWR7 = 270;;
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let _MIPS_REG_HWR8 = 271;;
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let _MIPS_REG_HWR9 = 272;;
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let _MIPS_REG_HWR10 = 273;;
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let _MIPS_REG_HWR11 = 274;;
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let _MIPS_REG_HWR12 = 275;;
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let _MIPS_REG_HWR13 = 276;;
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let _MIPS_REG_HWR14 = 277;;
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let _MIPS_REG_HWR15 = 278;;
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let _MIPS_REG_HWR16 = 279;;
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let _MIPS_REG_HWR17 = 280;;
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let _MIPS_REG_HWR18 = 281;;
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let _MIPS_REG_HWR19 = 282;;
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let _MIPS_REG_HWR20 = 283;;
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let _MIPS_REG_HWR21 = 284;;
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let _MIPS_REG_HWR22 = 285;;
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let _MIPS_REG_HWR23 = 286;;
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let _MIPS_REG_HWR24 = 287;;
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let _MIPS_REG_HWR25 = 288;;
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let _MIPS_REG_HWR26 = 289;;
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let _MIPS_REG_HWR27 = 290;;
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let _MIPS_REG_HWR28 = 291;;
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let _MIPS_REG_HWR29 = 292;;
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let _MIPS_REG_HWR30 = 293;;
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let _MIPS_REG_HWR31 = 294;;
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let _MIPS_REG_K0 = 295;;
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let _MIPS_REG_K1 = 296;;
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let _MIPS_REG_LO0 = 297;;
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let _MIPS_REG_LO1 = 298;;
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let _MIPS_REG_LO2 = 299;;
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let _MIPS_REG_LO3 = 300;;
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let _MIPS_REG_MPL0 = 301;;
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let _MIPS_REG_MPL1 = 302;;
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let _MIPS_REG_MPL2 = 303;;
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let _MIPS_REG_MSA8 = 304;;
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let _MIPS_REG_MSA9 = 305;;
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let _MIPS_REG_MSA10 = 306;;
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let _MIPS_REG_MSA11 = 307;;
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let _MIPS_REG_MSA12 = 308;;
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let _MIPS_REG_MSA13 = 309;;
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let _MIPS_REG_MSA14 = 310;;
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let _MIPS_REG_MSA15 = 311;;
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let _MIPS_REG_MSA16 = 312;;
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let _MIPS_REG_MSA17 = 313;;
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let _MIPS_REG_MSA18 = 314;;
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let _MIPS_REG_MSA19 = 315;;
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let _MIPS_REG_MSA20 = 316;;
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let _MIPS_REG_MSA21 = 317;;
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let _MIPS_REG_MSA22 = 318;;
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let _MIPS_REG_MSA23 = 319;;
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let _MIPS_REG_MSA24 = 320;;
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let _MIPS_REG_MSA25 = 321;;
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let _MIPS_REG_MSA26 = 322;;
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let _MIPS_REG_MSA27 = 323;;
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let _MIPS_REG_MSA28 = 324;;
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let _MIPS_REG_MSA29 = 325;;
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let _MIPS_REG_MSA30 = 326;;
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let _MIPS_REG_MSA31 = 327;;
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let _MIPS_REG_P0 = 328;;
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let _MIPS_REG_P1 = 329;;
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let _MIPS_REG_P2 = 330;;
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let _MIPS_REG_RA_64 = 331;;
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let _MIPS_REG_S0 = 332;;
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let _MIPS_REG_S1 = 333;;
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let _MIPS_REG_S2 = 334;;
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let _MIPS_REG_S3 = 335;;
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let _MIPS_REG_S4 = 336;;
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let _MIPS_REG_S5 = 337;;
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let _MIPS_REG_S6 = 338;;
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let _MIPS_REG_S7 = 339;;
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let _MIPS_REG_SP_64 = 340;;
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let _MIPS_REG_T0 = 341;;
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let _MIPS_REG_T1 = 342;;
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let _MIPS_REG_T2 = 343;;
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let _MIPS_REG_T3 = 344;;
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let _MIPS_REG_T4 = 345;;
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let _MIPS_REG_T5 = 346;;
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let _MIPS_REG_T6 = 347;;
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let _MIPS_REG_T7 = 348;;
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|
let _MIPS_REG_T8 = 349;;
|
|
let _MIPS_REG_T9 = 350;;
|
|
let _MIPS_REG_V0 = 351;;
|
|
let _MIPS_REG_V1 = 352;;
|
|
let _MIPS_REG_W0 = 353;;
|
|
let _MIPS_REG_W1 = 354;;
|
|
let _MIPS_REG_W2 = 355;;
|
|
let _MIPS_REG_W3 = 356;;
|
|
let _MIPS_REG_W4 = 357;;
|
|
let _MIPS_REG_W5 = 358;;
|
|
let _MIPS_REG_W6 = 359;;
|
|
let _MIPS_REG_W7 = 360;;
|
|
let _MIPS_REG_W8 = 361;;
|
|
let _MIPS_REG_W9 = 362;;
|
|
let _MIPS_REG_W10 = 363;;
|
|
let _MIPS_REG_W11 = 364;;
|
|
let _MIPS_REG_W12 = 365;;
|
|
let _MIPS_REG_W13 = 366;;
|
|
let _MIPS_REG_W14 = 367;;
|
|
let _MIPS_REG_W15 = 368;;
|
|
let _MIPS_REG_W16 = 369;;
|
|
let _MIPS_REG_W17 = 370;;
|
|
let _MIPS_REG_W18 = 371;;
|
|
let _MIPS_REG_W19 = 372;;
|
|
let _MIPS_REG_W20 = 373;;
|
|
let _MIPS_REG_W21 = 374;;
|
|
let _MIPS_REG_W22 = 375;;
|
|
let _MIPS_REG_W23 = 376;;
|
|
let _MIPS_REG_W24 = 377;;
|
|
let _MIPS_REG_W25 = 378;;
|
|
let _MIPS_REG_W26 = 379;;
|
|
let _MIPS_REG_W27 = 380;;
|
|
let _MIPS_REG_W28 = 381;;
|
|
let _MIPS_REG_W29 = 382;;
|
|
let _MIPS_REG_W30 = 383;;
|
|
let _MIPS_REG_W31 = 384;;
|
|
let _MIPS_REG_ZERO_64 = 385;;
|
|
let _MIPS_REG_A0_NM = 386;;
|
|
let _MIPS_REG_A1_NM = 387;;
|
|
let _MIPS_REG_A2_NM = 388;;
|
|
let _MIPS_REG_A3_NM = 389;;
|
|
let _MIPS_REG_A4_NM = 390;;
|
|
let _MIPS_REG_A5_NM = 391;;
|
|
let _MIPS_REG_A6_NM = 392;;
|
|
let _MIPS_REG_A7_NM = 393;;
|
|
let _MIPS_REG_COP0SEL_BADINST = 394;;
|
|
let _MIPS_REG_COP0SEL_BADINSTRP = 395;;
|
|
let _MIPS_REG_COP0SEL_BADINSTRX = 396;;
|
|
let _MIPS_REG_COP0SEL_BADVADDR = 397;;
|
|
let _MIPS_REG_COP0SEL_BEVVA = 398;;
|
|
let _MIPS_REG_COP0SEL_CACHEERR = 399;;
|
|
let _MIPS_REG_COP0SEL_CAUSE = 400;;
|
|
let _MIPS_REG_COP0SEL_CDMMBASE = 401;;
|
|
let _MIPS_REG_COP0SEL_CMGCRBASE = 402;;
|
|
let _MIPS_REG_COP0SEL_COMPARE = 403;;
|
|
let _MIPS_REG_COP0SEL_CONFIG = 404;;
|
|
let _MIPS_REG_COP0SEL_CONTEXT = 405;;
|
|
let _MIPS_REG_COP0SEL_CONTEXTCONFIG = 406;;
|
|
let _MIPS_REG_COP0SEL_COUNT = 407;;
|
|
let _MIPS_REG_COP0SEL_DDATAHI = 408;;
|
|
let _MIPS_REG_COP0SEL_DDATALO = 409;;
|
|
let _MIPS_REG_COP0SEL_DEBUG = 410;;
|
|
let _MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411;;
|
|
let _MIPS_REG_COP0SEL_DEPC = 412;;
|
|
let _MIPS_REG_COP0SEL_DESAVE = 413;;
|
|
let _MIPS_REG_COP0SEL_DTAGHI = 414;;
|
|
let _MIPS_REG_COP0SEL_DTAGLO = 415;;
|
|
let _MIPS_REG_COP0SEL_EBASE = 416;;
|
|
let _MIPS_REG_COP0SEL_ENTRYHI = 417;;
|
|
let _MIPS_REG_COP0SEL_EPC = 418;;
|
|
let _MIPS_REG_COP0SEL_ERRCTL = 419;;
|
|
let _MIPS_REG_COP0SEL_ERROREPC = 420;;
|
|
let _MIPS_REG_COP0SEL_GLOBALNUMBER = 421;;
|
|
let _MIPS_REG_COP0SEL_GTOFFSET = 422;;
|
|
let _MIPS_REG_COP0SEL_HWRENA = 423;;
|
|
let _MIPS_REG_COP0SEL_IDATAHI = 424;;
|
|
let _MIPS_REG_COP0SEL_IDATALO = 425;;
|
|
let _MIPS_REG_COP0SEL_INDEX = 426;;
|
|
let _MIPS_REG_COP0SEL_INTCTL = 427;;
|
|
let _MIPS_REG_COP0SEL_ITAGHI = 428;;
|
|
let _MIPS_REG_COP0SEL_ITAGLO = 429;;
|
|
let _MIPS_REG_COP0SEL_LLADDR = 430;;
|
|
let _MIPS_REG_COP0SEL_MAAR = 431;;
|
|
let _MIPS_REG_COP0SEL_MAARI = 432;;
|
|
let _MIPS_REG_COP0SEL_MEMORYMAPID = 433;;
|
|
let _MIPS_REG_COP0SEL_MVPCONTROL = 434;;
|
|
let _MIPS_REG_COP0SEL_NESTEDEPC = 435;;
|
|
let _MIPS_REG_COP0SEL_NESTEDEXC = 436;;
|
|
let _MIPS_REG_COP0SEL_PAGEGRAIN = 437;;
|
|
let _MIPS_REG_COP0SEL_PAGEMASK = 438;;
|
|
let _MIPS_REG_COP0SEL_PRID = 439;;
|
|
let _MIPS_REG_COP0SEL_PWBASE = 440;;
|
|
let _MIPS_REG_COP0SEL_PWCTL = 441;;
|
|
let _MIPS_REG_COP0SEL_PWFIELD = 442;;
|
|
let _MIPS_REG_COP0SEL_PWSIZE = 443;;
|
|
let _MIPS_REG_COP0SEL_RANDOM = 444;;
|
|
let _MIPS_REG_COP0SEL_SRSCTL = 445;;
|
|
let _MIPS_REG_COP0SEL_SRSMAP = 446;;
|
|
let _MIPS_REG_COP0SEL_STATUS = 447;;
|
|
let _MIPS_REG_COP0SEL_TCBIND = 448;;
|
|
let _MIPS_REG_COP0SEL_TCCONTEXT = 449;;
|
|
let _MIPS_REG_COP0SEL_TCHALT = 450;;
|
|
let _MIPS_REG_COP0SEL_TCOPT = 451;;
|
|
let _MIPS_REG_COP0SEL_TCRESTART = 452;;
|
|
let _MIPS_REG_COP0SEL_TCSCHEDULE = 453;;
|
|
let _MIPS_REG_COP0SEL_TCSCHEFBACK = 454;;
|
|
let _MIPS_REG_COP0SEL_TCSTATUS = 455;;
|
|
let _MIPS_REG_COP0SEL_TRACECONTROL = 456;;
|
|
let _MIPS_REG_COP0SEL_TRACEDBPC = 457;;
|
|
let _MIPS_REG_COP0SEL_TRACEIBPC = 458;;
|
|
let _MIPS_REG_COP0SEL_USERLOCAL = 459;;
|
|
let _MIPS_REG_COP0SEL_VIEW_IPL = 460;;
|
|
let _MIPS_REG_COP0SEL_VIEW_RIPL = 461;;
|
|
let _MIPS_REG_COP0SEL_VPCONTROL = 462;;
|
|
let _MIPS_REG_COP0SEL_VPECONTROL = 463;;
|
|
let _MIPS_REG_COP0SEL_VPEOPT = 464;;
|
|
let _MIPS_REG_COP0SEL_VPESCHEDULE = 465;;
|
|
let _MIPS_REG_COP0SEL_VPESCHEFBACK = 466;;
|
|
let _MIPS_REG_COP0SEL_WIRED = 467;;
|
|
let _MIPS_REG_COP0SEL_XCONTEXT = 468;;
|
|
let _MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469;;
|
|
let _MIPS_REG_COP0SEL_YQMASK = 470;;
|
|
let _MIPS_REG_K0_NM = 471;;
|
|
let _MIPS_REG_K1_NM = 472;;
|
|
let _MIPS_REG_S0_NM = 473;;
|
|
let _MIPS_REG_S1_NM = 474;;
|
|
let _MIPS_REG_S2_NM = 475;;
|
|
let _MIPS_REG_S3_NM = 476;;
|
|
let _MIPS_REG_S4_NM = 477;;
|
|
let _MIPS_REG_S5_NM = 478;;
|
|
let _MIPS_REG_S6_NM = 479;;
|
|
let _MIPS_REG_S7_NM = 480;;
|
|
let _MIPS_REG_T0_NM = 481;;
|
|
let _MIPS_REG_T1_NM = 482;;
|
|
let _MIPS_REG_T2_NM = 483;;
|
|
let _MIPS_REG_T3_NM = 484;;
|
|
let _MIPS_REG_T4_NM = 485;;
|
|
let _MIPS_REG_T5_NM = 486;;
|
|
let _MIPS_REG_T8_NM = 487;;
|
|
let _MIPS_REG_T9_NM = 488;;
|
|
let _MIPS_REG_A0_64 = 489;;
|
|
let _MIPS_REG_A1_64 = 490;;
|
|
let _MIPS_REG_A2_64 = 491;;
|
|
let _MIPS_REG_A3_64 = 492;;
|
|
let _MIPS_REG_AC0_64 = 493;;
|
|
let _MIPS_REG_COP0SEL_CONFIG1 = 494;;
|
|
let _MIPS_REG_COP0SEL_CONFIG2 = 495;;
|
|
let _MIPS_REG_COP0SEL_CONFIG3 = 496;;
|
|
let _MIPS_REG_COP0SEL_CONFIG4 = 497;;
|
|
let _MIPS_REG_COP0SEL_CONFIG5 = 498;;
|
|
let _MIPS_REG_COP0SEL_DEBUG2 = 499;;
|
|
let _MIPS_REG_COP0SEL_ENTRYLO0 = 500;;
|
|
let _MIPS_REG_COP0SEL_ENTRYLO1 = 501;;
|
|
let _MIPS_REG_COP0SEL_GUESTCTL0 = 502;;
|
|
let _MIPS_REG_COP0SEL_GUESTCTL1 = 503;;
|
|
let _MIPS_REG_COP0SEL_GUESTCTL2 = 504;;
|
|
let _MIPS_REG_COP0SEL_GUESTCTL3 = 505;;
|
|
let _MIPS_REG_COP0SEL_KSCRATCH1 = 506;;
|
|
let _MIPS_REG_COP0SEL_KSCRATCH2 = 507;;
|
|
let _MIPS_REG_COP0SEL_KSCRATCH3 = 508;;
|
|
let _MIPS_REG_COP0SEL_KSCRATCH4 = 509;;
|
|
let _MIPS_REG_COP0SEL_KSCRATCH5 = 510;;
|
|
let _MIPS_REG_COP0SEL_KSCRATCH6 = 511;;
|
|
let _MIPS_REG_COP0SEL_MVPCONF0 = 512;;
|
|
let _MIPS_REG_COP0SEL_MVPCONF1 = 513;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT0 = 514;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT1 = 515;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT2 = 516;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT3 = 517;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT4 = 518;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT5 = 519;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT6 = 520;;
|
|
let _MIPS_REG_COP0SEL_PERFCNT7 = 521;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL0 = 522;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL1 = 523;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL2 = 524;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL3 = 525;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL4 = 526;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL5 = 527;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL6 = 528;;
|
|
let _MIPS_REG_COP0SEL_PERFCTL7 = 529;;
|
|
let _MIPS_REG_COP0SEL_SEGCTL0 = 530;;
|
|
let _MIPS_REG_COP0SEL_SEGCTL1 = 531;;
|
|
let _MIPS_REG_COP0SEL_SEGCTL2 = 532;;
|
|
let _MIPS_REG_COP0SEL_SRSCONF0 = 533;;
|
|
let _MIPS_REG_COP0SEL_SRSCONF1 = 534;;
|
|
let _MIPS_REG_COP0SEL_SRSCONF2 = 535;;
|
|
let _MIPS_REG_COP0SEL_SRSCONF3 = 536;;
|
|
let _MIPS_REG_COP0SEL_SRSCONF4 = 537;;
|
|
let _MIPS_REG_COP0SEL_SRSMAP2 = 538;;
|
|
let _MIPS_REG_COP0SEL_TRACECONTROL2 = 539;;
|
|
let _MIPS_REG_COP0SEL_TRACECONTROL3 = 540;;
|
|
let _MIPS_REG_COP0SEL_USERTRACEDATA1 = 541;;
|
|
let _MIPS_REG_COP0SEL_USERTRACEDATA2 = 542;;
|
|
let _MIPS_REG_COP0SEL_VPECONF0 = 543;;
|
|
let _MIPS_REG_COP0SEL_VPECONF1 = 544;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI0 = 545;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI1 = 546;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI2 = 547;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI3 = 548;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI4 = 549;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI5 = 550;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI6 = 551;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI7 = 552;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI8 = 553;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI9 = 554;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI10 = 555;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI11 = 556;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI12 = 557;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI13 = 558;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI14 = 559;;
|
|
let _MIPS_REG_COP0SEL_WATCHHI15 = 560;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO0 = 561;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO1 = 562;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO2 = 563;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO3 = 564;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO4 = 565;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO5 = 566;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO6 = 567;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO7 = 568;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO8 = 569;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO9 = 570;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO10 = 571;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO11 = 572;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO12 = 573;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO13 = 574;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO14 = 575;;
|
|
let _MIPS_REG_COP0SEL_WATCHLO15 = 576;;
|
|
let _MIPS_REG_D0_64 = 577;;
|
|
let _MIPS_REG_D1_64 = 578;;
|
|
let _MIPS_REG_D2_64 = 579;;
|
|
let _MIPS_REG_D3_64 = 580;;
|
|
let _MIPS_REG_D4_64 = 581;;
|
|
let _MIPS_REG_D5_64 = 582;;
|
|
let _MIPS_REG_D6_64 = 583;;
|
|
let _MIPS_REG_D7_64 = 584;;
|
|
let _MIPS_REG_D8_64 = 585;;
|
|
let _MIPS_REG_D9_64 = 586;;
|
|
let _MIPS_REG_D10_64 = 587;;
|
|
let _MIPS_REG_D11_64 = 588;;
|
|
let _MIPS_REG_D12_64 = 589;;
|
|
let _MIPS_REG_D13_64 = 590;;
|
|
let _MIPS_REG_D14_64 = 591;;
|
|
let _MIPS_REG_D15_64 = 592;;
|
|
let _MIPS_REG_D16_64 = 593;;
|
|
let _MIPS_REG_D17_64 = 594;;
|
|
let _MIPS_REG_D18_64 = 595;;
|
|
let _MIPS_REG_D19_64 = 596;;
|
|
let _MIPS_REG_D20_64 = 597;;
|
|
let _MIPS_REG_D21_64 = 598;;
|
|
let _MIPS_REG_D22_64 = 599;;
|
|
let _MIPS_REG_D23_64 = 600;;
|
|
let _MIPS_REG_D24_64 = 601;;
|
|
let _MIPS_REG_D25_64 = 602;;
|
|
let _MIPS_REG_D26_64 = 603;;
|
|
let _MIPS_REG_D27_64 = 604;;
|
|
let _MIPS_REG_D28_64 = 605;;
|
|
let _MIPS_REG_D29_64 = 606;;
|
|
let _MIPS_REG_D30_64 = 607;;
|
|
let _MIPS_REG_D31_64 = 608;;
|
|
let _MIPS_REG_DSPOUTFLAG16_19 = 609;;
|
|
let _MIPS_REG_HI0_64 = 610;;
|
|
let _MIPS_REG_K0_64 = 611;;
|
|
let _MIPS_REG_K1_64 = 612;;
|
|
let _MIPS_REG_LO0_64 = 613;;
|
|
let _MIPS_REG_S0_64 = 614;;
|
|
let _MIPS_REG_S1_64 = 615;;
|
|
let _MIPS_REG_S2_64 = 616;;
|
|
let _MIPS_REG_S3_64 = 617;;
|
|
let _MIPS_REG_S4_64 = 618;;
|
|
let _MIPS_REG_S5_64 = 619;;
|
|
let _MIPS_REG_S6_64 = 620;;
|
|
let _MIPS_REG_S7_64 = 621;;
|
|
let _MIPS_REG_T0_64 = 622;;
|
|
let _MIPS_REG_T1_64 = 623;;
|
|
let _MIPS_REG_T2_64 = 624;;
|
|
let _MIPS_REG_T3_64 = 625;;
|
|
let _MIPS_REG_T4_64 = 626;;
|
|
let _MIPS_REG_T5_64 = 627;;
|
|
let _MIPS_REG_T6_64 = 628;;
|
|
let _MIPS_REG_T7_64 = 629;;
|
|
let _MIPS_REG_T8_64 = 630;;
|
|
let _MIPS_REG_T9_64 = 631;;
|
|
let _MIPS_REG_V0_64 = 632;;
|
|
let _MIPS_REG_V1_64 = 633;;
|
|
let _MIPS_REG_COP0SEL_GUESTCTL0EXT = 634;;
|
|
let _MIPS_REG_ENDING = 635;;
|
|
|
|
let _MIPS_INS_INVALID = 0;;
|
|
let _MIPS_INS_ABS = 1;;
|
|
let _MIPS_INS_ALIGN = 2;;
|
|
let _MIPS_INS_BEQL = 3;;
|
|
let _MIPS_INS_BGE = 4;;
|
|
let _MIPS_INS_BGEL = 5;;
|
|
let _MIPS_INS_BGEU = 6;;
|
|
let _MIPS_INS_BGEUL = 7;;
|
|
let _MIPS_INS_BGT = 8;;
|
|
let _MIPS_INS_BGTL = 9;;
|
|
let _MIPS_INS_BGTU = 10;;
|
|
let _MIPS_INS_BGTUL = 11;;
|
|
let _MIPS_INS_BLE = 12;;
|
|
let _MIPS_INS_BLEL = 13;;
|
|
let _MIPS_INS_BLEU = 14;;
|
|
let _MIPS_INS_BLEUL = 15;;
|
|
let _MIPS_INS_BLT = 16;;
|
|
let _MIPS_INS_BLTL = 17;;
|
|
let _MIPS_INS_BLTU = 18;;
|
|
let _MIPS_INS_BLTUL = 19;;
|
|
let _MIPS_INS_BNEL = 20;;
|
|
let _MIPS_INS_B = 21;;
|
|
let _MIPS_INS_BEQ = 22;;
|
|
let _MIPS_INS_BNE = 23;;
|
|
let _MIPS_INS_CFTC1 = 24;;
|
|
let _MIPS_INS_CTTC1 = 25;;
|
|
let _MIPS_INS_DMUL = 26;;
|
|
let _MIPS_INS_DMULO = 27;;
|
|
let _MIPS_INS_DMULOU = 28;;
|
|
let _MIPS_INS_DROL = 29;;
|
|
let _MIPS_INS_DROR = 30;;
|
|
let _MIPS_INS_DDIV = 31;;
|
|
let _MIPS_INS_DREM = 32;;
|
|
let _MIPS_INS_DDIVU = 33;;
|
|
let _MIPS_INS_DREMU = 34;;
|
|
let _MIPS_INS_JAL = 35;;
|
|
let _MIPS_INS_LD = 36;;
|
|
let _MIPS_INS_LWM = 37;;
|
|
let _MIPS_INS_LA = 38;;
|
|
let _MIPS_INS_DLA = 39;;
|
|
let _MIPS_INS_LI = 40;;
|
|
let _MIPS_INS_DLI = 41;;
|
|
let _MIPS_INS_LI_D = 42;;
|
|
let _MIPS_INS_LI_S = 43;;
|
|
let _MIPS_INS_MFTACX = 44;;
|
|
let _MIPS_INS_MFTC0 = 45;;
|
|
let _MIPS_INS_MFTC1 = 46;;
|
|
let _MIPS_INS_MFTDSP = 47;;
|
|
let _MIPS_INS_MFTGPR = 48;;
|
|
let _MIPS_INS_MFTHC1 = 49;;
|
|
let _MIPS_INS_MFTHI = 50;;
|
|
let _MIPS_INS_MFTLO = 51;;
|
|
let _MIPS_INS_MTTACX = 52;;
|
|
let _MIPS_INS_MTTC0 = 53;;
|
|
let _MIPS_INS_MTTC1 = 54;;
|
|
let _MIPS_INS_MTTDSP = 55;;
|
|
let _MIPS_INS_MTTGPR = 56;;
|
|
let _MIPS_INS_MTTHC1 = 57;;
|
|
let _MIPS_INS_MTTHI = 58;;
|
|
let _MIPS_INS_MTTLO = 59;;
|
|
let _MIPS_INS_MUL = 60;;
|
|
let _MIPS_INS_MULO = 61;;
|
|
let _MIPS_INS_MULOU = 62;;
|
|
let _MIPS_INS_NOR = 63;;
|
|
let _MIPS_INS_ADDIU = 64;;
|
|
let _MIPS_INS_ANDI = 65;;
|
|
let _MIPS_INS_SUBU = 66;;
|
|
let _MIPS_INS_TRUNC_W_D = 67;;
|
|
let _MIPS_INS_TRUNC_W_S = 68;;
|
|
let _MIPS_INS_ROL = 69;;
|
|
let _MIPS_INS_ROR = 70;;
|
|
let _MIPS_INS_S_D = 71;;
|
|
let _MIPS_INS_SD = 72;;
|
|
let _MIPS_INS_DIV = 73;;
|
|
let _MIPS_INS_SEQ = 74;;
|
|
let _MIPS_INS_SGE = 75;;
|
|
let _MIPS_INS_SGEU = 76;;
|
|
let _MIPS_INS_SGT = 77;;
|
|
let _MIPS_INS_SGTU = 78;;
|
|
let _MIPS_INS_SLE = 79;;
|
|
let _MIPS_INS_SLEU = 80;;
|
|
let _MIPS_INS_SLT = 81;;
|
|
let _MIPS_INS_SLTU = 82;;
|
|
let _MIPS_INS_SNE = 83;;
|
|
let _MIPS_INS_REM = 84;;
|
|
let _MIPS_INS_SWM = 85;;
|
|
let _MIPS_INS_SAA = 86;;
|
|
let _MIPS_INS_SAAD = 87;;
|
|
let _MIPS_INS_DIVU = 88;;
|
|
let _MIPS_INS_REMU = 89;;
|
|
let _MIPS_INS_ULH = 90;;
|
|
let _MIPS_INS_ULHU = 91;;
|
|
let _MIPS_INS_ULW = 92;;
|
|
let _MIPS_INS_USH = 93;;
|
|
let _MIPS_INS_USW = 94;;
|
|
let _MIPS_INS_ABSQ_S_PH = 95;;
|
|
let _MIPS_INS_ABSQ_S_QB = 96;;
|
|
let _MIPS_INS_ABSQ_S_W = 97;;
|
|
let _MIPS_INS_ADD = 98;;
|
|
let _MIPS_INS_ADDIUPC = 99;;
|
|
let _MIPS_INS_ADDIUR1SP = 100;;
|
|
let _MIPS_INS_ADDIUR2 = 101;;
|
|
let _MIPS_INS_ADDIUS5 = 102;;
|
|
let _MIPS_INS_ADDIUSP = 103;;
|
|
let _MIPS_INS_ADDQH_PH = 104;;
|
|
let _MIPS_INS_ADDQH_R_PH = 105;;
|
|
let _MIPS_INS_ADDQH_R_W = 106;;
|
|
let _MIPS_INS_ADDQH_W = 107;;
|
|
let _MIPS_INS_ADDQ_PH = 108;;
|
|
let _MIPS_INS_ADDQ_S_PH = 109;;
|
|
let _MIPS_INS_ADDQ_S_W = 110;;
|
|
let _MIPS_INS_ADDR_PS = 111;;
|
|
let _MIPS_INS_ADDSC = 112;;
|
|
let _MIPS_INS_ADDS_A_B = 113;;
|
|
let _MIPS_INS_ADDS_A_D = 114;;
|
|
let _MIPS_INS_ADDS_A_H = 115;;
|
|
let _MIPS_INS_ADDS_A_W = 116;;
|
|
let _MIPS_INS_ADDS_S_B = 117;;
|
|
let _MIPS_INS_ADDS_S_D = 118;;
|
|
let _MIPS_INS_ADDS_S_H = 119;;
|
|
let _MIPS_INS_ADDS_S_W = 120;;
|
|
let _MIPS_INS_ADDS_U_B = 121;;
|
|
let _MIPS_INS_ADDS_U_D = 122;;
|
|
let _MIPS_INS_ADDS_U_H = 123;;
|
|
let _MIPS_INS_ADDS_U_W = 124;;
|
|
let _MIPS_INS_ADDU16 = 125;;
|
|
let _MIPS_INS_ADDUH_QB = 126;;
|
|
let _MIPS_INS_ADDUH_R_QB = 127;;
|
|
let _MIPS_INS_ADDU = 128;;
|
|
let _MIPS_INS_ADDU_PH = 129;;
|
|
let _MIPS_INS_ADDU_QB = 130;;
|
|
let _MIPS_INS_ADDU_S_PH = 131;;
|
|
let _MIPS_INS_ADDU_S_QB = 132;;
|
|
let _MIPS_INS_ADDVI_B = 133;;
|
|
let _MIPS_INS_ADDVI_D = 134;;
|
|
let _MIPS_INS_ADDVI_H = 135;;
|
|
let _MIPS_INS_ADDVI_W = 136;;
|
|
let _MIPS_INS_ADDV_B = 137;;
|
|
let _MIPS_INS_ADDV_D = 138;;
|
|
let _MIPS_INS_ADDV_H = 139;;
|
|
let _MIPS_INS_ADDV_W = 140;;
|
|
let _MIPS_INS_ADDWC = 141;;
|
|
let _MIPS_INS_ADD_A_B = 142;;
|
|
let _MIPS_INS_ADD_A_D = 143;;
|
|
let _MIPS_INS_ADD_A_H = 144;;
|
|
let _MIPS_INS_ADD_A_W = 145;;
|
|
let _MIPS_INS_ADDI = 146;;
|
|
let _MIPS_INS_ALUIPC = 147;;
|
|
let _MIPS_INS_AND = 148;;
|
|
let _MIPS_INS_AND16 = 149;;
|
|
let _MIPS_INS_ANDI16 = 150;;
|
|
let _MIPS_INS_ANDI_B = 151;;
|
|
let _MIPS_INS_AND_V = 152;;
|
|
let _MIPS_INS_APPEND = 153;;
|
|
let _MIPS_INS_ASUB_S_B = 154;;
|
|
let _MIPS_INS_ASUB_S_D = 155;;
|
|
let _MIPS_INS_ASUB_S_H = 156;;
|
|
let _MIPS_INS_ASUB_S_W = 157;;
|
|
let _MIPS_INS_ASUB_U_B = 158;;
|
|
let _MIPS_INS_ASUB_U_D = 159;;
|
|
let _MIPS_INS_ASUB_U_H = 160;;
|
|
let _MIPS_INS_ASUB_U_W = 161;;
|
|
let _MIPS_INS_AUI = 162;;
|
|
let _MIPS_INS_AUIPC = 163;;
|
|
let _MIPS_INS_AVER_S_B = 164;;
|
|
let _MIPS_INS_AVER_S_D = 165;;
|
|
let _MIPS_INS_AVER_S_H = 166;;
|
|
let _MIPS_INS_AVER_S_W = 167;;
|
|
let _MIPS_INS_AVER_U_B = 168;;
|
|
let _MIPS_INS_AVER_U_D = 169;;
|
|
let _MIPS_INS_AVER_U_H = 170;;
|
|
let _MIPS_INS_AVER_U_W = 171;;
|
|
let _MIPS_INS_AVE_S_B = 172;;
|
|
let _MIPS_INS_AVE_S_D = 173;;
|
|
let _MIPS_INS_AVE_S_H = 174;;
|
|
let _MIPS_INS_AVE_S_W = 175;;
|
|
let _MIPS_INS_AVE_U_B = 176;;
|
|
let _MIPS_INS_AVE_U_D = 177;;
|
|
let _MIPS_INS_AVE_U_H = 178;;
|
|
let _MIPS_INS_AVE_U_W = 179;;
|
|
let _MIPS_INS_B16 = 180;;
|
|
let _MIPS_INS_BADDU = 181;;
|
|
let _MIPS_INS_BAL = 182;;
|
|
let _MIPS_INS_BALC = 183;;
|
|
let _MIPS_INS_BALIGN = 184;;
|
|
let _MIPS_INS_BALRSC = 185;;
|
|
let _MIPS_INS_BBEQZC = 186;;
|
|
let _MIPS_INS_BBIT0 = 187;;
|
|
let _MIPS_INS_BBIT032 = 188;;
|
|
let _MIPS_INS_BBIT1 = 189;;
|
|
let _MIPS_INS_BBIT132 = 190;;
|
|
let _MIPS_INS_BBNEZC = 191;;
|
|
let _MIPS_INS_BC = 192;;
|
|
let _MIPS_INS_BC16 = 193;;
|
|
let _MIPS_INS_BC1EQZ = 194;;
|
|
let _MIPS_INS_BC1EQZC = 195;;
|
|
let _MIPS_INS_BC1F = 196;;
|
|
let _MIPS_INS_BC1FL = 197;;
|
|
let _MIPS_INS_BC1NEZ = 198;;
|
|
let _MIPS_INS_BC1NEZC = 199;;
|
|
let _MIPS_INS_BC1T = 200;;
|
|
let _MIPS_INS_BC1TL = 201;;
|
|
let _MIPS_INS_BC2EQZ = 202;;
|
|
let _MIPS_INS_BC2EQZC = 203;;
|
|
let _MIPS_INS_BC2NEZ = 204;;
|
|
let _MIPS_INS_BC2NEZC = 205;;
|
|
let _MIPS_INS_BCLRI_B = 206;;
|
|
let _MIPS_INS_BCLRI_D = 207;;
|
|
let _MIPS_INS_BCLRI_H = 208;;
|
|
let _MIPS_INS_BCLRI_W = 209;;
|
|
let _MIPS_INS_BCLR_B = 210;;
|
|
let _MIPS_INS_BCLR_D = 211;;
|
|
let _MIPS_INS_BCLR_H = 212;;
|
|
let _MIPS_INS_BCLR_W = 213;;
|
|
let _MIPS_INS_BEQC = 214;;
|
|
let _MIPS_INS_BEQIC = 215;;
|
|
let _MIPS_INS_BEQZ16 = 216;;
|
|
let _MIPS_INS_BEQZALC = 217;;
|
|
let _MIPS_INS_BEQZC = 218;;
|
|
let _MIPS_INS_BEQZC16 = 219;;
|
|
let _MIPS_INS_BGEC = 220;;
|
|
let _MIPS_INS_BGEIC = 221;;
|
|
let _MIPS_INS_BGEIUC = 222;;
|
|
let _MIPS_INS_BGEUC = 223;;
|
|
let _MIPS_INS_BGEZ = 224;;
|
|
let _MIPS_INS_BGEZAL = 225;;
|
|
let _MIPS_INS_BGEZALC = 226;;
|
|
let _MIPS_INS_BGEZALL = 227;;
|
|
let _MIPS_INS_BGEZALS = 228;;
|
|
let _MIPS_INS_BGEZC = 229;;
|
|
let _MIPS_INS_BGEZL = 230;;
|
|
let _MIPS_INS_BGTZ = 231;;
|
|
let _MIPS_INS_BGTZALC = 232;;
|
|
let _MIPS_INS_BGTZC = 233;;
|
|
let _MIPS_INS_BGTZL = 234;;
|
|
let _MIPS_INS_BINSLI_B = 235;;
|
|
let _MIPS_INS_BINSLI_D = 236;;
|
|
let _MIPS_INS_BINSLI_H = 237;;
|
|
let _MIPS_INS_BINSLI_W = 238;;
|
|
let _MIPS_INS_BINSL_B = 239;;
|
|
let _MIPS_INS_BINSL_D = 240;;
|
|
let _MIPS_INS_BINSL_H = 241;;
|
|
let _MIPS_INS_BINSL_W = 242;;
|
|
let _MIPS_INS_BINSRI_B = 243;;
|
|
let _MIPS_INS_BINSRI_D = 244;;
|
|
let _MIPS_INS_BINSRI_H = 245;;
|
|
let _MIPS_INS_BINSRI_W = 246;;
|
|
let _MIPS_INS_BINSR_B = 247;;
|
|
let _MIPS_INS_BINSR_D = 248;;
|
|
let _MIPS_INS_BINSR_H = 249;;
|
|
let _MIPS_INS_BINSR_W = 250;;
|
|
let _MIPS_INS_BITREV = 251;;
|
|
let _MIPS_INS_BITREVW = 252;;
|
|
let _MIPS_INS_BITSWAP = 253;;
|
|
let _MIPS_INS_BLEZ = 254;;
|
|
let _MIPS_INS_BLEZALC = 255;;
|
|
let _MIPS_INS_BLEZC = 256;;
|
|
let _MIPS_INS_BLEZL = 257;;
|
|
let _MIPS_INS_BLTC = 258;;
|
|
let _MIPS_INS_BLTIC = 259;;
|
|
let _MIPS_INS_BLTIUC = 260;;
|
|
let _MIPS_INS_BLTUC = 261;;
|
|
let _MIPS_INS_BLTZ = 262;;
|
|
let _MIPS_INS_BLTZAL = 263;;
|
|
let _MIPS_INS_BLTZALC = 264;;
|
|
let _MIPS_INS_BLTZALL = 265;;
|
|
let _MIPS_INS_BLTZALS = 266;;
|
|
let _MIPS_INS_BLTZC = 267;;
|
|
let _MIPS_INS_BLTZL = 268;;
|
|
let _MIPS_INS_BMNZI_B = 269;;
|
|
let _MIPS_INS_BMNZ_V = 270;;
|
|
let _MIPS_INS_BMZI_B = 271;;
|
|
let _MIPS_INS_BMZ_V = 272;;
|
|
let _MIPS_INS_BNEC = 273;;
|
|
let _MIPS_INS_BNEGI_B = 274;;
|
|
let _MIPS_INS_BNEGI_D = 275;;
|
|
let _MIPS_INS_BNEGI_H = 276;;
|
|
let _MIPS_INS_BNEGI_W = 277;;
|
|
let _MIPS_INS_BNEG_B = 278;;
|
|
let _MIPS_INS_BNEG_D = 279;;
|
|
let _MIPS_INS_BNEG_H = 280;;
|
|
let _MIPS_INS_BNEG_W = 281;;
|
|
let _MIPS_INS_BNEIC = 282;;
|
|
let _MIPS_INS_BNEZ16 = 283;;
|
|
let _MIPS_INS_BNEZALC = 284;;
|
|
let _MIPS_INS_BNEZC = 285;;
|
|
let _MIPS_INS_BNEZC16 = 286;;
|
|
let _MIPS_INS_BNVC = 287;;
|
|
let _MIPS_INS_BNZ_B = 288;;
|
|
let _MIPS_INS_BNZ_D = 289;;
|
|
let _MIPS_INS_BNZ_H = 290;;
|
|
let _MIPS_INS_BNZ_V = 291;;
|
|
let _MIPS_INS_BNZ_W = 292;;
|
|
let _MIPS_INS_BOVC = 293;;
|
|
let _MIPS_INS_BPOSGE32 = 294;;
|
|
let _MIPS_INS_BPOSGE32C = 295;;
|
|
let _MIPS_INS_BREAK = 296;;
|
|
let _MIPS_INS_BREAK16 = 297;;
|
|
let _MIPS_INS_BRSC = 298;;
|
|
let _MIPS_INS_BSELI_B = 299;;
|
|
let _MIPS_INS_BSEL_V = 300;;
|
|
let _MIPS_INS_BSETI_B = 301;;
|
|
let _MIPS_INS_BSETI_D = 302;;
|
|
let _MIPS_INS_BSETI_H = 303;;
|
|
let _MIPS_INS_BSETI_W = 304;;
|
|
let _MIPS_INS_BSET_B = 305;;
|
|
let _MIPS_INS_BSET_D = 306;;
|
|
let _MIPS_INS_BSET_H = 307;;
|
|
let _MIPS_INS_BSET_W = 308;;
|
|
let _MIPS_INS_BYTEREVW = 309;;
|
|
let _MIPS_INS_BZ_B = 310;;
|
|
let _MIPS_INS_BZ_D = 311;;
|
|
let _MIPS_INS_BZ_H = 312;;
|
|
let _MIPS_INS_BZ_V = 313;;
|
|
let _MIPS_INS_BZ_W = 314;;
|
|
let _MIPS_INS_BEQZ = 315;;
|
|
let _MIPS_INS_BNEZ = 316;;
|
|
let _MIPS_INS_BTEQZ = 317;;
|
|
let _MIPS_INS_BTNEZ = 318;;
|
|
let _MIPS_INS_CACHE = 319;;
|
|
let _MIPS_INS_CACHEE = 320;;
|
|
let _MIPS_INS_CEIL_L_D = 321;;
|
|
let _MIPS_INS_CEIL_L_S = 322;;
|
|
let _MIPS_INS_CEIL_W_D = 323;;
|
|
let _MIPS_INS_CEIL_W_S = 324;;
|
|
let _MIPS_INS_CEQI_B = 325;;
|
|
let _MIPS_INS_CEQI_D = 326;;
|
|
let _MIPS_INS_CEQI_H = 327;;
|
|
let _MIPS_INS_CEQI_W = 328;;
|
|
let _MIPS_INS_CEQ_B = 329;;
|
|
let _MIPS_INS_CEQ_D = 330;;
|
|
let _MIPS_INS_CEQ_H = 331;;
|
|
let _MIPS_INS_CEQ_W = 332;;
|
|
let _MIPS_INS_CFC1 = 333;;
|
|
let _MIPS_INS_CFC2 = 334;;
|
|
let _MIPS_INS_CFCMSA = 335;;
|
|
let _MIPS_INS_CINS = 336;;
|
|
let _MIPS_INS_CINS32 = 337;;
|
|
let _MIPS_INS_CLASS_D = 338;;
|
|
let _MIPS_INS_CLASS_S = 339;;
|
|
let _MIPS_INS_CLEI_S_B = 340;;
|
|
let _MIPS_INS_CLEI_S_D = 341;;
|
|
let _MIPS_INS_CLEI_S_H = 342;;
|
|
let _MIPS_INS_CLEI_S_W = 343;;
|
|
let _MIPS_INS_CLEI_U_B = 344;;
|
|
let _MIPS_INS_CLEI_U_D = 345;;
|
|
let _MIPS_INS_CLEI_U_H = 346;;
|
|
let _MIPS_INS_CLEI_U_W = 347;;
|
|
let _MIPS_INS_CLE_S_B = 348;;
|
|
let _MIPS_INS_CLE_S_D = 349;;
|
|
let _MIPS_INS_CLE_S_H = 350;;
|
|
let _MIPS_INS_CLE_S_W = 351;;
|
|
let _MIPS_INS_CLE_U_B = 352;;
|
|
let _MIPS_INS_CLE_U_D = 353;;
|
|
let _MIPS_INS_CLE_U_H = 354;;
|
|
let _MIPS_INS_CLE_U_W = 355;;
|
|
let _MIPS_INS_CLO = 356;;
|
|
let _MIPS_INS_CLTI_S_B = 357;;
|
|
let _MIPS_INS_CLTI_S_D = 358;;
|
|
let _MIPS_INS_CLTI_S_H = 359;;
|
|
let _MIPS_INS_CLTI_S_W = 360;;
|
|
let _MIPS_INS_CLTI_U_B = 361;;
|
|
let _MIPS_INS_CLTI_U_D = 362;;
|
|
let _MIPS_INS_CLTI_U_H = 363;;
|
|
let _MIPS_INS_CLTI_U_W = 364;;
|
|
let _MIPS_INS_CLT_S_B = 365;;
|
|
let _MIPS_INS_CLT_S_D = 366;;
|
|
let _MIPS_INS_CLT_S_H = 367;;
|
|
let _MIPS_INS_CLT_S_W = 368;;
|
|
let _MIPS_INS_CLT_U_B = 369;;
|
|
let _MIPS_INS_CLT_U_D = 370;;
|
|
let _MIPS_INS_CLT_U_H = 371;;
|
|
let _MIPS_INS_CLT_U_W = 372;;
|
|
let _MIPS_INS_CLZ = 373;;
|
|
let _MIPS_INS_CMPGDU_EQ_QB = 374;;
|
|
let _MIPS_INS_CMPGDU_LE_QB = 375;;
|
|
let _MIPS_INS_CMPGDU_LT_QB = 376;;
|
|
let _MIPS_INS_CMPGU_EQ_QB = 377;;
|
|
let _MIPS_INS_CMPGU_LE_QB = 378;;
|
|
let _MIPS_INS_CMPGU_LT_QB = 379;;
|
|
let _MIPS_INS_CMPU_EQ_QB = 380;;
|
|
let _MIPS_INS_CMPU_LE_QB = 381;;
|
|
let _MIPS_INS_CMPU_LT_QB = 382;;
|
|
let _MIPS_INS_CMP_AF_D = 383;;
|
|
let _MIPS_INS_CMP_AF_S = 384;;
|
|
let _MIPS_INS_CMP_EQ_D = 385;;
|
|
let _MIPS_INS_CMP_EQ_PH = 386;;
|
|
let _MIPS_INS_CMP_EQ_S = 387;;
|
|
let _MIPS_INS_CMP_LE_D = 388;;
|
|
let _MIPS_INS_CMP_LE_PH = 389;;
|
|
let _MIPS_INS_CMP_LE_S = 390;;
|
|
let _MIPS_INS_CMP_LT_D = 391;;
|
|
let _MIPS_INS_CMP_LT_PH = 392;;
|
|
let _MIPS_INS_CMP_LT_S = 393;;
|
|
let _MIPS_INS_CMP_SAF_D = 394;;
|
|
let _MIPS_INS_CMP_SAF_S = 395;;
|
|
let _MIPS_INS_CMP_SEQ_D = 396;;
|
|
let _MIPS_INS_CMP_SEQ_S = 397;;
|
|
let _MIPS_INS_CMP_SLE_D = 398;;
|
|
let _MIPS_INS_CMP_SLE_S = 399;;
|
|
let _MIPS_INS_CMP_SLT_D = 400;;
|
|
let _MIPS_INS_CMP_SLT_S = 401;;
|
|
let _MIPS_INS_CMP_SUEQ_D = 402;;
|
|
let _MIPS_INS_CMP_SUEQ_S = 403;;
|
|
let _MIPS_INS_CMP_SULE_D = 404;;
|
|
let _MIPS_INS_CMP_SULE_S = 405;;
|
|
let _MIPS_INS_CMP_SULT_D = 406;;
|
|
let _MIPS_INS_CMP_SULT_S = 407;;
|
|
let _MIPS_INS_CMP_SUN_D = 408;;
|
|
let _MIPS_INS_CMP_SUN_S = 409;;
|
|
let _MIPS_INS_CMP_UEQ_D = 410;;
|
|
let _MIPS_INS_CMP_UEQ_S = 411;;
|
|
let _MIPS_INS_CMP_ULE_D = 412;;
|
|
let _MIPS_INS_CMP_ULE_S = 413;;
|
|
let _MIPS_INS_CMP_ULT_D = 414;;
|
|
let _MIPS_INS_CMP_ULT_S = 415;;
|
|
let _MIPS_INS_CMP_UN_D = 416;;
|
|
let _MIPS_INS_CMP_UN_S = 417;;
|
|
let _MIPS_INS_COPY_S_B = 418;;
|
|
let _MIPS_INS_COPY_S_D = 419;;
|
|
let _MIPS_INS_COPY_S_H = 420;;
|
|
let _MIPS_INS_COPY_S_W = 421;;
|
|
let _MIPS_INS_COPY_U_B = 422;;
|
|
let _MIPS_INS_COPY_U_H = 423;;
|
|
let _MIPS_INS_COPY_U_W = 424;;
|
|
let _MIPS_INS_CRC32B = 425;;
|
|
let _MIPS_INS_CRC32CB = 426;;
|
|
let _MIPS_INS_CRC32CD = 427;;
|
|
let _MIPS_INS_CRC32CH = 428;;
|
|
let _MIPS_INS_CRC32CW = 429;;
|
|
let _MIPS_INS_CRC32D = 430;;
|
|
let _MIPS_INS_CRC32H = 431;;
|
|
let _MIPS_INS_CRC32W = 432;;
|
|
let _MIPS_INS_CTC1 = 433;;
|
|
let _MIPS_INS_CTC2 = 434;;
|
|
let _MIPS_INS_CTCMSA = 435;;
|
|
let _MIPS_INS_CVT_D_S = 436;;
|
|
let _MIPS_INS_CVT_D_W = 437;;
|
|
let _MIPS_INS_CVT_D_L = 438;;
|
|
let _MIPS_INS_CVT_L_D = 439;;
|
|
let _MIPS_INS_CVT_L_S = 440;;
|
|
let _MIPS_INS_CVT_PS_PW = 441;;
|
|
let _MIPS_INS_CVT_PS_S = 442;;
|
|
let _MIPS_INS_CVT_PW_PS = 443;;
|
|
let _MIPS_INS_CVT_S_D = 444;;
|
|
let _MIPS_INS_CVT_S_L = 445;;
|
|
let _MIPS_INS_CVT_S_PL = 446;;
|
|
let _MIPS_INS_CVT_S_PU = 447;;
|
|
let _MIPS_INS_CVT_S_W = 448;;
|
|
let _MIPS_INS_CVT_W_D = 449;;
|
|
let _MIPS_INS_CVT_W_S = 450;;
|
|
let _MIPS_INS_C_EQ_D = 451;;
|
|
let _MIPS_INS_C_EQ_S = 452;;
|
|
let _MIPS_INS_C_F_D = 453;;
|
|
let _MIPS_INS_C_F_S = 454;;
|
|
let _MIPS_INS_C_LE_D = 455;;
|
|
let _MIPS_INS_C_LE_S = 456;;
|
|
let _MIPS_INS_C_LT_D = 457;;
|
|
let _MIPS_INS_C_LT_S = 458;;
|
|
let _MIPS_INS_C_NGE_D = 459;;
|
|
let _MIPS_INS_C_NGE_S = 460;;
|
|
let _MIPS_INS_C_NGLE_D = 461;;
|
|
let _MIPS_INS_C_NGLE_S = 462;;
|
|
let _MIPS_INS_C_NGL_D = 463;;
|
|
let _MIPS_INS_C_NGL_S = 464;;
|
|
let _MIPS_INS_C_NGT_D = 465;;
|
|
let _MIPS_INS_C_NGT_S = 466;;
|
|
let _MIPS_INS_C_OLE_D = 467;;
|
|
let _MIPS_INS_C_OLE_S = 468;;
|
|
let _MIPS_INS_C_OLT_D = 469;;
|
|
let _MIPS_INS_C_OLT_S = 470;;
|
|
let _MIPS_INS_C_SEQ_D = 471;;
|
|
let _MIPS_INS_C_SEQ_S = 472;;
|
|
let _MIPS_INS_C_SF_D = 473;;
|
|
let _MIPS_INS_C_SF_S = 474;;
|
|
let _MIPS_INS_C_UEQ_D = 475;;
|
|
let _MIPS_INS_C_UEQ_S = 476;;
|
|
let _MIPS_INS_C_ULE_D = 477;;
|
|
let _MIPS_INS_C_ULE_S = 478;;
|
|
let _MIPS_INS_C_ULT_D = 479;;
|
|
let _MIPS_INS_C_ULT_S = 480;;
|
|
let _MIPS_INS_C_UN_D = 481;;
|
|
let _MIPS_INS_C_UN_S = 482;;
|
|
let _MIPS_INS_CMP = 483;;
|
|
let _MIPS_INS_CMPI = 484;;
|
|
let _MIPS_INS_DADD = 485;;
|
|
let _MIPS_INS_DADDI = 486;;
|
|
let _MIPS_INS_DADDIU = 487;;
|
|
let _MIPS_INS_DADDU = 488;;
|
|
let _MIPS_INS_DAHI = 489;;
|
|
let _MIPS_INS_DALIGN = 490;;
|
|
let _MIPS_INS_DATI = 491;;
|
|
let _MIPS_INS_DAUI = 492;;
|
|
let _MIPS_INS_DBITSWAP = 493;;
|
|
let _MIPS_INS_DCLO = 494;;
|
|
let _MIPS_INS_DCLZ = 495;;
|
|
let _MIPS_INS_DERET = 496;;
|
|
let _MIPS_INS_DEXT = 497;;
|
|
let _MIPS_INS_DEXTM = 498;;
|
|
let _MIPS_INS_DEXTU = 499;;
|
|
let _MIPS_INS_DI = 500;;
|
|
let _MIPS_INS_DINS = 501;;
|
|
let _MIPS_INS_DINSM = 502;;
|
|
let _MIPS_INS_DINSU = 503;;
|
|
let _MIPS_INS_DIV_S_B = 504;;
|
|
let _MIPS_INS_DIV_S_D = 505;;
|
|
let _MIPS_INS_DIV_S_H = 506;;
|
|
let _MIPS_INS_DIV_S_W = 507;;
|
|
let _MIPS_INS_DIV_U_B = 508;;
|
|
let _MIPS_INS_DIV_U_D = 509;;
|
|
let _MIPS_INS_DIV_U_H = 510;;
|
|
let _MIPS_INS_DIV_U_W = 511;;
|
|
let _MIPS_INS_DLSA = 512;;
|
|
let _MIPS_INS_DMFC0 = 513;;
|
|
let _MIPS_INS_DMFC1 = 514;;
|
|
let _MIPS_INS_DMFC2 = 515;;
|
|
let _MIPS_INS_DMFGC0 = 516;;
|
|
let _MIPS_INS_DMOD = 517;;
|
|
let _MIPS_INS_DMODU = 518;;
|
|
let _MIPS_INS_DMT = 519;;
|
|
let _MIPS_INS_DMTC0 = 520;;
|
|
let _MIPS_INS_DMTC1 = 521;;
|
|
let _MIPS_INS_DMTC2 = 522;;
|
|
let _MIPS_INS_DMTGC0 = 523;;
|
|
let _MIPS_INS_DMUH = 524;;
|
|
let _MIPS_INS_DMUHU = 525;;
|
|
let _MIPS_INS_DMULT = 526;;
|
|
let _MIPS_INS_DMULTU = 527;;
|
|
let _MIPS_INS_DMULU = 528;;
|
|
let _MIPS_INS_DOTP_S_D = 529;;
|
|
let _MIPS_INS_DOTP_S_H = 530;;
|
|
let _MIPS_INS_DOTP_S_W = 531;;
|
|
let _MIPS_INS_DOTP_U_D = 532;;
|
|
let _MIPS_INS_DOTP_U_H = 533;;
|
|
let _MIPS_INS_DOTP_U_W = 534;;
|
|
let _MIPS_INS_DPADD_S_D = 535;;
|
|
let _MIPS_INS_DPADD_S_H = 536;;
|
|
let _MIPS_INS_DPADD_S_W = 537;;
|
|
let _MIPS_INS_DPADD_U_D = 538;;
|
|
let _MIPS_INS_DPADD_U_H = 539;;
|
|
let _MIPS_INS_DPADD_U_W = 540;;
|
|
let _MIPS_INS_DPAQX_SA_W_PH = 541;;
|
|
let _MIPS_INS_DPAQX_S_W_PH = 542;;
|
|
let _MIPS_INS_DPAQ_SA_L_W = 543;;
|
|
let _MIPS_INS_DPAQ_S_W_PH = 544;;
|
|
let _MIPS_INS_DPAU_H_QBL = 545;;
|
|
let _MIPS_INS_DPAU_H_QBR = 546;;
|
|
let _MIPS_INS_DPAX_W_PH = 547;;
|
|
let _MIPS_INS_DPA_W_PH = 548;;
|
|
let _MIPS_INS_DPOP = 549;;
|
|
let _MIPS_INS_DPSQX_SA_W_PH = 550;;
|
|
let _MIPS_INS_DPSQX_S_W_PH = 551;;
|
|
let _MIPS_INS_DPSQ_SA_L_W = 552;;
|
|
let _MIPS_INS_DPSQ_S_W_PH = 553;;
|
|
let _MIPS_INS_DPSUB_S_D = 554;;
|
|
let _MIPS_INS_DPSUB_S_H = 555;;
|
|
let _MIPS_INS_DPSUB_S_W = 556;;
|
|
let _MIPS_INS_DPSUB_U_D = 557;;
|
|
let _MIPS_INS_DPSUB_U_H = 558;;
|
|
let _MIPS_INS_DPSUB_U_W = 559;;
|
|
let _MIPS_INS_DPSU_H_QBL = 560;;
|
|
let _MIPS_INS_DPSU_H_QBR = 561;;
|
|
let _MIPS_INS_DPSX_W_PH = 562;;
|
|
let _MIPS_INS_DPS_W_PH = 563;;
|
|
let _MIPS_INS_DROTR = 564;;
|
|
let _MIPS_INS_DROTR32 = 565;;
|
|
let _MIPS_INS_DROTRV = 566;;
|
|
let _MIPS_INS_DSBH = 567;;
|
|
let _MIPS_INS_DSHD = 568;;
|
|
let _MIPS_INS_DSLL = 569;;
|
|
let _MIPS_INS_DSLL32 = 570;;
|
|
let _MIPS_INS_DSLLV = 571;;
|
|
let _MIPS_INS_DSRA = 572;;
|
|
let _MIPS_INS_DSRA32 = 573;;
|
|
let _MIPS_INS_DSRAV = 574;;
|
|
let _MIPS_INS_DSRL = 575;;
|
|
let _MIPS_INS_DSRL32 = 576;;
|
|
let _MIPS_INS_DSRLV = 577;;
|
|
let _MIPS_INS_DSUB = 578;;
|
|
let _MIPS_INS_DSUBU = 579;;
|
|
let _MIPS_INS_DVP = 580;;
|
|
let _MIPS_INS_DVPE = 581;;
|
|
let _MIPS_INS_EHB = 582;;
|
|
let _MIPS_INS_EI = 583;;
|
|
let _MIPS_INS_EMT = 584;;
|
|
let _MIPS_INS_ERET = 585;;
|
|
let _MIPS_INS_ERETNC = 586;;
|
|
let _MIPS_INS_EVP = 587;;
|
|
let _MIPS_INS_EVPE = 588;;
|
|
let _MIPS_INS_EXT = 589;;
|
|
let _MIPS_INS_EXTP = 590;;
|
|
let _MIPS_INS_EXTPDP = 591;;
|
|
let _MIPS_INS_EXTPDPV = 592;;
|
|
let _MIPS_INS_EXTPV = 593;;
|
|
let _MIPS_INS_EXTRV_RS_W = 594;;
|
|
let _MIPS_INS_EXTRV_R_W = 595;;
|
|
let _MIPS_INS_EXTRV_S_H = 596;;
|
|
let _MIPS_INS_EXTRV_W = 597;;
|
|
let _MIPS_INS_EXTR_RS_W = 598;;
|
|
let _MIPS_INS_EXTR_R_W = 599;;
|
|
let _MIPS_INS_EXTR_S_H = 600;;
|
|
let _MIPS_INS_EXTR_W = 601;;
|
|
let _MIPS_INS_EXTS = 602;;
|
|
let _MIPS_INS_EXTS32 = 603;;
|
|
let _MIPS_INS_EXTW = 604;;
|
|
let _MIPS_INS_ABS_D = 605;;
|
|
let _MIPS_INS_ABS_S = 606;;
|
|
let _MIPS_INS_FADD_D = 607;;
|
|
let _MIPS_INS_ADD_D = 608;;
|
|
let _MIPS_INS_ADD_PS = 609;;
|
|
let _MIPS_INS_ADD_S = 610;;
|
|
let _MIPS_INS_FADD_W = 611;;
|
|
let _MIPS_INS_FCAF_D = 612;;
|
|
let _MIPS_INS_FCAF_W = 613;;
|
|
let _MIPS_INS_FCEQ_D = 614;;
|
|
let _MIPS_INS_FCEQ_W = 615;;
|
|
let _MIPS_INS_FCLASS_D = 616;;
|
|
let _MIPS_INS_FCLASS_W = 617;;
|
|
let _MIPS_INS_FCLE_D = 618;;
|
|
let _MIPS_INS_FCLE_W = 619;;
|
|
let _MIPS_INS_FCLT_D = 620;;
|
|
let _MIPS_INS_FCLT_W = 621;;
|
|
let _MIPS_INS_FCNE_D = 622;;
|
|
let _MIPS_INS_FCNE_W = 623;;
|
|
let _MIPS_INS_FCOR_D = 624;;
|
|
let _MIPS_INS_FCOR_W = 625;;
|
|
let _MIPS_INS_FCUEQ_D = 626;;
|
|
let _MIPS_INS_FCUEQ_W = 627;;
|
|
let _MIPS_INS_FCULE_D = 628;;
|
|
let _MIPS_INS_FCULE_W = 629;;
|
|
let _MIPS_INS_FCULT_D = 630;;
|
|
let _MIPS_INS_FCULT_W = 631;;
|
|
let _MIPS_INS_FCUNE_D = 632;;
|
|
let _MIPS_INS_FCUNE_W = 633;;
|
|
let _MIPS_INS_FCUN_D = 634;;
|
|
let _MIPS_INS_FCUN_W = 635;;
|
|
let _MIPS_INS_FDIV_D = 636;;
|
|
let _MIPS_INS_DIV_D = 637;;
|
|
let _MIPS_INS_DIV_S = 638;;
|
|
let _MIPS_INS_FDIV_W = 639;;
|
|
let _MIPS_INS_FEXDO_H = 640;;
|
|
let _MIPS_INS_FEXDO_W = 641;;
|
|
let _MIPS_INS_FEXP2_D = 642;;
|
|
let _MIPS_INS_FEXP2_W = 643;;
|
|
let _MIPS_INS_FEXUPL_D = 644;;
|
|
let _MIPS_INS_FEXUPL_W = 645;;
|
|
let _MIPS_INS_FEXUPR_D = 646;;
|
|
let _MIPS_INS_FEXUPR_W = 647;;
|
|
let _MIPS_INS_FFINT_S_D = 648;;
|
|
let _MIPS_INS_FFINT_S_W = 649;;
|
|
let _MIPS_INS_FFINT_U_D = 650;;
|
|
let _MIPS_INS_FFINT_U_W = 651;;
|
|
let _MIPS_INS_FFQL_D = 652;;
|
|
let _MIPS_INS_FFQL_W = 653;;
|
|
let _MIPS_INS_FFQR_D = 654;;
|
|
let _MIPS_INS_FFQR_W = 655;;
|
|
let _MIPS_INS_FILL_B = 656;;
|
|
let _MIPS_INS_FILL_D = 657;;
|
|
let _MIPS_INS_FILL_H = 658;;
|
|
let _MIPS_INS_FILL_W = 659;;
|
|
let _MIPS_INS_FLOG2_D = 660;;
|
|
let _MIPS_INS_FLOG2_W = 661;;
|
|
let _MIPS_INS_FLOOR_L_D = 662;;
|
|
let _MIPS_INS_FLOOR_L_S = 663;;
|
|
let _MIPS_INS_FLOOR_W_D = 664;;
|
|
let _MIPS_INS_FLOOR_W_S = 665;;
|
|
let _MIPS_INS_FMADD_D = 666;;
|
|
let _MIPS_INS_FMADD_W = 667;;
|
|
let _MIPS_INS_FMAX_A_D = 668;;
|
|
let _MIPS_INS_FMAX_A_W = 669;;
|
|
let _MIPS_INS_FMAX_D = 670;;
|
|
let _MIPS_INS_FMAX_W = 671;;
|
|
let _MIPS_INS_FMIN_A_D = 672;;
|
|
let _MIPS_INS_FMIN_A_W = 673;;
|
|
let _MIPS_INS_FMIN_D = 674;;
|
|
let _MIPS_INS_FMIN_W = 675;;
|
|
let _MIPS_INS_MOV_D = 676;;
|
|
let _MIPS_INS_MOV_S = 677;;
|
|
let _MIPS_INS_FMSUB_D = 678;;
|
|
let _MIPS_INS_FMSUB_W = 679;;
|
|
let _MIPS_INS_FMUL_D = 680;;
|
|
let _MIPS_INS_MUL_D = 681;;
|
|
let _MIPS_INS_MUL_PS = 682;;
|
|
let _MIPS_INS_MUL_S = 683;;
|
|
let _MIPS_INS_FMUL_W = 684;;
|
|
let _MIPS_INS_NEG_D = 685;;
|
|
let _MIPS_INS_NEG_S = 686;;
|
|
let _MIPS_INS_FORK = 687;;
|
|
let _MIPS_INS_FRCP_D = 688;;
|
|
let _MIPS_INS_FRCP_W = 689;;
|
|
let _MIPS_INS_FRINT_D = 690;;
|
|
let _MIPS_INS_FRINT_W = 691;;
|
|
let _MIPS_INS_FRSQRT_D = 692;;
|
|
let _MIPS_INS_FRSQRT_W = 693;;
|
|
let _MIPS_INS_FSAF_D = 694;;
|
|
let _MIPS_INS_FSAF_W = 695;;
|
|
let _MIPS_INS_FSEQ_D = 696;;
|
|
let _MIPS_INS_FSEQ_W = 697;;
|
|
let _MIPS_INS_FSLE_D = 698;;
|
|
let _MIPS_INS_FSLE_W = 699;;
|
|
let _MIPS_INS_FSLT_D = 700;;
|
|
let _MIPS_INS_FSLT_W = 701;;
|
|
let _MIPS_INS_FSNE_D = 702;;
|
|
let _MIPS_INS_FSNE_W = 703;;
|
|
let _MIPS_INS_FSOR_D = 704;;
|
|
let _MIPS_INS_FSOR_W = 705;;
|
|
let _MIPS_INS_FSQRT_D = 706;;
|
|
let _MIPS_INS_SQRT_D = 707;;
|
|
let _MIPS_INS_SQRT_S = 708;;
|
|
let _MIPS_INS_FSQRT_W = 709;;
|
|
let _MIPS_INS_FSUB_D = 710;;
|
|
let _MIPS_INS_SUB_D = 711;;
|
|
let _MIPS_INS_SUB_PS = 712;;
|
|
let _MIPS_INS_SUB_S = 713;;
|
|
let _MIPS_INS_FSUB_W = 714;;
|
|
let _MIPS_INS_FSUEQ_D = 715;;
|
|
let _MIPS_INS_FSUEQ_W = 716;;
|
|
let _MIPS_INS_FSULE_D = 717;;
|
|
let _MIPS_INS_FSULE_W = 718;;
|
|
let _MIPS_INS_FSULT_D = 719;;
|
|
let _MIPS_INS_FSULT_W = 720;;
|
|
let _MIPS_INS_FSUNE_D = 721;;
|
|
let _MIPS_INS_FSUNE_W = 722;;
|
|
let _MIPS_INS_FSUN_D = 723;;
|
|
let _MIPS_INS_FSUN_W = 724;;
|
|
let _MIPS_INS_FTINT_S_D = 725;;
|
|
let _MIPS_INS_FTINT_S_W = 726;;
|
|
let _MIPS_INS_FTINT_U_D = 727;;
|
|
let _MIPS_INS_FTINT_U_W = 728;;
|
|
let _MIPS_INS_FTQ_H = 729;;
|
|
let _MIPS_INS_FTQ_W = 730;;
|
|
let _MIPS_INS_FTRUNC_S_D = 731;;
|
|
let _MIPS_INS_FTRUNC_S_W = 732;;
|
|
let _MIPS_INS_FTRUNC_U_D = 733;;
|
|
let _MIPS_INS_FTRUNC_U_W = 734;;
|
|
let _MIPS_INS_GINVI = 735;;
|
|
let _MIPS_INS_GINVT = 736;;
|
|
let _MIPS_INS_HADD_S_D = 737;;
|
|
let _MIPS_INS_HADD_S_H = 738;;
|
|
let _MIPS_INS_HADD_S_W = 739;;
|
|
let _MIPS_INS_HADD_U_D = 740;;
|
|
let _MIPS_INS_HADD_U_H = 741;;
|
|
let _MIPS_INS_HADD_U_W = 742;;
|
|
let _MIPS_INS_HSUB_S_D = 743;;
|
|
let _MIPS_INS_HSUB_S_H = 744;;
|
|
let _MIPS_INS_HSUB_S_W = 745;;
|
|
let _MIPS_INS_HSUB_U_D = 746;;
|
|
let _MIPS_INS_HSUB_U_H = 747;;
|
|
let _MIPS_INS_HSUB_U_W = 748;;
|
|
let _MIPS_INS_HYPCALL = 749;;
|
|
let _MIPS_INS_ILVEV_B = 750;;
|
|
let _MIPS_INS_ILVEV_D = 751;;
|
|
let _MIPS_INS_ILVEV_H = 752;;
|
|
let _MIPS_INS_ILVEV_W = 753;;
|
|
let _MIPS_INS_ILVL_B = 754;;
|
|
let _MIPS_INS_ILVL_D = 755;;
|
|
let _MIPS_INS_ILVL_H = 756;;
|
|
let _MIPS_INS_ILVL_W = 757;;
|
|
let _MIPS_INS_ILVOD_B = 758;;
|
|
let _MIPS_INS_ILVOD_D = 759;;
|
|
let _MIPS_INS_ILVOD_H = 760;;
|
|
let _MIPS_INS_ILVOD_W = 761;;
|
|
let _MIPS_INS_ILVR_B = 762;;
|
|
let _MIPS_INS_ILVR_D = 763;;
|
|
let _MIPS_INS_ILVR_H = 764;;
|
|
let _MIPS_INS_ILVR_W = 765;;
|
|
let _MIPS_INS_INS = 766;;
|
|
let _MIPS_INS_INSERT_B = 767;;
|
|
let _MIPS_INS_INSERT_D = 768;;
|
|
let _MIPS_INS_INSERT_H = 769;;
|
|
let _MIPS_INS_INSERT_W = 770;;
|
|
let _MIPS_INS_INSV = 771;;
|
|
let _MIPS_INS_INSVE_B = 772;;
|
|
let _MIPS_INS_INSVE_D = 773;;
|
|
let _MIPS_INS_INSVE_H = 774;;
|
|
let _MIPS_INS_INSVE_W = 775;;
|
|
let _MIPS_INS_J = 776;;
|
|
let _MIPS_INS_JALR = 777;;
|
|
let _MIPS_INS_JALRC = 778;;
|
|
let _MIPS_INS_JALRC_HB = 779;;
|
|
let _MIPS_INS_JALRS16 = 780;;
|
|
let _MIPS_INS_JALRS = 781;;
|
|
let _MIPS_INS_JALR_HB = 782;;
|
|
let _MIPS_INS_JALS = 783;;
|
|
let _MIPS_INS_JALX = 784;;
|
|
let _MIPS_INS_JIALC = 785;;
|
|
let _MIPS_INS_JIC = 786;;
|
|
let _MIPS_INS_JR = 787;;
|
|
let _MIPS_INS_JR16 = 788;;
|
|
let _MIPS_INS_JRADDIUSP = 789;;
|
|
let _MIPS_INS_JRC = 790;;
|
|
let _MIPS_INS_JRC16 = 791;;
|
|
let _MIPS_INS_JRCADDIUSP = 792;;
|
|
let _MIPS_INS_JR_HB = 793;;
|
|
let _MIPS_INS_LAPC_H = 794;;
|
|
let _MIPS_INS_LAPC_B = 795;;
|
|
let _MIPS_INS_LB = 796;;
|
|
let _MIPS_INS_LBE = 797;;
|
|
let _MIPS_INS_LBU16 = 798;;
|
|
let _MIPS_INS_LBU = 799;;
|
|
let _MIPS_INS_LBUX = 800;;
|
|
let _MIPS_INS_LBX = 801;;
|
|
let _MIPS_INS_LBUE = 802;;
|
|
let _MIPS_INS_LDC1 = 803;;
|
|
let _MIPS_INS_LDC2 = 804;;
|
|
let _MIPS_INS_LDC3 = 805;;
|
|
let _MIPS_INS_LDI_B = 806;;
|
|
let _MIPS_INS_LDI_D = 807;;
|
|
let _MIPS_INS_LDI_H = 808;;
|
|
let _MIPS_INS_LDI_W = 809;;
|
|
let _MIPS_INS_LDL = 810;;
|
|
let _MIPS_INS_LDPC = 811;;
|
|
let _MIPS_INS_LDR = 812;;
|
|
let _MIPS_INS_LDXC1 = 813;;
|
|
let _MIPS_INS_LD_B = 814;;
|
|
let _MIPS_INS_LD_D = 815;;
|
|
let _MIPS_INS_LD_H = 816;;
|
|
let _MIPS_INS_LD_W = 817;;
|
|
let _MIPS_INS_LH = 818;;
|
|
let _MIPS_INS_LHE = 819;;
|
|
let _MIPS_INS_LHU16 = 820;;
|
|
let _MIPS_INS_LHU = 821;;
|
|
let _MIPS_INS_LHUXS = 822;;
|
|
let _MIPS_INS_LHUX = 823;;
|
|
let _MIPS_INS_LHX = 824;;
|
|
let _MIPS_INS_LHXS = 825;;
|
|
let _MIPS_INS_LHUE = 826;;
|
|
let _MIPS_INS_LI16 = 827;;
|
|
let _MIPS_INS_LL = 828;;
|
|
let _MIPS_INS_LLD = 829;;
|
|
let _MIPS_INS_LLE = 830;;
|
|
let _MIPS_INS_LLWP = 831;;
|
|
let _MIPS_INS_LSA = 832;;
|
|
let _MIPS_INS_LUI = 833;;
|
|
let _MIPS_INS_LUXC1 = 834;;
|
|
let _MIPS_INS_LW = 835;;
|
|
let _MIPS_INS_LW16 = 836;;
|
|
let _MIPS_INS_LWC1 = 837;;
|
|
let _MIPS_INS_LWC2 = 838;;
|
|
let _MIPS_INS_LWC3 = 839;;
|
|
let _MIPS_INS_LWE = 840;;
|
|
let _MIPS_INS_LWL = 841;;
|
|
let _MIPS_INS_LWLE = 842;;
|
|
let _MIPS_INS_LWM16 = 843;;
|
|
let _MIPS_INS_LWM32 = 844;;
|
|
let _MIPS_INS_LWPC = 845;;
|
|
let _MIPS_INS_LWP = 846;;
|
|
let _MIPS_INS_LWR = 847;;
|
|
let _MIPS_INS_LWRE = 848;;
|
|
let _MIPS_INS_LWUPC = 849;;
|
|
let _MIPS_INS_LWU = 850;;
|
|
let _MIPS_INS_LWX = 851;;
|
|
let _MIPS_INS_LWXC1 = 852;;
|
|
let _MIPS_INS_LWXS = 853;;
|
|
let _MIPS_INS_MADD = 854;;
|
|
let _MIPS_INS_MADDF_D = 855;;
|
|
let _MIPS_INS_MADDF_S = 856;;
|
|
let _MIPS_INS_MADDR_Q_H = 857;;
|
|
let _MIPS_INS_MADDR_Q_W = 858;;
|
|
let _MIPS_INS_MADDU = 859;;
|
|
let _MIPS_INS_MADDV_B = 860;;
|
|
let _MIPS_INS_MADDV_D = 861;;
|
|
let _MIPS_INS_MADDV_H = 862;;
|
|
let _MIPS_INS_MADDV_W = 863;;
|
|
let _MIPS_INS_MADD_D = 864;;
|
|
let _MIPS_INS_MADD_Q_H = 865;;
|
|
let _MIPS_INS_MADD_Q_W = 866;;
|
|
let _MIPS_INS_MADD_S = 867;;
|
|
let _MIPS_INS_MAQ_SA_W_PHL = 868;;
|
|
let _MIPS_INS_MAQ_SA_W_PHR = 869;;
|
|
let _MIPS_INS_MAQ_S_W_PHL = 870;;
|
|
let _MIPS_INS_MAQ_S_W_PHR = 871;;
|
|
let _MIPS_INS_MAXA_D = 872;;
|
|
let _MIPS_INS_MAXA_S = 873;;
|
|
let _MIPS_INS_MAXI_S_B = 874;;
|
|
let _MIPS_INS_MAXI_S_D = 875;;
|
|
let _MIPS_INS_MAXI_S_H = 876;;
|
|
let _MIPS_INS_MAXI_S_W = 877;;
|
|
let _MIPS_INS_MAXI_U_B = 878;;
|
|
let _MIPS_INS_MAXI_U_D = 879;;
|
|
let _MIPS_INS_MAXI_U_H = 880;;
|
|
let _MIPS_INS_MAXI_U_W = 881;;
|
|
let _MIPS_INS_MAX_A_B = 882;;
|
|
let _MIPS_INS_MAX_A_D = 883;;
|
|
let _MIPS_INS_MAX_A_H = 884;;
|
|
let _MIPS_INS_MAX_A_W = 885;;
|
|
let _MIPS_INS_MAX_D = 886;;
|
|
let _MIPS_INS_MAX_S = 887;;
|
|
let _MIPS_INS_MAX_S_B = 888;;
|
|
let _MIPS_INS_MAX_S_D = 889;;
|
|
let _MIPS_INS_MAX_S_H = 890;;
|
|
let _MIPS_INS_MAX_S_W = 891;;
|
|
let _MIPS_INS_MAX_U_B = 892;;
|
|
let _MIPS_INS_MAX_U_D = 893;;
|
|
let _MIPS_INS_MAX_U_H = 894;;
|
|
let _MIPS_INS_MAX_U_W = 895;;
|
|
let _MIPS_INS_MFC0 = 896;;
|
|
let _MIPS_INS_MFC1 = 897;;
|
|
let _MIPS_INS_MFC2 = 898;;
|
|
let _MIPS_INS_MFGC0 = 899;;
|
|
let _MIPS_INS_MFHC0 = 900;;
|
|
let _MIPS_INS_MFHC1 = 901;;
|
|
let _MIPS_INS_MFHC2 = 902;;
|
|
let _MIPS_INS_MFHGC0 = 903;;
|
|
let _MIPS_INS_MFHI = 904;;
|
|
let _MIPS_INS_MFHI16 = 905;;
|
|
let _MIPS_INS_MFLO = 906;;
|
|
let _MIPS_INS_MFLO16 = 907;;
|
|
let _MIPS_INS_MFTR = 908;;
|
|
let _MIPS_INS_MINA_D = 909;;
|
|
let _MIPS_INS_MINA_S = 910;;
|
|
let _MIPS_INS_MINI_S_B = 911;;
|
|
let _MIPS_INS_MINI_S_D = 912;;
|
|
let _MIPS_INS_MINI_S_H = 913;;
|
|
let _MIPS_INS_MINI_S_W = 914;;
|
|
let _MIPS_INS_MINI_U_B = 915;;
|
|
let _MIPS_INS_MINI_U_D = 916;;
|
|
let _MIPS_INS_MINI_U_H = 917;;
|
|
let _MIPS_INS_MINI_U_W = 918;;
|
|
let _MIPS_INS_MIN_A_B = 919;;
|
|
let _MIPS_INS_MIN_A_D = 920;;
|
|
let _MIPS_INS_MIN_A_H = 921;;
|
|
let _MIPS_INS_MIN_A_W = 922;;
|
|
let _MIPS_INS_MIN_D = 923;;
|
|
let _MIPS_INS_MIN_S = 924;;
|
|
let _MIPS_INS_MIN_S_B = 925;;
|
|
let _MIPS_INS_MIN_S_D = 926;;
|
|
let _MIPS_INS_MIN_S_H = 927;;
|
|
let _MIPS_INS_MIN_S_W = 928;;
|
|
let _MIPS_INS_MIN_U_B = 929;;
|
|
let _MIPS_INS_MIN_U_D = 930;;
|
|
let _MIPS_INS_MIN_U_H = 931;;
|
|
let _MIPS_INS_MIN_U_W = 932;;
|
|
let _MIPS_INS_MOD = 933;;
|
|
let _MIPS_INS_MODSUB = 934;;
|
|
let _MIPS_INS_MODU = 935;;
|
|
let _MIPS_INS_MOD_S_B = 936;;
|
|
let _MIPS_INS_MOD_S_D = 937;;
|
|
let _MIPS_INS_MOD_S_H = 938;;
|
|
let _MIPS_INS_MOD_S_W = 939;;
|
|
let _MIPS_INS_MOD_U_B = 940;;
|
|
let _MIPS_INS_MOD_U_D = 941;;
|
|
let _MIPS_INS_MOD_U_H = 942;;
|
|
let _MIPS_INS_MOD_U_W = 943;;
|
|
let _MIPS_INS_MOVE = 944;;
|
|
let _MIPS_INS_MOVE16 = 945;;
|
|
let _MIPS_INS_MOVE_BALC = 946;;
|
|
let _MIPS_INS_MOVEP = 947;;
|
|
let _MIPS_INS_MOVE_V = 948;;
|
|
let _MIPS_INS_MOVF_D = 949;;
|
|
let _MIPS_INS_MOVF = 950;;
|
|
let _MIPS_INS_MOVF_S = 951;;
|
|
let _MIPS_INS_MOVN_D = 952;;
|
|
let _MIPS_INS_MOVN = 953;;
|
|
let _MIPS_INS_MOVN_S = 954;;
|
|
let _MIPS_INS_MOVT_D = 955;;
|
|
let _MIPS_INS_MOVT = 956;;
|
|
let _MIPS_INS_MOVT_S = 957;;
|
|
let _MIPS_INS_MOVZ_D = 958;;
|
|
let _MIPS_INS_MOVZ = 959;;
|
|
let _MIPS_INS_MOVZ_S = 960;;
|
|
let _MIPS_INS_MSUB = 961;;
|
|
let _MIPS_INS_MSUBF_D = 962;;
|
|
let _MIPS_INS_MSUBF_S = 963;;
|
|
let _MIPS_INS_MSUBR_Q_H = 964;;
|
|
let _MIPS_INS_MSUBR_Q_W = 965;;
|
|
let _MIPS_INS_MSUBU = 966;;
|
|
let _MIPS_INS_MSUBV_B = 967;;
|
|
let _MIPS_INS_MSUBV_D = 968;;
|
|
let _MIPS_INS_MSUBV_H = 969;;
|
|
let _MIPS_INS_MSUBV_W = 970;;
|
|
let _MIPS_INS_MSUB_D = 971;;
|
|
let _MIPS_INS_MSUB_Q_H = 972;;
|
|
let _MIPS_INS_MSUB_Q_W = 973;;
|
|
let _MIPS_INS_MSUB_S = 974;;
|
|
let _MIPS_INS_MTC0 = 975;;
|
|
let _MIPS_INS_MTC1 = 976;;
|
|
let _MIPS_INS_MTC2 = 977;;
|
|
let _MIPS_INS_MTGC0 = 978;;
|
|
let _MIPS_INS_MTHC0 = 979;;
|
|
let _MIPS_INS_MTHC1 = 980;;
|
|
let _MIPS_INS_MTHC2 = 981;;
|
|
let _MIPS_INS_MTHGC0 = 982;;
|
|
let _MIPS_INS_MTHI = 983;;
|
|
let _MIPS_INS_MTHLIP = 984;;
|
|
let _MIPS_INS_MTLO = 985;;
|
|
let _MIPS_INS_MTM0 = 986;;
|
|
let _MIPS_INS_MTM1 = 987;;
|
|
let _MIPS_INS_MTM2 = 988;;
|
|
let _MIPS_INS_MTP0 = 989;;
|
|
let _MIPS_INS_MTP1 = 990;;
|
|
let _MIPS_INS_MTP2 = 991;;
|
|
let _MIPS_INS_MTTR = 992;;
|
|
let _MIPS_INS_MUH = 993;;
|
|
let _MIPS_INS_MUHU = 994;;
|
|
let _MIPS_INS_MULEQ_S_W_PHL = 995;;
|
|
let _MIPS_INS_MULEQ_S_W_PHR = 996;;
|
|
let _MIPS_INS_MULEU_S_PH_QBL = 997;;
|
|
let _MIPS_INS_MULEU_S_PH_QBR = 998;;
|
|
let _MIPS_INS_MULQ_RS_PH = 999;;
|
|
let _MIPS_INS_MULQ_RS_W = 1000;;
|
|
let _MIPS_INS_MULQ_S_PH = 1001;;
|
|
let _MIPS_INS_MULQ_S_W = 1002;;
|
|
let _MIPS_INS_MULR_PS = 1003;;
|
|
let _MIPS_INS_MULR_Q_H = 1004;;
|
|
let _MIPS_INS_MULR_Q_W = 1005;;
|
|
let _MIPS_INS_MULSAQ_S_W_PH = 1006;;
|
|
let _MIPS_INS_MULSA_W_PH = 1007;;
|
|
let _MIPS_INS_MULT = 1008;;
|
|
let _MIPS_INS_MULTU = 1009;;
|
|
let _MIPS_INS_MULU = 1010;;
|
|
let _MIPS_INS_MULV_B = 1011;;
|
|
let _MIPS_INS_MULV_D = 1012;;
|
|
let _MIPS_INS_MULV_H = 1013;;
|
|
let _MIPS_INS_MULV_W = 1014;;
|
|
let _MIPS_INS_MUL_PH = 1015;;
|
|
let _MIPS_INS_MUL_Q_H = 1016;;
|
|
let _MIPS_INS_MUL_Q_W = 1017;;
|
|
let _MIPS_INS_MUL_S_PH = 1018;;
|
|
let _MIPS_INS_NLOC_B = 1019;;
|
|
let _MIPS_INS_NLOC_D = 1020;;
|
|
let _MIPS_INS_NLOC_H = 1021;;
|
|
let _MIPS_INS_NLOC_W = 1022;;
|
|
let _MIPS_INS_NLZC_B = 1023;;
|
|
let _MIPS_INS_NLZC_D = 1024;;
|
|
let _MIPS_INS_NLZC_H = 1025;;
|
|
let _MIPS_INS_NLZC_W = 1026;;
|
|
let _MIPS_INS_NMADD_D = 1027;;
|
|
let _MIPS_INS_NMADD_S = 1028;;
|
|
let _MIPS_INS_NMSUB_D = 1029;;
|
|
let _MIPS_INS_NMSUB_S = 1030;;
|
|
let _MIPS_INS_NOP32 = 1031;;
|
|
let _MIPS_INS_NOP = 1032;;
|
|
let _MIPS_INS_NORI_B = 1033;;
|
|
let _MIPS_INS_NOR_V = 1034;;
|
|
let _MIPS_INS_NOT16 = 1035;;
|
|
let _MIPS_INS_NOT = 1036;;
|
|
let _MIPS_INS_NEG = 1037;;
|
|
let _MIPS_INS_OR = 1038;;
|
|
let _MIPS_INS_OR16 = 1039;;
|
|
let _MIPS_INS_ORI_B = 1040;;
|
|
let _MIPS_INS_ORI = 1041;;
|
|
let _MIPS_INS_OR_V = 1042;;
|
|
let _MIPS_INS_PACKRL_PH = 1043;;
|
|
let _MIPS_INS_PAUSE = 1044;;
|
|
let _MIPS_INS_PCKEV_B = 1045;;
|
|
let _MIPS_INS_PCKEV_D = 1046;;
|
|
let _MIPS_INS_PCKEV_H = 1047;;
|
|
let _MIPS_INS_PCKEV_W = 1048;;
|
|
let _MIPS_INS_PCKOD_B = 1049;;
|
|
let _MIPS_INS_PCKOD_D = 1050;;
|
|
let _MIPS_INS_PCKOD_H = 1051;;
|
|
let _MIPS_INS_PCKOD_W = 1052;;
|
|
let _MIPS_INS_PCNT_B = 1053;;
|
|
let _MIPS_INS_PCNT_D = 1054;;
|
|
let _MIPS_INS_PCNT_H = 1055;;
|
|
let _MIPS_INS_PCNT_W = 1056;;
|
|
let _MIPS_INS_PICK_PH = 1057;;
|
|
let _MIPS_INS_PICK_QB = 1058;;
|
|
let _MIPS_INS_PLL_PS = 1059;;
|
|
let _MIPS_INS_PLU_PS = 1060;;
|
|
let _MIPS_INS_POP = 1061;;
|
|
let _MIPS_INS_PRECEQU_PH_QBL = 1062;;
|
|
let _MIPS_INS_PRECEQU_PH_QBLA = 1063;;
|
|
let _MIPS_INS_PRECEQU_PH_QBR = 1064;;
|
|
let _MIPS_INS_PRECEQU_PH_QBRA = 1065;;
|
|
let _MIPS_INS_PRECEQ_W_PHL = 1066;;
|
|
let _MIPS_INS_PRECEQ_W_PHR = 1067;;
|
|
let _MIPS_INS_PRECEU_PH_QBL = 1068;;
|
|
let _MIPS_INS_PRECEU_PH_QBLA = 1069;;
|
|
let _MIPS_INS_PRECEU_PH_QBR = 1070;;
|
|
let _MIPS_INS_PRECEU_PH_QBRA = 1071;;
|
|
let _MIPS_INS_PRECRQU_S_QB_PH = 1072;;
|
|
let _MIPS_INS_PRECRQ_PH_W = 1073;;
|
|
let _MIPS_INS_PRECRQ_QB_PH = 1074;;
|
|
let _MIPS_INS_PRECRQ_RS_PH_W = 1075;;
|
|
let _MIPS_INS_PRECR_QB_PH = 1076;;
|
|
let _MIPS_INS_PRECR_SRA_PH_W = 1077;;
|
|
let _MIPS_INS_PRECR_SRA_R_PH_W = 1078;;
|
|
let _MIPS_INS_PREF = 1079;;
|
|
let _MIPS_INS_PREFE = 1080;;
|
|
let _MIPS_INS_PREFX = 1081;;
|
|
let _MIPS_INS_PREPEND = 1082;;
|
|
let _MIPS_INS_PUL_PS = 1083;;
|
|
let _MIPS_INS_PUU_PS = 1084;;
|
|
let _MIPS_INS_RADDU_W_QB = 1085;;
|
|
let _MIPS_INS_RDDSP = 1086;;
|
|
let _MIPS_INS_RDHWR = 1087;;
|
|
let _MIPS_INS_RDPGPR = 1088;;
|
|
let _MIPS_INS_RECIP_D = 1089;;
|
|
let _MIPS_INS_RECIP_S = 1090;;
|
|
let _MIPS_INS_REPLV_PH = 1091;;
|
|
let _MIPS_INS_REPLV_QB = 1092;;
|
|
let _MIPS_INS_REPL_PH = 1093;;
|
|
let _MIPS_INS_REPL_QB = 1094;;
|
|
let _MIPS_INS_RESTORE_JRC = 1095;;
|
|
let _MIPS_INS_RESTORE = 1096;;
|
|
let _MIPS_INS_RINT_D = 1097;;
|
|
let _MIPS_INS_RINT_S = 1098;;
|
|
let _MIPS_INS_ROTR = 1099;;
|
|
let _MIPS_INS_ROTRV = 1100;;
|
|
let _MIPS_INS_ROTX = 1101;;
|
|
let _MIPS_INS_ROUND_L_D = 1102;;
|
|
let _MIPS_INS_ROUND_L_S = 1103;;
|
|
let _MIPS_INS_ROUND_W_D = 1104;;
|
|
let _MIPS_INS_ROUND_W_S = 1105;;
|
|
let _MIPS_INS_RSQRT_D = 1106;;
|
|
let _MIPS_INS_RSQRT_S = 1107;;
|
|
let _MIPS_INS_SAT_S_B = 1108;;
|
|
let _MIPS_INS_SAT_S_D = 1109;;
|
|
let _MIPS_INS_SAT_S_H = 1110;;
|
|
let _MIPS_INS_SAT_S_W = 1111;;
|
|
let _MIPS_INS_SAT_U_B = 1112;;
|
|
let _MIPS_INS_SAT_U_D = 1113;;
|
|
let _MIPS_INS_SAT_U_H = 1114;;
|
|
let _MIPS_INS_SAT_U_W = 1115;;
|
|
let _MIPS_INS_SAVE = 1116;;
|
|
let _MIPS_INS_SB = 1117;;
|
|
let _MIPS_INS_SB16 = 1118;;
|
|
let _MIPS_INS_SBE = 1119;;
|
|
let _MIPS_INS_SBX = 1120;;
|
|
let _MIPS_INS_SC = 1121;;
|
|
let _MIPS_INS_SCD = 1122;;
|
|
let _MIPS_INS_SCE = 1123;;
|
|
let _MIPS_INS_SCWP = 1124;;
|
|
let _MIPS_INS_SDBBP = 1125;;
|
|
let _MIPS_INS_SDBBP16 = 1126;;
|
|
let _MIPS_INS_SDC1 = 1127;;
|
|
let _MIPS_INS_SDC2 = 1128;;
|
|
let _MIPS_INS_SDC3 = 1129;;
|
|
let _MIPS_INS_SDL = 1130;;
|
|
let _MIPS_INS_SDR = 1131;;
|
|
let _MIPS_INS_SDXC1 = 1132;;
|
|
let _MIPS_INS_SEB = 1133;;
|
|
let _MIPS_INS_SEH = 1134;;
|
|
let _MIPS_INS_SELEQZ = 1135;;
|
|
let _MIPS_INS_SELEQZ_D = 1136;;
|
|
let _MIPS_INS_SELEQZ_S = 1137;;
|
|
let _MIPS_INS_SELNEZ = 1138;;
|
|
let _MIPS_INS_SELNEZ_D = 1139;;
|
|
let _MIPS_INS_SELNEZ_S = 1140;;
|
|
let _MIPS_INS_SEL_D = 1141;;
|
|
let _MIPS_INS_SEL_S = 1142;;
|
|
let _MIPS_INS_SEQI = 1143;;
|
|
let _MIPS_INS_SH = 1144;;
|
|
let _MIPS_INS_SH16 = 1145;;
|
|
let _MIPS_INS_SHE = 1146;;
|
|
let _MIPS_INS_SHF_B = 1147;;
|
|
let _MIPS_INS_SHF_H = 1148;;
|
|
let _MIPS_INS_SHF_W = 1149;;
|
|
let _MIPS_INS_SHILO = 1150;;
|
|
let _MIPS_INS_SHILOV = 1151;;
|
|
let _MIPS_INS_SHLLV_PH = 1152;;
|
|
let _MIPS_INS_SHLLV_QB = 1153;;
|
|
let _MIPS_INS_SHLLV_S_PH = 1154;;
|
|
let _MIPS_INS_SHLLV_S_W = 1155;;
|
|
let _MIPS_INS_SHLL_PH = 1156;;
|
|
let _MIPS_INS_SHLL_QB = 1157;;
|
|
let _MIPS_INS_SHLL_S_PH = 1158;;
|
|
let _MIPS_INS_SHLL_S_W = 1159;;
|
|
let _MIPS_INS_SHRAV_PH = 1160;;
|
|
let _MIPS_INS_SHRAV_QB = 1161;;
|
|
let _MIPS_INS_SHRAV_R_PH = 1162;;
|
|
let _MIPS_INS_SHRAV_R_QB = 1163;;
|
|
let _MIPS_INS_SHRAV_R_W = 1164;;
|
|
let _MIPS_INS_SHRA_PH = 1165;;
|
|
let _MIPS_INS_SHRA_QB = 1166;;
|
|
let _MIPS_INS_SHRA_R_PH = 1167;;
|
|
let _MIPS_INS_SHRA_R_QB = 1168;;
|
|
let _MIPS_INS_SHRA_R_W = 1169;;
|
|
let _MIPS_INS_SHRLV_PH = 1170;;
|
|
let _MIPS_INS_SHRLV_QB = 1171;;
|
|
let _MIPS_INS_SHRL_PH = 1172;;
|
|
let _MIPS_INS_SHRL_QB = 1173;;
|
|
let _MIPS_INS_SHXS = 1174;;
|
|
let _MIPS_INS_SHX = 1175;;
|
|
let _MIPS_INS_SIGRIE = 1176;;
|
|
let _MIPS_INS_SLDI_B = 1177;;
|
|
let _MIPS_INS_SLDI_D = 1178;;
|
|
let _MIPS_INS_SLDI_H = 1179;;
|
|
let _MIPS_INS_SLDI_W = 1180;;
|
|
let _MIPS_INS_SLD_B = 1181;;
|
|
let _MIPS_INS_SLD_D = 1182;;
|
|
let _MIPS_INS_SLD_H = 1183;;
|
|
let _MIPS_INS_SLD_W = 1184;;
|
|
let _MIPS_INS_SLL = 1185;;
|
|
let _MIPS_INS_SLL16 = 1186;;
|
|
let _MIPS_INS_SLLI_B = 1187;;
|
|
let _MIPS_INS_SLLI_D = 1188;;
|
|
let _MIPS_INS_SLLI_H = 1189;;
|
|
let _MIPS_INS_SLLI_W = 1190;;
|
|
let _MIPS_INS_SLLV = 1191;;
|
|
let _MIPS_INS_SLL_B = 1192;;
|
|
let _MIPS_INS_SLL_D = 1193;;
|
|
let _MIPS_INS_SLL_H = 1194;;
|
|
let _MIPS_INS_SLL_W = 1195;;
|
|
let _MIPS_INS_SLTIU = 1196;;
|
|
let _MIPS_INS_SLTI = 1197;;
|
|
let _MIPS_INS_SNEI = 1198;;
|
|
let _MIPS_INS_SOV = 1199;;
|
|
let _MIPS_INS_SPLATI_B = 1200;;
|
|
let _MIPS_INS_SPLATI_D = 1201;;
|
|
let _MIPS_INS_SPLATI_H = 1202;;
|
|
let _MIPS_INS_SPLATI_W = 1203;;
|
|
let _MIPS_INS_SPLAT_B = 1204;;
|
|
let _MIPS_INS_SPLAT_D = 1205;;
|
|
let _MIPS_INS_SPLAT_H = 1206;;
|
|
let _MIPS_INS_SPLAT_W = 1207;;
|
|
let _MIPS_INS_SRA = 1208;;
|
|
let _MIPS_INS_SRAI_B = 1209;;
|
|
let _MIPS_INS_SRAI_D = 1210;;
|
|
let _MIPS_INS_SRAI_H = 1211;;
|
|
let _MIPS_INS_SRAI_W = 1212;;
|
|
let _MIPS_INS_SRARI_B = 1213;;
|
|
let _MIPS_INS_SRARI_D = 1214;;
|
|
let _MIPS_INS_SRARI_H = 1215;;
|
|
let _MIPS_INS_SRARI_W = 1216;;
|
|
let _MIPS_INS_SRAR_B = 1217;;
|
|
let _MIPS_INS_SRAR_D = 1218;;
|
|
let _MIPS_INS_SRAR_H = 1219;;
|
|
let _MIPS_INS_SRAR_W = 1220;;
|
|
let _MIPS_INS_SRAV = 1221;;
|
|
let _MIPS_INS_SRA_B = 1222;;
|
|
let _MIPS_INS_SRA_D = 1223;;
|
|
let _MIPS_INS_SRA_H = 1224;;
|
|
let _MIPS_INS_SRA_W = 1225;;
|
|
let _MIPS_INS_SRL = 1226;;
|
|
let _MIPS_INS_SRL16 = 1227;;
|
|
let _MIPS_INS_SRLI_B = 1228;;
|
|
let _MIPS_INS_SRLI_D = 1229;;
|
|
let _MIPS_INS_SRLI_H = 1230;;
|
|
let _MIPS_INS_SRLI_W = 1231;;
|
|
let _MIPS_INS_SRLRI_B = 1232;;
|
|
let _MIPS_INS_SRLRI_D = 1233;;
|
|
let _MIPS_INS_SRLRI_H = 1234;;
|
|
let _MIPS_INS_SRLRI_W = 1235;;
|
|
let _MIPS_INS_SRLR_B = 1236;;
|
|
let _MIPS_INS_SRLR_D = 1237;;
|
|
let _MIPS_INS_SRLR_H = 1238;;
|
|
let _MIPS_INS_SRLR_W = 1239;;
|
|
let _MIPS_INS_SRLV = 1240;;
|
|
let _MIPS_INS_SRL_B = 1241;;
|
|
let _MIPS_INS_SRL_D = 1242;;
|
|
let _MIPS_INS_SRL_H = 1243;;
|
|
let _MIPS_INS_SRL_W = 1244;;
|
|
let _MIPS_INS_SSNOP = 1245;;
|
|
let _MIPS_INS_ST_B = 1246;;
|
|
let _MIPS_INS_ST_D = 1247;;
|
|
let _MIPS_INS_ST_H = 1248;;
|
|
let _MIPS_INS_ST_W = 1249;;
|
|
let _MIPS_INS_SUB = 1250;;
|
|
let _MIPS_INS_SUBQH_PH = 1251;;
|
|
let _MIPS_INS_SUBQH_R_PH = 1252;;
|
|
let _MIPS_INS_SUBQH_R_W = 1253;;
|
|
let _MIPS_INS_SUBQH_W = 1254;;
|
|
let _MIPS_INS_SUBQ_PH = 1255;;
|
|
let _MIPS_INS_SUBQ_S_PH = 1256;;
|
|
let _MIPS_INS_SUBQ_S_W = 1257;;
|
|
let _MIPS_INS_SUBSUS_U_B = 1258;;
|
|
let _MIPS_INS_SUBSUS_U_D = 1259;;
|
|
let _MIPS_INS_SUBSUS_U_H = 1260;;
|
|
let _MIPS_INS_SUBSUS_U_W = 1261;;
|
|
let _MIPS_INS_SUBSUU_S_B = 1262;;
|
|
let _MIPS_INS_SUBSUU_S_D = 1263;;
|
|
let _MIPS_INS_SUBSUU_S_H = 1264;;
|
|
let _MIPS_INS_SUBSUU_S_W = 1265;;
|
|
let _MIPS_INS_SUBS_S_B = 1266;;
|
|
let _MIPS_INS_SUBS_S_D = 1267;;
|
|
let _MIPS_INS_SUBS_S_H = 1268;;
|
|
let _MIPS_INS_SUBS_S_W = 1269;;
|
|
let _MIPS_INS_SUBS_U_B = 1270;;
|
|
let _MIPS_INS_SUBS_U_D = 1271;;
|
|
let _MIPS_INS_SUBS_U_H = 1272;;
|
|
let _MIPS_INS_SUBS_U_W = 1273;;
|
|
let _MIPS_INS_SUBU16 = 1274;;
|
|
let _MIPS_INS_SUBUH_QB = 1275;;
|
|
let _MIPS_INS_SUBUH_R_QB = 1276;;
|
|
let _MIPS_INS_SUBU_PH = 1277;;
|
|
let _MIPS_INS_SUBU_QB = 1278;;
|
|
let _MIPS_INS_SUBU_S_PH = 1279;;
|
|
let _MIPS_INS_SUBU_S_QB = 1280;;
|
|
let _MIPS_INS_SUBVI_B = 1281;;
|
|
let _MIPS_INS_SUBVI_D = 1282;;
|
|
let _MIPS_INS_SUBVI_H = 1283;;
|
|
let _MIPS_INS_SUBVI_W = 1284;;
|
|
let _MIPS_INS_SUBV_B = 1285;;
|
|
let _MIPS_INS_SUBV_D = 1286;;
|
|
let _MIPS_INS_SUBV_H = 1287;;
|
|
let _MIPS_INS_SUBV_W = 1288;;
|
|
let _MIPS_INS_SUXC1 = 1289;;
|
|
let _MIPS_INS_SW = 1290;;
|
|
let _MIPS_INS_SW16 = 1291;;
|
|
let _MIPS_INS_SWC1 = 1292;;
|
|
let _MIPS_INS_SWC2 = 1293;;
|
|
let _MIPS_INS_SWC3 = 1294;;
|
|
let _MIPS_INS_SWE = 1295;;
|
|
let _MIPS_INS_SWL = 1296;;
|
|
let _MIPS_INS_SWLE = 1297;;
|
|
let _MIPS_INS_SWM16 = 1298;;
|
|
let _MIPS_INS_SWM32 = 1299;;
|
|
let _MIPS_INS_SWPC = 1300;;
|
|
let _MIPS_INS_SWP = 1301;;
|
|
let _MIPS_INS_SWR = 1302;;
|
|
let _MIPS_INS_SWRE = 1303;;
|
|
let _MIPS_INS_SWSP = 1304;;
|
|
let _MIPS_INS_SWXC1 = 1305;;
|
|
let _MIPS_INS_SWXS = 1306;;
|
|
let _MIPS_INS_SWX = 1307;;
|
|
let _MIPS_INS_SYNC = 1308;;
|
|
let _MIPS_INS_SYNCI = 1309;;
|
|
let _MIPS_INS_SYSCALL = 1310;;
|
|
let _MIPS_INS_TEQ = 1311;;
|
|
let _MIPS_INS_TEQI = 1312;;
|
|
let _MIPS_INS_TGE = 1313;;
|
|
let _MIPS_INS_TGEI = 1314;;
|
|
let _MIPS_INS_TGEIU = 1315;;
|
|
let _MIPS_INS_TGEU = 1316;;
|
|
let _MIPS_INS_TLBGINV = 1317;;
|
|
let _MIPS_INS_TLBGINVF = 1318;;
|
|
let _MIPS_INS_TLBGP = 1319;;
|
|
let _MIPS_INS_TLBGR = 1320;;
|
|
let _MIPS_INS_TLBGWI = 1321;;
|
|
let _MIPS_INS_TLBGWR = 1322;;
|
|
let _MIPS_INS_TLBINV = 1323;;
|
|
let _MIPS_INS_TLBINVF = 1324;;
|
|
let _MIPS_INS_TLBP = 1325;;
|
|
let _MIPS_INS_TLBR = 1326;;
|
|
let _MIPS_INS_TLBWI = 1327;;
|
|
let _MIPS_INS_TLBWR = 1328;;
|
|
let _MIPS_INS_TLT = 1329;;
|
|
let _MIPS_INS_TLTI = 1330;;
|
|
let _MIPS_INS_TLTIU = 1331;;
|
|
let _MIPS_INS_TLTU = 1332;;
|
|
let _MIPS_INS_TNE = 1333;;
|
|
let _MIPS_INS_TNEI = 1334;;
|
|
let _MIPS_INS_TRUNC_L_D = 1335;;
|
|
let _MIPS_INS_TRUNC_L_S = 1336;;
|
|
let _MIPS_INS_UALH = 1337;;
|
|
let _MIPS_INS_UALWM = 1338;;
|
|
let _MIPS_INS_UALW = 1339;;
|
|
let _MIPS_INS_UASH = 1340;;
|
|
let _MIPS_INS_UASWM = 1341;;
|
|
let _MIPS_INS_UASW = 1342;;
|
|
let _MIPS_INS_V3MULU = 1343;;
|
|
let _MIPS_INS_VMM0 = 1344;;
|
|
let _MIPS_INS_VMULU = 1345;;
|
|
let _MIPS_INS_VSHF_B = 1346;;
|
|
let _MIPS_INS_VSHF_D = 1347;;
|
|
let _MIPS_INS_VSHF_H = 1348;;
|
|
let _MIPS_INS_VSHF_W = 1349;;
|
|
let _MIPS_INS_WAIT = 1350;;
|
|
let _MIPS_INS_WRDSP = 1351;;
|
|
let _MIPS_INS_WRPGPR = 1352;;
|
|
let _MIPS_INS_WSBH = 1353;;
|
|
let _MIPS_INS_XOR = 1354;;
|
|
let _MIPS_INS_XOR16 = 1355;;
|
|
let _MIPS_INS_XORI_B = 1356;;
|
|
let _MIPS_INS_XORI = 1357;;
|
|
let _MIPS_INS_XOR_V = 1358;;
|
|
let _MIPS_INS_YIELD = 1359;;
|
|
let _MIPS_INS_ENDING = 1360;;
|
|
let _MIPS_INS_ALIAS_BEGIN = 1361;;
|
|
let _MIPS_INS_ALIAS_ADDIU_B32 = 1362;;
|
|
let _MIPS_INS_ALIAS_BITREVB = 1363;;
|
|
let _MIPS_INS_ALIAS_BITREVH = 1364;;
|
|
let _MIPS_INS_ALIAS_BYTEREVH = 1365;;
|
|
let _MIPS_INS_ALIAS_NOT = 1366;;
|
|
let _MIPS_INS_ALIAS_RESTORE_JRC = 1367;;
|
|
let _MIPS_INS_ALIAS_RESTORE = 1368;;
|
|
let _MIPS_INS_ALIAS_SAVE = 1369;;
|
|
let _MIPS_INS_ALIAS_MOVE = 1370;;
|
|
let _MIPS_INS_ALIAS_BAL = 1371;;
|
|
let _MIPS_INS_ALIAS_JALR_HB = 1372;;
|
|
let _MIPS_INS_ALIAS_NEG = 1373;;
|
|
let _MIPS_INS_ALIAS_NEGU = 1374;;
|
|
let _MIPS_INS_ALIAS_NOP = 1375;;
|
|
let _MIPS_INS_ALIAS_BNEZL = 1376;;
|
|
let _MIPS_INS_ALIAS_BEQZL = 1377;;
|
|
let _MIPS_INS_ALIAS_SYSCALL = 1378;;
|
|
let _MIPS_INS_ALIAS_BREAK = 1379;;
|
|
let _MIPS_INS_ALIAS_EI = 1380;;
|
|
let _MIPS_INS_ALIAS_DI = 1381;;
|
|
let _MIPS_INS_ALIAS_TEQ = 1382;;
|
|
let _MIPS_INS_ALIAS_TGE = 1383;;
|
|
let _MIPS_INS_ALIAS_TGEU = 1384;;
|
|
let _MIPS_INS_ALIAS_TLT = 1385;;
|
|
let _MIPS_INS_ALIAS_TLTU = 1386;;
|
|
let _MIPS_INS_ALIAS_TNE = 1387;;
|
|
let _MIPS_INS_ALIAS_RDHWR = 1388;;
|
|
let _MIPS_INS_ALIAS_SDBBP = 1389;;
|
|
let _MIPS_INS_ALIAS_SYNC = 1390;;
|
|
let _MIPS_INS_ALIAS_HYPCALL = 1391;;
|
|
let _MIPS_INS_ALIAS_NOR = 1392;;
|
|
let _MIPS_INS_ALIAS_C_F_S = 1393;;
|
|
let _MIPS_INS_ALIAS_C_UN_S = 1394;;
|
|
let _MIPS_INS_ALIAS_C_EQ_S = 1395;;
|
|
let _MIPS_INS_ALIAS_C_UEQ_S = 1396;;
|
|
let _MIPS_INS_ALIAS_C_OLT_S = 1397;;
|
|
let _MIPS_INS_ALIAS_C_ULT_S = 1398;;
|
|
let _MIPS_INS_ALIAS_C_OLE_S = 1399;;
|
|
let _MIPS_INS_ALIAS_C_ULE_S = 1400;;
|
|
let _MIPS_INS_ALIAS_C_SF_S = 1401;;
|
|
let _MIPS_INS_ALIAS_C_NGLE_S = 1402;;
|
|
let _MIPS_INS_ALIAS_C_SEQ_S = 1403;;
|
|
let _MIPS_INS_ALIAS_C_NGL_S = 1404;;
|
|
let _MIPS_INS_ALIAS_C_LT_S = 1405;;
|
|
let _MIPS_INS_ALIAS_C_NGE_S = 1406;;
|
|
let _MIPS_INS_ALIAS_C_LE_S = 1407;;
|
|
let _MIPS_INS_ALIAS_C_NGT_S = 1408;;
|
|
let _MIPS_INS_ALIAS_BC1T = 1409;;
|
|
let _MIPS_INS_ALIAS_BC1F = 1410;;
|
|
let _MIPS_INS_ALIAS_C_F_D = 1411;;
|
|
let _MIPS_INS_ALIAS_C_UN_D = 1412;;
|
|
let _MIPS_INS_ALIAS_C_EQ_D = 1413;;
|
|
let _MIPS_INS_ALIAS_C_UEQ_D = 1414;;
|
|
let _MIPS_INS_ALIAS_C_OLT_D = 1415;;
|
|
let _MIPS_INS_ALIAS_C_ULT_D = 1416;;
|
|
let _MIPS_INS_ALIAS_C_OLE_D = 1417;;
|
|
let _MIPS_INS_ALIAS_C_ULE_D = 1418;;
|
|
let _MIPS_INS_ALIAS_C_SF_D = 1419;;
|
|
let _MIPS_INS_ALIAS_C_NGLE_D = 1420;;
|
|
let _MIPS_INS_ALIAS_C_SEQ_D = 1421;;
|
|
let _MIPS_INS_ALIAS_C_NGL_D = 1422;;
|
|
let _MIPS_INS_ALIAS_C_LT_D = 1423;;
|
|
let _MIPS_INS_ALIAS_C_NGE_D = 1424;;
|
|
let _MIPS_INS_ALIAS_C_LE_D = 1425;;
|
|
let _MIPS_INS_ALIAS_C_NGT_D = 1426;;
|
|
let _MIPS_INS_ALIAS_BC1TL = 1427;;
|
|
let _MIPS_INS_ALIAS_BC1FL = 1428;;
|
|
let _MIPS_INS_ALIAS_DNEG = 1429;;
|
|
let _MIPS_INS_ALIAS_DNEGU = 1430;;
|
|
let _MIPS_INS_ALIAS_SLT = 1431;;
|
|
let _MIPS_INS_ALIAS_SLTU = 1432;;
|
|
let _MIPS_INS_ALIAS_SIGRIE = 1433;;
|
|
let _MIPS_INS_ALIAS_JR = 1434;;
|
|
let _MIPS_INS_ALIAS_JRC = 1435;;
|
|
let _MIPS_INS_ALIAS_JALRC = 1436;;
|
|
let _MIPS_INS_ALIAS_DIV = 1437;;
|
|
let _MIPS_INS_ALIAS_DIVU = 1438;;
|
|
let _MIPS_INS_ALIAS_LAPC = 1439;;
|
|
let _MIPS_INS_ALIAS_WRDSP = 1440;;
|
|
let _MIPS_INS_ALIAS_WAIT = 1441;;
|
|
let _MIPS_INS_ALIAS_SW = 1442;;
|
|
let _MIPS_INS_ALIAS_JALRC_HB = 1443;;
|
|
let _MIPS_INS_ALIAS_ADDIU_B = 1444;;
|
|
let _MIPS_INS_ALIAS_ADDIU_W = 1445;;
|
|
let _MIPS_INS_ALIAS_JRC_HB = 1446;;
|
|
let _MIPS_INS_ALIAS_BEQC = 1447;;
|
|
let _MIPS_INS_ALIAS_BNEC = 1448;;
|
|
let _MIPS_INS_ALIAS_BEQZC = 1449;;
|
|
let _MIPS_INS_ALIAS_BNEZC = 1450;;
|
|
let _MIPS_INS_ALIAS_MFC0 = 1451;;
|
|
let _MIPS_INS_ALIAS_MFHC0 = 1452;;
|
|
let _MIPS_INS_ALIAS_MTC0 = 1453;;
|
|
let _MIPS_INS_ALIAS_MTHC0 = 1454;;
|
|
let _MIPS_INS_ALIAS_DMT = 1455;;
|
|
let _MIPS_INS_ALIAS_EMT = 1456;;
|
|
let _MIPS_INS_ALIAS_DVPE = 1457;;
|
|
let _MIPS_INS_ALIAS_EVPE = 1458;;
|
|
let _MIPS_INS_ALIAS_YIELD = 1459;;
|
|
let _MIPS_INS_ALIAS_MFTC0 = 1460;;
|
|
let _MIPS_INS_ALIAS_MFTLO = 1461;;
|
|
let _MIPS_INS_ALIAS_MFTHI = 1462;;
|
|
let _MIPS_INS_ALIAS_MFTACX = 1463;;
|
|
let _MIPS_INS_ALIAS_MTTC0 = 1464;;
|
|
let _MIPS_INS_ALIAS_MTTLO = 1465;;
|
|
let _MIPS_INS_ALIAS_MTTHI = 1466;;
|
|
let _MIPS_INS_ALIAS_MTTACX = 1467;;
|
|
let _MIPS_INS_ALIAS_B = 1468;;
|
|
let _MIPS_INS_ALIAS_BEQZ = 1469;;
|
|
let _MIPS_INS_ALIAS_BNEZ = 1470;;
|
|
let _MIPS_INS_ALIAS_LI = 1471;;
|
|
let _MIPS_INS_ALIAS_END = 1472;;
|
|
|
|
let _MIPS_GRP_INVALID = 0;;
|
|
let _MIPS_GRP_JUMP = 1;;
|
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let _MIPS_GRP_CALL = 2;;
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let _MIPS_GRP_RET = 3;;
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let _MIPS_GRP_INT = 4;;
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let _MIPS_GRP_IRET = 5;;
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let _MIPS_GRP_PRIVILEGE = 6;;
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let _MIPS_GRP_BRANCH_RELATIVE = 7;;
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let _MIPS_FEATURE_HASMIPS2 = 128;;
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let _MIPS_FEATURE_HASMIPS3_32 = 129;;
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let _MIPS_FEATURE_HASMIPS3_32R2 = 130;;
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let _MIPS_FEATURE_HASMIPS3 = 131;;
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let _MIPS_FEATURE_NOTMIPS3 = 132;;
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let _MIPS_FEATURE_HASMIPS4_32 = 133;;
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let _MIPS_FEATURE_NOTMIPS4_32 = 134;;
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let _MIPS_FEATURE_HASMIPS4_32R2 = 135;;
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let _MIPS_FEATURE_HASMIPS5_32R2 = 136;;
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let _MIPS_FEATURE_HASMIPS32 = 137;;
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|
let _MIPS_FEATURE_HASMIPS32R2 = 138;;
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|
let _MIPS_FEATURE_HASMIPS32R5 = 139;;
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|
let _MIPS_FEATURE_HASMIPS32R6 = 140;;
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|
let _MIPS_FEATURE_NOTMIPS32R6 = 141;;
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|
let _MIPS_FEATURE_HASNANOMIPS = 142;;
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|
let _MIPS_FEATURE_NOTNANOMIPS = 143;;
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|
let _MIPS_FEATURE_ISGP64BIT = 144;;
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|
let _MIPS_FEATURE_ISGP32BIT = 145;;
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|
let _MIPS_FEATURE_ISPTR64BIT = 146;;
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|
let _MIPS_FEATURE_ISPTR32BIT = 147;;
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|
let _MIPS_FEATURE_HASMIPS64 = 148;;
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|
let _MIPS_FEATURE_NOTMIPS64 = 149;;
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|
let _MIPS_FEATURE_HASMIPS64R2 = 150;;
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|
let _MIPS_FEATURE_HASMIPS64R5 = 151;;
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|
let _MIPS_FEATURE_HASMIPS64R6 = 152;;
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|
let _MIPS_FEATURE_NOTMIPS64R6 = 153;;
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|
let _MIPS_FEATURE_INMIPS16MODE = 154;;
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|
let _MIPS_FEATURE_NOTINMIPS16MODE = 155;;
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|
let _MIPS_FEATURE_HASCNMIPS = 156;;
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|
let _MIPS_FEATURE_NOTCNMIPS = 157;;
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|
let _MIPS_FEATURE_HASCNMIPSP = 158;;
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|
let _MIPS_FEATURE_NOTCNMIPSP = 159;;
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|
let _MIPS_FEATURE_ISSYM32 = 160;;
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|
let _MIPS_FEATURE_ISSYM64 = 161;;
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|
let _MIPS_FEATURE_HASSTDENC = 162;;
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|
let _MIPS_FEATURE_INMICROMIPS = 163;;
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|
let _MIPS_FEATURE_NOTINMICROMIPS = 164;;
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|
let _MIPS_FEATURE_HASEVA = 165;;
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|
let _MIPS_FEATURE_HASMSA = 166;;
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|
let _MIPS_FEATURE_HASMADD4 = 167;;
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|
let _MIPS_FEATURE_HASMT = 168;;
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|
let _MIPS_FEATURE_USEINDIRECTJUMPSHAZARD = 169;;
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|
let _MIPS_FEATURE_NOINDIRECTJUMPGUARDS = 170;;
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|
let _MIPS_FEATURE_HASCRC = 171;;
|
|
let _MIPS_FEATURE_HASVIRT = 172;;
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|
let _MIPS_FEATURE_HASGINV = 173;;
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|
let _MIPS_FEATURE_HASTLB = 174;;
|
|
let _MIPS_FEATURE_ISFP64BIT = 175;;
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|
let _MIPS_FEATURE_NOTFP64BIT = 176;;
|
|
let _MIPS_FEATURE_ISSINGLEFLOAT = 177;;
|
|
let _MIPS_FEATURE_ISNOTSINGLEFLOAT = 178;;
|
|
let _MIPS_FEATURE_ISNOTSOFTFLOAT = 179;;
|
|
let _MIPS_FEATURE_HASMIPS3D = 180;;
|
|
let _MIPS_FEATURE_HASDSP = 181;;
|
|
let _MIPS_FEATURE_HASDSPR2 = 182;;
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|
let _MIPS_FEATURE_HASDSPR3 = 183;;
|
|
let _MIPS_GRP_ENDING = 184;;
|