00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
198 lines
5.1 KiB
OpenEdge ABL
198 lines
5.1 KiB
OpenEdge ABL
VERSION 1.0 CLASS
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BEGIN
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MultiUse = -1 'True
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Persistable = 0 'NotPersistable
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DataBindingBehavior = 0 'vbNone
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DataSourceBehavior = 0 'vbNone
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MTSTransactionMode = 0 'NotAnMTSObject
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END
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Attribute VB_Name = "CX86Inst"
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Attribute VB_GlobalNameSpace = False
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Attribute VB_Creatable = True
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Attribute VB_PredeclaredId = False
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Attribute VB_Exposed = False
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Option Explicit
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'Capstone Disassembly Engine bindings for VB6
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'Contributed by FireEye FLARE Team
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'Author: David Zimmer <david.zimmer@fireeye.com>, <dzzie@yahoo.com>
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'License: Apache 2.0
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'Copyright: FireEye 2017
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'// Instruction structure sizeof() = 432 bytes
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'typedef struct cs_x86 {
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' // Instruction prefix, which can be up to 4 bytes.
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' // A prefix byte gets value 0 when irrelevant.
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' // prefix[0] indicates REP/REPNE/LOCK prefix (See X86_PREFIX_REP/REPNE/LOCK above)
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' // prefix[1] indicates segment override (irrelevant for x86_64):
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' // See X86_PREFIX_CS/SS/DS/ES/FS/GS above.
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' // prefix[2] indicates operand-size override (X86_PREFIX_OPSIZE)
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' // prefix[3] indicates address-size override (X86_PREFIX_ADDRSIZE)
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' uint8_t prefix[4];
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'
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' // Instruction opcode, which can be from 1 to 4 bytes in size.
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' // This contains VEX opcode as well.
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' // An trailing opcode byte gets value 0 when irrelevant.
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' uint8_t opcode[4];
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'
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' // REX prefix: only a non-zero value is relevant for x86_64
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' uint8_t rex;
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'
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' // Address size, which can be overrided with above prefix[5].
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' uint8_t addr_size;
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'
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' // ModR/M byte
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' uint8_t modrm;
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'
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' // SIB value, or 0 when irrelevant.
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' uint8_t sib;
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'
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' // Displacement value, or 0 when irrelevant.
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' int32_t disp;
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'
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' /* SIB state */
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' // SIB index register, or X86_REG_INVALID when irrelevant.
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' x86_reg sib_index;
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' // SIB scale. only applicable if sib_index is relevant.
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' int8_t sib_scale;
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' // SIB base register, or X86_REG_INVALID when irrelevant.
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' x86_reg sib_base;
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'
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' // SSE Code Condition
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' x86_sse_cc sse_cc;
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'
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' // AVX Code Condition
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' x86_avx_cc avx_cc;
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'
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' // AVX Suppress all Exception
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' bool avx_sae;
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'
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' // AVX static rounding mode
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' x86_avx_rm avx_rm;
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'
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' // Number of operands of this instruction,
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' // or 0 when instruction has no operand.
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' uint8_t op_count;
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'
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' cs_x86_op operands[8]; // operands for this instruction.
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'} cs_x86;
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Private m_prefix() As Byte
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Private m_opcode() As Byte
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Public rex As Byte
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Public addr_size As Byte
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Public modrm As Byte
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Public sib As Byte
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Public disp As Long
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Public sib_index As x86_reg
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Public sib_scale As Byte
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Public sib_base As x86_reg
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Public sse_cc As x86_sse_cc
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Public avx_cc As x86_avx_cc
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Public avx_sae As Boolean
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Public avx_rm As x86_avx_rm
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Public operands As New Collection
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Public parent As CDisassembler
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Private hEngine As Long
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Private m_raw() As Byte
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Property Get prefix() As Byte()
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prefix = m_prefix
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End Property
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Property Get opcode() As Byte()
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opcode = m_opcode
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End Property
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Function toString() As String
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Dim r() As String
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Dim o As CX86Operand
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push r, "X86 Instruction Details:"
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push r, String(40, "-")
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If DEBUG_DUMP Then
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push r, "Raw: "
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push r, HexDump(m_raw)
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End If
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push r, "Prefix: " & b2Str(m_prefix)
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push r, "OpCode: " & b2Str(m_opcode)
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push r, "Rex: " & rex
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push r, "addr_size: " & addr_size
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push r, "modrm: " & Hex(modrm)
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push r, "disp: " & Hex(disp)
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If parent.mode <> CS_MODE_16 Then
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push r, "sib: " & Hex(sib)
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push r, "sib_index: " & regName(hEngine, sib_index)
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push r, "sib_scale: " & Hex(sib_scale)
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push r, "sib_base: " & regName(hEngine, sib_base)
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End If
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If sse_cc <> 0 Then push r, "sse_cc: " & x86_sse_cc2str(sse_cc)
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If avx_cc <> 0 Then push r, "avx_cc: " & x86_avx_cc2str(avx_cc)
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If avx_sae <> 0 Then push r, "avx_sae: " & avx_sae
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If avx_rm <> 0 Then push r, "avx_rm: " & x86_avx_rm2str(avx_rm)
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push r, "Operands: " & operands.count
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For Each o In operands
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push r, String(40, "-")
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push r, o.toString
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Next
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toString = Join(r, vbCrLf)
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End Function
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Friend Sub LoadDetails(lpStruct As Long, parent As CDisassembler)
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Dim cs As cs_x86
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Dim o As CX86Operand
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Dim ptr As Long
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Dim i As Long
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Const sizeOfx86Operand = 48
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Set Me.parent = parent
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hEngine = parent.hCapstone
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CopyMemory ByVal VarPtr(cs), ByVal lpStruct, LenB(cs)
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If DEBUG_DUMP Then
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ReDim m_raw(LenB(cs))
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CopyMemory ByVal VarPtr(m_raw(0)), ByVal lpStruct, LenB(cs)
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End If
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Me.rex = cs.rex
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Me.addr_size = cs.addr_size
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Me.modrm = cs.modrm
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Me.sib = cs.sib
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Me.disp = cs.disp
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Me.sib_index = cs.sib_index
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Me.sib_scale = cs.sib_scale
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Me.sib_base = cs.sib_base
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Me.sse_cc = cs.sse_cc
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Me.avx_cc = cs.avx_cc
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Me.avx_sae = cs.avx_sae
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Me.avx_rm = cs.avx_rm
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m_prefix = cs.prefix
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m_opcode = cs.opcode
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ptr = lpStruct + LenB(cs) 'we don't include the operands in our vb struct..
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For i = 1 To cs.op_count
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Set o = New CX86Operand
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o.LoadDetails ptr, hEngine
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operands.Add o
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ptr = ptr + sizeOfx86Operand
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Next
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End Sub
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