de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
270 lines
5.5 KiB
C
270 lines
5.5 KiB
C
/* Capstone Disassembly Engine */
|
|
/* BPF Backend by david942j <david942j@gmail.com>, 2019 */
|
|
/* SPDX-FileCopyrightText: 2024 Roee Toledano <roeetoledano10@gmail.com> */
|
|
/* SPDX-License-Identifier: BSD-3 */
|
|
|
|
#ifndef CAPSTONE_BPF_H
|
|
#define CAPSTONE_BPF_H
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
#include "platform.h"
|
|
#include "cs_operand.h"
|
|
|
|
#ifdef _MSC_VER
|
|
#pragma warning(disable : 4201)
|
|
#endif
|
|
|
|
#define NUM_BPF_OPS 3
|
|
/// Operand type for instruction's operands
|
|
typedef enum bpf_op_type {
|
|
BPF_OP_INVALID = CS_OP_INVALID,
|
|
BPF_OP_REG = CS_OP_REG,
|
|
BPF_OP_IMM = CS_OP_IMM,
|
|
BPF_OP_OFF = CS_OP_SPECIAL + 0,
|
|
BPF_OP_MSH = CS_OP_SPECIAL + 1, ///< corresponds to cBPF's BPF_MSH mode
|
|
BPF_OP_EXT = CS_OP_SPECIAL + 2, ///< cBPF's extension (not eBPF)
|
|
BPF_OP_MMEM = CS_OP_MEM | (CS_OP_SPECIAL + 3), ///< M[k] in cBPF
|
|
BPF_OP_MEM = CS_OP_MEM,
|
|
} bpf_op_type;
|
|
|
|
/// BPF registers
|
|
typedef enum bpf_reg {
|
|
BPF_REG_INVALID = 0,
|
|
|
|
///< cBPF
|
|
BPF_REG_A,
|
|
BPF_REG_X,
|
|
|
|
///< eBPF
|
|
BPF_REG_R0,
|
|
BPF_REG_R1,
|
|
BPF_REG_R2,
|
|
BPF_REG_R3,
|
|
BPF_REG_R4,
|
|
BPF_REG_R5,
|
|
BPF_REG_R6,
|
|
BPF_REG_R7,
|
|
BPF_REG_R8,
|
|
BPF_REG_R9,
|
|
BPF_REG_R10,
|
|
|
|
BPF_REG_ENDING,
|
|
} bpf_reg;
|
|
|
|
/// Instruction's operand referring to memory
|
|
/// This is associated with BPF_OP_MEM operand type above
|
|
typedef struct bpf_op_mem {
|
|
bpf_reg base; ///< base register
|
|
uint32_t disp; ///< offset value
|
|
} bpf_op_mem;
|
|
|
|
typedef enum bpf_ext_type {
|
|
BPF_EXT_INVALID = 0,
|
|
|
|
BPF_EXT_LEN,
|
|
} bpf_ext_type;
|
|
|
|
/// Instruction operand
|
|
typedef struct cs_bpf_op {
|
|
bpf_op_type type;
|
|
union {
|
|
uint8_t reg; ///< register value for REG operand
|
|
uint64_t imm; ///< immediate value IMM operand
|
|
uint32_t off; ///< offset value, used in jump & call
|
|
bpf_op_mem mem; ///< base/disp value for MEM operand
|
|
/* cBPF only */
|
|
uint32_t mmem; ///< M[k] in cBPF
|
|
uint32_t msh; ///< corresponds to cBPF's BPF_MSH mode
|
|
uint32_t ext; ///< cBPF's extension (not eBPF)
|
|
};
|
|
|
|
bool is_signed; ///< is this operand signed? It is set for memory, immediate and offset operands.
|
|
bool is_pkt; ///< is this operand referring to packet data? It is set for memory operands.
|
|
/// How is this operand accessed? (READ, WRITE or READ|WRITE)
|
|
/// This field is combined of cs_ac_type.
|
|
/// NOTE: this field is irrelevant if engine is compiled in DIET mode.
|
|
cs_ac_type access;
|
|
} cs_bpf_op;
|
|
|
|
/// Instruction structure
|
|
typedef struct cs_bpf {
|
|
uint8_t op_count;
|
|
cs_bpf_op operands[4];
|
|
} cs_bpf;
|
|
|
|
/// BPF instruction
|
|
typedef enum bpf_insn {
|
|
BPF_INS_INVALID = 0,
|
|
|
|
///< ALU
|
|
BPF_INS_ADD,
|
|
BPF_INS_SUB,
|
|
BPF_INS_MUL,
|
|
BPF_INS_DIV,
|
|
BPF_INS_SDIV,
|
|
BPF_INS_OR,
|
|
BPF_INS_AND,
|
|
BPF_INS_LSH,
|
|
BPF_INS_RSH,
|
|
BPF_INS_NEG,
|
|
BPF_INS_MOD,
|
|
BPF_INS_SMOD,
|
|
BPF_INS_XOR,
|
|
BPF_INS_MOV, ///< eBPF only
|
|
BPF_INS_MOVSB, ///< eBPF only
|
|
BPF_INS_MOVSH, ///< eBPF only
|
|
BPF_INS_ARSH, ///< eBPF only
|
|
|
|
///< ALU64, eBPF only
|
|
BPF_INS_ADD64,
|
|
BPF_INS_SUB64,
|
|
BPF_INS_MUL64,
|
|
BPF_INS_DIV64,
|
|
BPF_INS_SDIV64,
|
|
BPF_INS_OR64,
|
|
BPF_INS_AND64,
|
|
BPF_INS_LSH64,
|
|
BPF_INS_RSH64,
|
|
BPF_INS_NEG64,
|
|
BPF_INS_MOD64,
|
|
BPF_INS_SMOD64,
|
|
BPF_INS_XOR64,
|
|
BPF_INS_MOV64,
|
|
BPF_INS_MOVSB64,
|
|
BPF_INS_MOVSH64,
|
|
BPF_INS_MOVSW64,
|
|
BPF_INS_ARSH64,
|
|
|
|
///< Byteswap, eBPF only
|
|
BPF_INS_LE16,
|
|
BPF_INS_LE32,
|
|
BPF_INS_LE64,
|
|
BPF_INS_BE16,
|
|
BPF_INS_BE32,
|
|
BPF_INS_BE64,
|
|
BPF_INS_BSWAP16,
|
|
BPF_INS_BSWAP32,
|
|
BPF_INS_BSWAP64,
|
|
|
|
///< Load
|
|
BPF_INS_LDW, ///< eBPF only
|
|
BPF_INS_LDH,
|
|
BPF_INS_LDB,
|
|
BPF_INS_LDDW, ///< eBPF only: load 64-bit imm
|
|
BPF_INS_LDXW, ///< eBPF only
|
|
BPF_INS_LDXH, ///< eBPF only
|
|
BPF_INS_LDXB, ///< eBPF only
|
|
BPF_INS_LDXDW, ///< eBPF only
|
|
///< Packet data access
|
|
BPF_INS_LDABSW, ///< eBPF only
|
|
BPF_INS_LDABSH, ///< eBPF only
|
|
BPF_INS_LDABSB, ///< eBPF only
|
|
BPF_INS_LDINDW, ///< eBPF only
|
|
BPF_INS_LDINDH, ///< eBPF only
|
|
BPF_INS_LDINDB, ///< eBPF only
|
|
|
|
///< Store
|
|
BPF_INS_STW, ///< eBPF only
|
|
BPF_INS_STH, ///< eBPF only
|
|
BPF_INS_STB, ///< eBPF only
|
|
BPF_INS_STDW, ///< eBPF only
|
|
BPF_INS_STXW, ///< eBPF only
|
|
BPF_INS_STXH, ///< eBPF only
|
|
BPF_INS_STXB, ///< eBPF only
|
|
BPF_INS_STXDW, ///< eBPF only
|
|
BPF_INS_XADDW, ///< eBPF only
|
|
BPF_INS_XADDDW, ///< eBPF only
|
|
|
|
///< Jump
|
|
BPF_INS_JA,
|
|
BPF_INS_JEQ,
|
|
BPF_INS_JGT,
|
|
BPF_INS_JGE,
|
|
BPF_INS_JSET,
|
|
BPF_INS_JNE, ///< eBPF only
|
|
BPF_INS_JSGT, ///< eBPF only
|
|
BPF_INS_JSGE, ///< eBPF only
|
|
BPF_INS_CALL, ///< eBPF only
|
|
BPF_INS_CALLX, ///< eBPF only
|
|
BPF_INS_EXIT, ///< eBPF only
|
|
BPF_INS_JLT, ///< eBPF only
|
|
BPF_INS_JLE, ///< eBPF only
|
|
BPF_INS_JSLT, ///< eBPF only
|
|
BPF_INS_JSLE, ///< eBPF only
|
|
|
|
///< Jump32, eBPF only
|
|
BPF_INS_JAL,
|
|
BPF_INS_JEQ32,
|
|
BPF_INS_JGT32,
|
|
BPF_INS_JGE32,
|
|
BPF_INS_JSET32,
|
|
BPF_INS_JNE32,
|
|
BPF_INS_JSGT32,
|
|
BPF_INS_JSGE32,
|
|
BPF_INS_JLT32,
|
|
BPF_INS_JLE32,
|
|
BPF_INS_JSLT32,
|
|
BPF_INS_JSLE32,
|
|
|
|
///< Return, cBPF only
|
|
BPF_INS_RET,
|
|
|
|
///< Atomic, eBPF only
|
|
BPF_INS_AADD,
|
|
BPF_INS_AOR,
|
|
BPF_INS_AAND,
|
|
BPF_INS_AXOR,
|
|
BPF_INS_AFADD,
|
|
BPF_INS_AFOR,
|
|
BPF_INS_AFAND,
|
|
BPF_INS_AFXOR,
|
|
|
|
///< Atomic 64-bit, eBPF only
|
|
BPF_INS_AXCHG64,
|
|
BPF_INS_ACMPXCHG64,
|
|
BPF_INS_AADD64,
|
|
BPF_INS_AOR64,
|
|
BPF_INS_AAND64,
|
|
BPF_INS_AXOR64,
|
|
BPF_INS_AFADD64,
|
|
BPF_INS_AFOR64,
|
|
BPF_INS_AFAND64,
|
|
BPF_INS_AFXOR64,
|
|
|
|
///< Misc, cBPF only
|
|
BPF_INS_TAX,
|
|
BPF_INS_TXA,
|
|
|
|
BPF_INS_ENDING,
|
|
|
|
// alias instructions
|
|
BPF_INS_LD = BPF_INS_LDW, ///< cBPF only
|
|
BPF_INS_LDX = BPF_INS_LDXW, ///< cBPF only
|
|
BPF_INS_ST = BPF_INS_STW, ///< cBPF only
|
|
BPF_INS_STX = BPF_INS_STXW, ///< cBPF only
|
|
} bpf_insn;
|
|
|
|
/// Group of BPF instructions
|
|
typedef enum bpf_insn_group {
|
|
BPF_GRP_INVALID = 0, ///< = CS_GRP_INVALID
|
|
|
|
BPF_GRP_LOAD,
|
|
BPF_GRP_STORE,
|
|
BPF_GRP_ALU,
|
|
BPF_GRP_JUMP,
|
|
BPF_GRP_CALL, ///< eBPF only
|
|
BPF_GRP_RETURN,
|
|
BPF_GRP_MISC, ///< cBPF only
|
|
|
|
BPF_GRP_ENDING,
|
|
} bpf_insn_group;
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif
|