iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
39 lines
1.8 KiB
C#
39 lines
1.8 KiB
C#
# CS_ARCH_AARCH64, 0, None
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0x00,0x90,0x11,0xd5 == msr BRBCR_EL1, x0
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0x01,0x90,0x31,0xd5 == mrs x1, BRBCR_EL1
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0x02,0x90,0x15,0xd5 == msr BRBCR_EL12, x2
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0x03,0x90,0x35,0xd5 == mrs x3, BRBCR_EL12
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0x04,0x90,0x14,0xd5 == msr BRBCR_EL2, x4
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0x05,0x90,0x34,0xd5 == mrs x5, BRBCR_EL2
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0x26,0x90,0x11,0xd5 == msr BRBFCR_EL1, x6
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0x27,0x90,0x31,0xd5 == mrs x7, BRBFCR_EL1
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0x08,0x92,0x11,0xd5 == expect failure: BRBIDR0_EL1 is RO
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0x09,0x92,0x31,0xd5 == msr S2_1_C9_C2_0, x8
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0x0a,0x91,0x11,0xd5 == msr BRBINFINJ_EL1, x10
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0x0b,0x91,0x31,0xd5 == mrs x11, BRBINFINJ_EL1
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0x2c,0x91,0x11,0xd5 == msr BRBSRCINJ_EL1, x12
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0x2d,0x91,0x31,0xd5 == mrs x13, BRBSRCINJ_EL1
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0x4e,0x91,0x11,0xd5 == msr BRBTGTINJ_EL1, x14
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0x4f,0x91,0x31,0xd5 == mrs x15, BRBTGTINJ_EL1
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0x50,0x90,0x11,0xd5 == msr BRBTS_EL1, x16
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0x51,0x90,0x31,0xd5 == mrs x17, BRBTS_EL1
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0x12,0x80,0x11,0xd5 == expect failure: BRBINF0_EL1 is RO
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0x13,0x80,0x31,0xd5 == msr S2_1_C8_C0_0, x18
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0x14,0x81,0x11,0xd5 == expect failure: BRBINF1_EL1 is RO
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0x15,0x81,0x31,0xd5 == msr S2_1_C8_C1_0, x20
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0x16,0x82,0x11,0xd5 == expect failure: BRBINF2_EL1 is RO
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0x17,0x82,0x31,0xd5 == msr S2_1_C8_C2_0, x22
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0x38,0x84,0x11,0xd5 == expect failure: BRBSRC4_EL1 is RO
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0x39,0x84,0x31,0xd5 == msr S2_1_C8_C4_1, x24
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0x3a,0x88,0x11,0xd5 == expect failure: BRBSRC8_EL1 is RO
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0x3b,0x88,0x31,0xd5 == msr S2_1_C8_C8_1, x26
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0xbc,0x80,0x11,0xd5 == expect failure: BRBSRC16_EL1 is RO
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0xbd,0x80,0x31,0xd5 == msr S2_1_C8_C0_5, x28
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0x40,0x8a,0x11,0xd5 == expect failure: BRBTGT10_EL1 is RO
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0x41,0x8a,0x31,0xd5 == msr S2_1_C8_C10_2, x0
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0xc2,0x85,0x11,0xd5 == expect failure: BRBTGT21_EL1 is RO
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0xc3,0x85,0x31,0xd5 == msr S2_1_C8_C5_6, x2
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0xc4,0x8f,0x11,0xd5 == expect failure: BRBTGT31_EL1 is RO
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0xc5,0x8f,0x31,0xd5 == msr S2_1_C8_C15_6, x4
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