iris
00cc9309cb
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
110 lines
7.1 KiB
C#
110 lines
7.1 KiB
C#
# CS_ARCH_AARCH64, None, None
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# This regression test file is new. The option flags could not be determined.
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# LLVM uses the following mattr = []
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0x8 0xcc 0x38 0xd5 == mrs x8, {{icc_iar1_el1|ICC_IAR1_EL1}}
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0x1a 0xc8 0x38 0xd5 == mrs x26, {{icc_iar0_el1|ICC_IAR0_EL1}}
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0x42 0xcc 0x38 0xd5 == mrs x2, {{icc_hppir1_el1|ICC_HPPIR1_EL1}}
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0x51 0xc8 0x38 0xd5 == mrs x17, {{icc_hppir0_el1|ICC_HPPIR0_EL1}}
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0x7d 0xcb 0x38 0xd5 == mrs x29, {{icc_rpr_el1|ICC_RPR_EL1}}
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0x24 0xcb 0x3c 0xd5 == mrs x4, {{ich_vtr_el2|ICH_VTR_EL2}}
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0x78 0xcb 0x3c 0xd5 == mrs x24, {{ich_eisr_el2|ICH_EISR_EL2}}
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0xa9 0xcb 0x3c 0xd5 == mrs x9, {{ich_elrsr_el2|ICH_ELRSR_EL2}}
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0x78 0xcc 0x38 0xd5 == mrs x24, {{icc_bpr1_el1|ICC_BPR1_EL1}}
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0x6e 0xc8 0x38 0xd5 == mrs x14, {{icc_bpr0_el1|ICC_BPR0_EL1}}
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0x13 0x46 0x38 0xd5 == mrs x19, {{icc_pmr_el1|ICC_PMR_EL1}}
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0x97 0xcc 0x38 0xd5 == mrs x23, {{icc_ctlr_el1|ICC_CTLR_EL1}}
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0x94 0xcc 0x3e 0xd5 == mrs x20, {{icc_ctlr_el3|ICC_CTLR_EL3}}
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0xbc 0xcc 0x38 0xd5 == mrs x28, {{icc_sre_el1|ICC_SRE_EL1}}
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0xb9 0xc9 0x3c 0xd5 == mrs x25, {{icc_sre_el2|ICC_SRE_EL2}}
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0xa8 0xcc 0x3e 0xd5 == mrs x8, {{icc_sre_el3|ICC_SRE_EL3}}
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0xd6 0xcc 0x38 0xd5 == mrs x22, {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}
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0xe5 0xcc 0x38 0xd5 == mrs x5, {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}
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0xe7 0xcc 0x3e 0xd5 == mrs x7, {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}
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0x84 0xc8 0x38 0xd5 == mrs x4, {{icc_ap0r0_el1|ICC_AP0R0_EL1}}
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0xab 0xc8 0x38 0xd5 == mrs x11, {{icc_ap0r1_el1|ICC_AP0R1_EL1}}
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0xdb 0xc8 0x38 0xd5 == mrs x27, {{icc_ap0r2_el1|ICC_AP0R2_EL1}}
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0xf5 0xc8 0x38 0xd5 == mrs x21, {{icc_ap0r3_el1|ICC_AP0R3_EL1}}
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0x2 0xc9 0x38 0xd5 == mrs x2, {{icc_ap1r0_el1|ICC_AP1R0_EL1}}
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0x35 0xc9 0x38 0xd5 == mrs x21, {{icc_ap1r1_el1|ICC_AP1R1_EL1}}
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0x4a 0xc9 0x38 0xd5 == mrs x10, {{icc_ap1r2_el1|ICC_AP1R2_EL1}}
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0x7b 0xc9 0x38 0xd5 == mrs x27, {{icc_ap1r3_el1|ICC_AP1R3_EL1}}
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0x14 0xc8 0x3c 0xd5 == mrs x20, {{ich_ap0r0_el2|ICH_AP0R0_EL2}}
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0x35 0xc8 0x3c 0xd5 == mrs x21, {{ich_ap0r1_el2|ICH_AP0R1_EL2}}
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0x45 0xc8 0x3c 0xd5 == mrs x5, {{ich_ap0r2_el2|ICH_AP0R2_EL2}}
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0x64 0xc8 0x3c 0xd5 == mrs x4, {{ich_ap0r3_el2|ICH_AP0R3_EL2}}
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0xf 0xc9 0x3c 0xd5 == mrs x15, {{ich_ap1r0_el2|ICH_AP1R0_EL2}}
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0x2c 0xc9 0x3c 0xd5 == mrs x12, {{ich_ap1r1_el2|ICH_AP1R1_EL2}}
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0x5b 0xc9 0x3c 0xd5 == mrs x27, {{ich_ap1r2_el2|ICH_AP1R2_EL2}}
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0x74 0xc9 0x3c 0xd5 == mrs x20, {{ich_ap1r3_el2|ICH_AP1R3_EL2}}
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0xa 0xcb 0x3c 0xd5 == mrs x10, {{ich_hcr_el2|ICH_HCR_EL2}}
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0x5b 0xcb 0x3c 0xd5 == mrs x27, {{ich_misr_el2|ICH_MISR_EL2}}
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0xe6 0xcb 0x3c 0xd5 == mrs x6, {{ich_vmcr_el2|ICH_VMCR_EL2}}
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0x3 0xcc 0x3c 0xd5 == mrs x3, {{ich_lr0_el2|ICH_LR0_EL2}}
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0x21 0xcc 0x3c 0xd5 == mrs x1, {{ich_lr1_el2|ICH_LR1_EL2}}
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0x56 0xcc 0x3c 0xd5 == mrs x22, {{ich_lr2_el2|ICH_LR2_EL2}}
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0x75 0xcc 0x3c 0xd5 == mrs x21, {{ich_lr3_el2|ICH_LR3_EL2}}
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0x86 0xcc 0x3c 0xd5 == mrs x6, {{ich_lr4_el2|ICH_LR4_EL2}}
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0xaa 0xcc 0x3c 0xd5 == mrs x10, {{ich_lr5_el2|ICH_LR5_EL2}}
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0xcb 0xcc 0x3c 0xd5 == mrs x11, {{ich_lr6_el2|ICH_LR6_EL2}}
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0xec 0xcc 0x3c 0xd5 == mrs x12, {{ich_lr7_el2|ICH_LR7_EL2}}
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0x0 0xcd 0x3c 0xd5 == mrs x0, {{ich_lr8_el2|ICH_LR8_EL2}}
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0x35 0xcd 0x3c 0xd5 == mrs x21, {{ich_lr9_el2|ICH_LR9_EL2}}
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0x4d 0xcd 0x3c 0xd5 == mrs x13, {{ich_lr10_el2|ICH_LR10_EL2}}
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0x7a 0xcd 0x3c 0xd5 == mrs x26, {{ich_lr11_el2|ICH_LR11_EL2}}
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0x81 0xcd 0x3c 0xd5 == mrs x1, {{ich_lr12_el2|ICH_LR12_EL2}}
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0xa8 0xcd 0x3c 0xd5 == mrs x8, {{ich_lr13_el2|ICH_LR13_EL2}}
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0xc2 0xcd 0x3c 0xd5 == mrs x2, {{ich_lr14_el2|ICH_LR14_EL2}}
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0xe8 0xcd 0x3c 0xd5 == mrs x8, {{ich_lr15_el2|ICH_LR15_EL2}}
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0x3b 0xcc 0x18 0xd5 == msr {{icc_eoir1_el1|ICC_EOIR1_EL1}}, x27
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0x25 0xc8 0x18 0xd5 == msr {{icc_eoir0_el1|ICC_EOIR0_EL1}}, x5
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0x2d 0xcb 0x18 0xd5 == msr {{icc_dir_el1|ICC_DIR_EL1}}, x13
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0xb5 0xcb 0x18 0xd5 == msr {{icc_sgi1r_el1|ICC_SGI1R_EL1}}, x21
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0xd9 0xcb 0x18 0xd5 == msr {{icc_asgi1r_el1|ICC_ASGI1R_EL1}}, x25
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0xfc 0xcb 0x18 0xd5 == msr {{icc_sgi0r_el1|ICC_SGI0R_EL1}}, x28
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0x67 0xcc 0x18 0xd5 == msr {{icc_bpr1_el1|ICC_BPR1_EL1}}, x7
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0x69 0xc8 0x18 0xd5 == msr {{icc_bpr0_el1|ICC_BPR0_EL1}}, x9
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0x1d 0x46 0x18 0xd5 == msr {{icc_pmr_el1|ICC_PMR_EL1}}, x29
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0x98 0xcc 0x18 0xd5 == msr {{icc_ctlr_el1|ICC_CTLR_EL1}}, x24
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0x80 0xcc 0x1e 0xd5 == msr {{icc_ctlr_el3|ICC_CTLR_EL3}}, x0
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0xa2 0xcc 0x18 0xd5 == msr {{icc_sre_el1|ICC_SRE_EL1}}, x2
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0xa5 0xc9 0x1c 0xd5 == msr {{icc_sre_el2|ICC_SRE_EL2}}, x5
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0xaa 0xcc 0x1e 0xd5 == msr {{icc_sre_el3|ICC_SRE_EL3}}, x10
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0xd6 0xcc 0x18 0xd5 == msr {{icc_igrpen0_el1|ICC_IGRPEN0_EL1}}, x22
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0xeb 0xcc 0x18 0xd5 == msr {{icc_igrpen1_el1|ICC_IGRPEN1_EL1}}, x11
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0xe8 0xcc 0x1e 0xd5 == msr {{icc_igrpen1_el3|ICC_IGRPEN1_EL3}}, x8
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0x9b 0xc8 0x18 0xd5 == msr {{icc_ap0r0_el1|ICC_AP0R0_EL1}}, x27
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0xa5 0xc8 0x18 0xd5 == msr {{icc_ap0r1_el1|ICC_AP0R1_EL1}}, x5
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0xd4 0xc8 0x18 0xd5 == msr {{icc_ap0r2_el1|ICC_AP0R2_EL1}}, x20
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0xe0 0xc8 0x18 0xd5 == msr {{icc_ap0r3_el1|ICC_AP0R3_EL1}}, x0
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0x2 0xc9 0x18 0xd5 == msr {{icc_ap1r0_el1|ICC_AP1R0_EL1}}, x2
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0x3d 0xc9 0x18 0xd5 == msr {{icc_ap1r1_el1|ICC_AP1R1_EL1}}, x29
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0x57 0xc9 0x18 0xd5 == msr {{icc_ap1r2_el1|ICC_AP1R2_EL1}}, x23
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0x6b 0xc9 0x18 0xd5 == msr {{icc_ap1r3_el1|ICC_AP1R3_EL1}}, x11
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0x2 0xc8 0x1c 0xd5 == msr {{ich_ap0r0_el2|ICH_AP0R0_EL2}}, x2
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0x3b 0xc8 0x1c 0xd5 == msr {{ich_ap0r1_el2|ICH_AP0R1_EL2}}, x27
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0x47 0xc8 0x1c 0xd5 == msr {{ich_ap0r2_el2|ICH_AP0R2_EL2}}, x7
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0x61 0xc8 0x1c 0xd5 == msr {{ich_ap0r3_el2|ICH_AP0R3_EL2}}, x1
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0x7 0xc9 0x1c 0xd5 == msr {{ich_ap1r0_el2|ICH_AP1R0_EL2}}, x7
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0x2c 0xc9 0x1c 0xd5 == msr {{ich_ap1r1_el2|ICH_AP1R1_EL2}}, x12
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0x4e 0xc9 0x1c 0xd5 == msr {{ich_ap1r2_el2|ICH_AP1R2_EL2}}, x14
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0x6d 0xc9 0x1c 0xd5 == msr {{ich_ap1r3_el2|ICH_AP1R3_EL2}}, x13
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0x1 0xcb 0x1c 0xd5 == msr {{ich_hcr_el2|ICH_HCR_EL2}}, x1
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0x4a 0xcb 0x1c 0xd5 == msr S3_4_C12_C11_2, x10
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0xf8 0xcb 0x1c 0xd5 == msr {{ich_vmcr_el2|ICH_VMCR_EL2}}, x24
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0x1a 0xcc 0x1c 0xd5 == msr {{ich_lr0_el2|ICH_LR0_EL2}}, x26
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0x29 0xcc 0x1c 0xd5 == msr {{ich_lr1_el2|ICH_LR1_EL2}}, x9
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0x52 0xcc 0x1c 0xd5 == msr {{ich_lr2_el2|ICH_LR2_EL2}}, x18
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0x7a 0xcc 0x1c 0xd5 == msr {{ich_lr3_el2|ICH_LR3_EL2}}, x26
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0x96 0xcc 0x1c 0xd5 == msr {{ich_lr4_el2|ICH_LR4_EL2}}, x22
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0xba 0xcc 0x1c 0xd5 == msr {{ich_lr5_el2|ICH_LR5_EL2}}, x26
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0xdb 0xcc 0x1c 0xd5 == msr {{ich_lr6_el2|ICH_LR6_EL2}}, x27
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0xe8 0xcc 0x1c 0xd5 == msr {{ich_lr7_el2|ICH_LR7_EL2}}, x8
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0x11 0xcd 0x1c 0xd5 == msr {{ich_lr8_el2|ICH_LR8_EL2}}, x17
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0x33 0xcd 0x1c 0xd5 == msr {{ich_lr9_el2|ICH_LR9_EL2}}, x19
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0x51 0xcd 0x1c 0xd5 == msr {{ich_lr10_el2|ICH_LR10_EL2}}, x17
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0x65 0xcd 0x1c 0xd5 == msr {{ich_lr11_el2|ICH_LR11_EL2}}, x5
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0x9d 0xcd 0x1c 0xd5 == msr {{ich_lr12_el2|ICH_LR12_EL2}}, x29
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0xa2 0xcd 0x1c 0xd5 == msr {{ich_lr13_el2|ICH_LR13_EL2}}, x2
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0xcd 0xcd 0x1c 0xd5 == msr {{ich_lr14_el2|ICH_LR14_EL2}}, x13
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0xfb 0xcd 0x1c 0xd5 == msr {{ich_lr15_el2|ICH_LR15_EL2}}, x27
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