3621a6c080
b102f1b8 Update Actions (#2593) 86293136 Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support (#2594) 27da950c Clarify between machine used vs. Capstone module affected. (#2586) 186f7aa0 Fix linking issue on Windows. (#2587) e160cbc5 Fix complex atomic instructions handling (#2584) 9907b22d Update v6 to have Debian Packages (#2579) efbbc3bb cstest: use DOWNLOAD_EXTRACT_TIMESTAMP conditionally (#2581) be6be784 x86: update read/write registers for transfer instructions (#2578) 812e654c Update BPF arch (#2568) 2c4b05f6 Clean up the cstest documentation and build instructions. (#2580) 4dc14ba1 Fix 2572 (#2574) b25aa841 PPC regressions (#2575) 0a29bf80 Small arm64 compat header fixes (#2563) b42e0903 Make thumb, v8 and m-class positional cstool arguments. (#2557) 89aee400 Add arm64 and sysz compatibility layer to Python bindings (#2559) a4281337 Python bindings: Enable more archs + bump cibuildwheel action to the v2.22.0 (#2558) ef74d449 Arm regressions (#2556) 93a104c0 PPC LLVM 18 (#2540) e46838ed Merge branch 'v6' into next cf3600e7 Update Changelog Version to 6.0.0-Alpha2 (#2553) b295cf57 Prepare for update (#2552) fc59da4d fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551) 7d01d7e7 Auto-Sync reproducability + ARM update (#2532) 6ad2608d Python package building rework (#2538) e3bc578d Move debian package generation to a dispatch only workflow (#2543) abbf32b4 fix coverity (#2546) 1ecfb5b0 xtensa: update to espressif/llvm-project (#2533) 379e2a41 Rename build arguments: (#2534) d7be5f9f Change CI to create Debian Package to Release (#2521) f6f96796 tricore: fixes #2474 (#2523) 09f35961 This time actually fix big endian issue. (#2530) 306d5716 Fix endianess issue during assignment. (#2528) 2cfca35e Add CC and VAS compatibility macros (#2525) 32519c01 Fix stringop-truncation warning some compilers raise. (#2522) 5026c2c4 Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64 cecb5ede Fix #2509. (#2510) f97e2705 xtensa: Fix Branch Target (#2516) 1d13a12f AArch64: Replace vararg add_cs_detail by multiple concrete functions 8b618528 Update libcyaml dependency in cstest to 1.4.2 (#2508) ea081286 Tricore EA calculation (#2504) 7db9a080 Fix cstest build with Ninja (#2506) 76242699 Only trigger on released action. (#2497) 981d648b Add hard asserts to all SStream functions and memset MCInst. (#2501) d667a627 Update labeler with Xtensa and v6 files. (#2500) 52b54ee3 Fixing UB santizer, `LITBASE` and assert errors. (#2499) 97db712c Remove irrelevant changes. (#2496) 5bd05e34 Remove irrelevant changes. (#2495) 616488c7 Update changelog for V6.0.0-Alpha1 (#2493) (#2494) c5955b92 Update changelog for V6.0.0-Alpha1 (#2493) a424e709 Be ready for V6-Alpha1 (#2492) 235ba8e0 SystemZ fixes (#2488) 5dffa75b Fix LDR not assigning immediate as memory offset. (#2487) 21f7bc85 Xtensa Support (#2380) 29d87734 Several small fixups (#2489) a34901e9 Update sponsors and remove empty file. (#2485) 3120932d Fix Coverity CID 509730: overflow before widen (#2486) 1014864d Rename CS_OPT_NO_BRANCH_OFFSET and corresponding flag to better name. (#2482) 0c90fe13 Replace `assert` with `CS_ASSERT` in modules (#2478) 823bfd53 AArch64 issues (#2473) git-subtree-dir: external/capstone git-subtree-split: b102f1b89e0455c072a751d287ab64378c14205f
116 lines
4.4 KiB
C
116 lines
4.4 KiB
C
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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ARM_OP_GROUP_LdStmModeOperand = 0,
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ARM_OP_GROUP_MandatoryInvertedPredicateOperand = 1,
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ARM_OP_GROUP_RegImmShift = 2,
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ARM_OP_GROUP_Operand = 3,
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ARM_OP_GROUP_ModImmOperand = 4,
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ARM_OP_GROUP_PredicateOperand = 5,
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ARM_OP_GROUP_SORegImmOperand = 6,
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ARM_OP_GROUP_SORegRegOperand = 7,
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ARM_OP_GROUP_SBitModifierOperand = 8,
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ARM_OP_GROUP_AddrModeImm12Operand_0 = 9,
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ARM_OP_GROUP_AddrMode2Operand = 10,
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ARM_OP_GROUP_CPInstOperand = 11,
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ARM_OP_GROUP_MandatoryPredicateOperand = 12,
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ARM_OP_GROUP_ThumbITMask = 13,
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ARM_OP_GROUP_RegisterList = 14,
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ARM_OP_GROUP_AddrMode7Operand = 15,
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ARM_OP_GROUP_GPRPairOperand = 16,
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ARM_OP_GROUP_AddrMode3Operand_0 = 17,
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ARM_OP_GROUP_PCLabel = 18,
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ARM_OP_GROUP_AddrModePCOperand = 19,
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ARM_OP_GROUP_AddrMode2OffsetOperand = 20,
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ARM_OP_GROUP_AddrMode3OffsetOperand = 21,
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ARM_OP_GROUP_AddrMode6Operand = 22,
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ARM_OP_GROUP_VectorListThreeAllLanes = 23,
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ARM_OP_GROUP_VectorListThreeSpacedAllLanes = 24,
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ARM_OP_GROUP_VectorListThree = 25,
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ARM_OP_GROUP_VectorListThreeSpaced = 26,
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ARM_OP_GROUP_VectorListFourAllLanes = 27,
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ARM_OP_GROUP_VectorListFourSpacedAllLanes = 28,
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ARM_OP_GROUP_VectorListFour = 29,
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ARM_OP_GROUP_VectorListFourSpaced = 30,
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ARM_OP_GROUP_T2SOOperand = 31,
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ARM_OP_GROUP_T2AddrModeImm8Operand_0 = 32,
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ARM_OP_GROUP_T2AddrModeImm8OffsetOperand = 33,
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ARM_OP_GROUP_T2AddrModeImm8Operand_1 = 34,
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ARM_OP_GROUP_AdrLabelOperand_0 = 35,
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ARM_OP_GROUP_VectorIndex = 36,
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ARM_OP_GROUP_BitfieldInvMaskImmOperand = 37,
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ARM_OP_GROUP_PImmediate = 38,
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ARM_OP_GROUP_VPTPredicateOperand = 39,
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ARM_OP_GROUP_CImmediate = 40,
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ARM_OP_GROUP_CPSIMod = 41,
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ARM_OP_GROUP_CPSIFlag = 42,
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ARM_OP_GROUP_MemBOption = 43,
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ARM_OP_GROUP_FPImmOperand = 44,
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ARM_OP_GROUP_InstSyncBOption = 45,
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ARM_OP_GROUP_AddrMode5Operand_0 = 46,
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ARM_OP_GROUP_CoprocOptionImm = 47,
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ARM_OP_GROUP_PostIdxImm8s4Operand = 48,
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ARM_OP_GROUP_AddrMode5Operand_1 = 49,
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ARM_OP_GROUP_AddrModeImm12Operand_1 = 50,
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ARM_OP_GROUP_AddrMode3Operand_1 = 51,
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ARM_OP_GROUP_PostIdxImm8Operand = 52,
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ARM_OP_GROUP_PostIdxRegOperand = 53,
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ARM_OP_GROUP_BankedRegOperand = 54,
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ARM_OP_GROUP_MSRMaskOperand = 55,
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ARM_OP_GROUP_MveSaturateOp = 56,
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ARM_OP_GROUP_VMOVModImmOperand = 57,
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ARM_OP_GROUP_ComplexRotationOp_180_90 = 58,
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ARM_OP_GROUP_ComplexRotationOp_90_0 = 59,
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ARM_OP_GROUP_MandatoryRestrictedPredicateOperand = 60,
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ARM_OP_GROUP_MVEVectorList_2 = 61,
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ARM_OP_GROUP_MVEVectorList_4 = 62,
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ARM_OP_GROUP_MveAddrModeRQOperand_0 = 63,
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ARM_OP_GROUP_MveAddrModeRQOperand_3 = 64,
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ARM_OP_GROUP_MveAddrModeRQOperand_1 = 65,
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ARM_OP_GROUP_MveAddrModeRQOperand_2 = 66,
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ARM_OP_GROUP_VPTMask = 67,
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ARM_OP_GROUP_PKHLSLShiftImm = 68,
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ARM_OP_GROUP_PKHASRShiftImm = 69,
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ARM_OP_GROUP_ImmPlusOneOperand = 70,
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ARM_OP_GROUP_SetendOperand = 71,
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ARM_OP_GROUP_ShiftImmOperand = 72,
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ARM_OP_GROUP_RotImmOperand = 73,
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ARM_OP_GROUP_TraceSyncBOption = 74,
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ARM_OP_GROUP_VectorListOneAllLanes = 75,
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ARM_OP_GROUP_VectorListTwoAllLanes = 76,
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ARM_OP_GROUP_NoHashImmediate = 77,
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ARM_OP_GROUP_AddrMode6OffsetOperand = 78,
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ARM_OP_GROUP_VectorListOne = 79,
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ARM_OP_GROUP_VectorListTwo = 80,
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ARM_OP_GROUP_VectorListTwoSpacedAllLanes = 81,
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ARM_OP_GROUP_VectorListTwoSpaced = 82,
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ARM_OP_GROUP_AddrMode5FP16Operand_0 = 83,
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ARM_OP_GROUP_T2AddrModeImm8s4Operand_0 = 84,
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ARM_OP_GROUP_T2AddrModeImm8s4OffsetOperand = 85,
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ARM_OP_GROUP_T2AddrModeImm8s4Operand_1 = 86,
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ARM_OP_GROUP_FBits16 = 87,
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ARM_OP_GROUP_FBits32 = 88,
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ARM_OP_GROUP_ThumbSRImm = 89,
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ARM_OP_GROUP_ThumbLdrLabelOperand = 90,
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ARM_OP_GROUP_T2AddrModeSoRegOperand = 91,
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ARM_OP_GROUP_T2AddrModeImm0_1020s4Operand = 92,
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ARM_OP_GROUP_AddrModeTBB = 93,
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ARM_OP_GROUP_AddrModeTBH = 94,
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ARM_OP_GROUP_ThumbS4ImmOperand = 95,
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ARM_OP_GROUP_AdrLabelOperand_2 = 96,
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ARM_OP_GROUP_ThumbAddrModeImm5S1Operand = 97,
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ARM_OP_GROUP_ThumbAddrModeRROperand = 98,
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ARM_OP_GROUP_ThumbAddrModeImm5S2Operand = 99,
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ARM_OP_GROUP_ThumbAddrModeImm5S4Operand = 100,
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ARM_OP_GROUP_ThumbAddrModeSPOperand = 101,
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