5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
186 lines
4.4 KiB
C
186 lines
4.4 KiB
C
/* Capstone Disassembly Engine */
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/* By Dmitry Sibirtsev <sibirtsevdl@gmail.com>, 2023 */
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#ifdef CAPSTONE_HAS_ALPHA
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#include <stdio.h> // debug
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#include <string.h>
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#include "../../Mapping.h"
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#include "../../cs_priv.h"
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#include "../../cs_simple_types.h"
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#include "../../utils.h"
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#include "AlphaLinkage.h"
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#include "AlphaMapping.h"
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#include "./AlphaDisassembler.h"
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#define GET_INSTRINFO_ENUM
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#include "AlphaGenInstrInfo.inc"
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static const insn_map insns[] = {
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#include "AlphaGenCSMappingInsn.inc"
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};
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static const map_insn_ops insn_operands[] = {
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#include "AlphaGenCSMappingInsnOp.inc"
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};
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void Alpha_init_cs_detail(MCInst *MI)
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{
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if (detail_is_set(MI)) {
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memset(get_detail(MI), 0,
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offsetof(cs_detail, alpha) + sizeof(cs_alpha));
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}
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}
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void Alpha_add_cs_detail(MCInst *MI, unsigned OpNum)
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{
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if (!detail_is_set(MI))
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return;
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cs_op_type op_type = map_get_op_type(MI, OpNum);
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if (op_type == CS_OP_IMM)
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Alpha_set_detail_op_imm(MI, OpNum, ALPHA_OP_IMM,
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MCInst_getOpVal(MI, OpNum));
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else if (op_type == CS_OP_REG)
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Alpha_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum));
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else
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CS_ASSERT_RET(0 && "Op type not handled.");
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}
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void Alpha_set_detail_op_imm(MCInst *MI, unsigned OpNum, alpha_op_type ImmType,
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int64_t Imm)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT_RET(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
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CS_ASSERT_RET(map_get_op_type(MI, OpNum) == CS_OP_IMM);
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CS_ASSERT_RET(ImmType == ALPHA_OP_IMM);
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Alpha_get_detail_op(MI, 0)->type = ImmType;
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Alpha_get_detail_op(MI, 0)->imm = Imm;
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Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
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Alpha_inc_op_count(MI);
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}
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void Alpha_set_detail_op_reg(MCInst *MI, unsigned OpNum, alpha_op_type Reg)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT_RET(!(map_get_op_type(MI, OpNum) & CS_OP_MEM));
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CS_ASSERT_RET(map_get_op_type(MI, OpNum) == CS_OP_REG);
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Alpha_get_detail_op(MI, 0)->type = ALPHA_OP_REG;
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Alpha_get_detail_op(MI, 0)->reg = Reg;
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Alpha_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
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Alpha_inc_op_count(MI);
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}
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// given internal insn id, return public instruction info
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void Alpha_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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unsigned short i;
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i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
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if (i == 0) { return; }
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insn->id = insns[i].mapid;
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if (insn->detail) {
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#ifndef CAPSTONE_DIET
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memcpy(insn->detail->regs_read, insns[i].regs_use,
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sizeof(insns[i].regs_use));
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insn->detail->regs_read_count =
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(uint8_t)count_positive(insns[i].regs_use);
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memcpy(insn->detail->regs_write, insns[i].regs_mod,
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sizeof(insns[i].regs_mod));
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insn->detail->regs_write_count =
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(uint8_t)count_positive(insns[i].regs_mod);
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memcpy(insn->detail->groups, insns[i].groups,
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sizeof(insns[i].groups));
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insn->detail->groups_count =
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(uint8_t)count_positive8(insns[i].groups);
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#endif
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}
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}
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#ifndef CAPSTONE_DIET
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static const char * const insn_names[] = {
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#include "AlphaGenCSMappingInsnName.inc"
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};
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// special alias insn
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// static name_map alias_insn_names[] = {{0, NULL}};
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#endif
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const char *Alpha_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id >= ALPHA_INS_ENDING)
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return NULL;
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if (id < ARR_SIZE(insn_names))
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return insn_names[id];
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return NULL;
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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{Alpha_GRP_INVALID, NULL},
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{Alpha_GRP_CALL, "call"},
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{Alpha_GRP_JUMP, "jump"},
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{Alpha_GRP_BRANCH_RELATIVE, "branch_relative"},
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};
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#endif
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const char *Alpha_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
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#else
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return NULL;
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#endif
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}
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const char *Alpha_getRegisterName(csh handle, unsigned int id)
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{
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return Alpha_LLVM_getRegisterName(handle, id);
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}
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void Alpha_printInst(MCInst *MI, SStream *O, void *Info)
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{
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Alpha_LLVM_printInstruction(MI, O, Info);
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}
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void Alpha_set_instr_map_data(MCInst *MI)
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{
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map_cs_id(MI, insns, ARR_SIZE(insns));
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map_implicit_reads(MI, insns);
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map_implicit_writes(MI, insns);
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map_groups(MI, insns);
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}
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bool Alpha_getInstruction(csh handle, const uint8_t *code,
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size_t code_len, MCInst *instr,
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uint16_t *size, uint64_t address, void *info)
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{
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Alpha_init_cs_detail(instr);
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DecodeStatus Result = Alpha_LLVM_getInstruction(handle, code, code_len, instr, size,
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address, info);
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Alpha_set_instr_map_data(instr);
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if (Result == MCDisassembler_SoftFail) {
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MCInst_setSoftFail(instr);
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}
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return Result != MCDisassembler_Fail;
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}
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#endif
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