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5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
114 lines
3.4 KiB
C
114 lines
3.4 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- SystemZMCTargetDesc.h - SystemZ target descriptions -----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
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#define LLVM_LIB_TARGET_SYSTEMZ_MCTARGETDESC_SYSTEMZMCTARGETDESC_H
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../MCInstPrinter.h"
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#include "../../cs_priv.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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// CS namespace begin: SystemZMC
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// Maps of asm register numbers to LLVM register numbers, with 0 indicating
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// an invalid register. In principle we could use 32-bit and 64-bit register
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// classes directly, provided that we relegated the GPR allocation order
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// in SystemZRegisterInfo.td to an AltOrder and left the default order
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// as %r0-%r15. It seems better to provide the same interface for
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// all classes though.
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extern const unsigned SystemZMC_GR32Regs[16];
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extern const unsigned SystemZMC_GRH32Regs[16];
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extern const unsigned SystemZMC_GR64Regs[16];
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extern const unsigned SystemZMC_GR128Regs[16];
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extern const unsigned SystemZMC_FP32Regs[16];
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extern const unsigned SystemZMC_FP64Regs[16];
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extern const unsigned SystemZMC_FP128Regs[16];
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extern const unsigned SystemZMC_VR32Regs[32];
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extern const unsigned SystemZMC_VR64Regs[32];
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extern const unsigned SystemZMC_VR128Regs[32];
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extern const unsigned SystemZMC_AR32Regs[16];
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extern const unsigned SystemZMC_CR64Regs[16];
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// Return the 0-based number of the first architectural register that
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// contains the given LLVM register. E.g. R1D -> 1.
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unsigned SystemZMC_getFirstReg(unsigned Reg);
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// Return the given register as a GR64.
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static inline unsigned SystemZMC_getRegAsGR64(unsigned Reg)
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{
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return SystemZMC_GR64Regs[SystemZMC_getFirstReg(Reg)];
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}
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// Return the given register as a low GR32.
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static inline unsigned SystemZMC_getRegAsGR32(unsigned Reg)
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{
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return SystemZMC_GR32Regs[SystemZMC_getFirstReg(Reg)];
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}
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// Return the given register as a high GR32.
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static inline unsigned SystemZMC_getRegAsGRH32(unsigned Reg)
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{
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return SystemZMC_GRH32Regs[SystemZMC_getFirstReg(Reg)];
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}
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// Return the given register as a VR128.
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static inline unsigned SystemZMC_getRegAsVR128(unsigned Reg)
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{
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return SystemZMC_VR128Regs[SystemZMC_getFirstReg(Reg)];
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}
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// CS namespace end: SystemZMC
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// end namespace SystemZMC
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// Defines symbolic names for SystemZ registers.
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// This defines a mapping from register name to register number.
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#define GET_REGINFO_ENUM
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#include "SystemZGenRegisterInfo.inc"
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// Defines symbolic names for the SystemZ instructions.
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_MC_HELPER_DECLS
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#include "SystemZGenInstrInfo.inc"
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#define GET_SUBTARGETINFO_ENUM
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#include "SystemZGenSubtargetInfo.inc"
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#endif
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