Files
kaizen/arch/SystemZ/SystemZMapping.c
irisz64 16a2cf3873 Squashed 'external/capstone/' changes from b102f1b8..5af28808
5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705)
99f018ac Python binding: (#2742)
a07baf83 Auto-Sync update Sparc LLVM-18 (#2704)
81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733)
a25d4980 Add warning about naive search and replace to patch reg names. (#2728)
7ac87d17 Print immediate only memory operands for AArch64. (#2732)
c34034c8 Add x30 implicit read to the RET alias. (#2739)
95a4ca3e Update source list before installing valgrind. (#2730)
6909724e Make assertion hit warnings optional in release builds. (#2729)
fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723)
21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721)
df26583f clang-format: change license to BSD-3-Clause (#2724)
280b749e Remove unused files. (#2709)
87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707)
efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720)
2ae64133 Fix missing sp register read in ret instruction (#2719)
8df252a6 Fix arm pop reg access (#2718)
14612272 ARM: fix typo, cspr -> cpsr (#2716)
f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701)
829be2bf LoongArch: Compute absolute address for address operand (#2699)
42fbce6c Add jump group for generic jirl (#2698)
fc525c73 Apple AArch64 proprietary (#2692)
895f2f2e Build PDB for debugging on Windows (#2685)
5c3aef03 Version: Update to v6.0.0-alpha4 (#2682)
106f7d3b Update read/written registers for x87 comparison instructions (#2680)
ebe3ef2a Add workflow for building on Windows (#2675)
72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678)
5b5c5ed8 Fix nanomips decoding of jalrc (#2672)
ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673)
21178aea Add a script to compare the inc file content with the latest generated ones. (#2667)
81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665)
98a393e3 Stringify BH fields when printing ppc details (#2663)
2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661)
5058c634 Decode BH field in print_insn_detail_ppc (#2662)
6461ed08 Add Call group to svc, smc and hvc. (#2651)
e2f1dc8d Tms32c64x Little Endian (#2648)
5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645)
bb2f6579 Enhance shift value and types of shift instructions. (#2638)
cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633)
dc0c0909 cmake: Fix building capstone as sub-project (#2629)
cd8dd20c - Added missing files for sdist archive (#2624)
9affd99b Give the user some guidance where to add missing enumeration values. (#2639)
1bea3fab Add checks for MIPS details on cstest_py (#2640)
ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635)
1abe1868 Build Tarball before DEB/RPM package. (#2627)
0a012190 Switch to ubuntu-24.04-arm runner image (#2625)
4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620)
8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616)
d7ef910b Rebased #2570 (#2614)
c831cd5e Fix SystemZ macro in Makefile (#2603)
30601176 Apply new EVM opcode updates (#2602)
3c4d7fc8 Add tricore tc1.8 instructions (#2595)
5f290cad Create debian and rpm package on releases (#2590)
0f09210a delete travis (#2600)
5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598)

git-subtree-dir: external/capstone
git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
2025-06-26 22:15:44 +02:00

369 lines
11 KiB
C

/* Capstone Disassembly Engine */
/* By Rot127 <unisono@quyllur.org> 2022-2023 */
#ifdef CAPSTONE_HAS_SYSTEMZ
#include <stdio.h> // debug
#include <string.h>
#include "../../Mapping.h"
#include "../../utils.h"
#include "../../cs_simple_types.h"
#include <capstone/cs_operand.h>
#include "SystemZMCTargetDesc.h"
#include "SystemZMapping.h"
#include "SystemZLinkage.h"
#ifndef CAPSTONE_DIET
static const char *const insn_name_maps[] = {
#include "SystemZGenCSMappingInsnName.inc"
};
static const name_map insn_alias_mnem_map[] = {
#include "SystemZGenCSAliasMnemMap.inc"
{ SYSTEMZ_INS_ALIAS_END, NULL },
};
static const map_insn_ops insn_operands[] = {
#include "SystemZGenCSMappingInsnOp.inc"
};
#endif
#define GET_REGINFO_MC_DESC
#include "SystemZGenRegisterInfo.inc"
const insn_map systemz_insns[] = {
#include "SystemZGenCSMappingInsn.inc"
};
void SystemZ_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen)
{
map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns));
map_implicit_reads(MI, systemz_insns);
map_implicit_writes(MI, systemz_insns);
map_groups(MI, systemz_insns);
const systemz_suppl_info *suppl_info =
map_get_suppl_info(MI, systemz_insns);
if (suppl_info) {
SystemZ_get_detail(MI)->format = suppl_info->form;
}
}
void SystemZ_init_mri(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(
MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0,
SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0,
0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists,
ARR_SIZE(SystemZSubRegIdxLists), 0);
}
const char *SystemZ_reg_name(csh handle, unsigned int reg)
{
return SystemZ_LLVM_getRegisterName(reg);
}
void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
{
MI->MRI = (MCRegisterInfo *)info;
MI->fillDetailOps = detail_is_set(MI);
SystemZ_LLVM_printInstruction(MI, "", O);
#ifndef CAPSTONE_DIET
map_set_alias_id(MI, O, insn_alias_mnem_map,
ARR_SIZE(insn_alias_mnem_map));
#endif
}
void SystemZ_init_cs_detail(MCInst *MI) {
if (!detail_is_set(MI)) {
return;
}
memset(get_detail(MI), 0, sizeof(cs_detail));
if (detail_is_set(MI)) {
SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID;
}
}
bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
MCInst *MI, uint16_t *size, uint64_t address,
void *info)
{
SystemZ_init_cs_detail(MI);
MI->MRI = (MCRegisterInfo *)info;
DecodeStatus Result = SystemZ_LLVM_getInstruction(
handle, bytes, bytes_len, MI, size, address, info);
SystemZ_set_instr_map_data(MI, bytes, bytes_len);
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(MI);
}
return Result != MCDisassembler_Fail;
}
// given internal insn id, return public instruction info
void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// We do this after Instruction disassembly.
}
const char *SystemZ_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) {
if (id - SYSTEMZ_INS_ALIAS_BEGIN >=
ARR_SIZE(insn_alias_mnem_map))
return NULL;
return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1]
.name;
}
if (id >= SYSTEMZ_INS_ENDING)
return NULL;
if (id < ARR_SIZE(insn_name_maps))
return insn_name_maps[id];
// not found
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
// generic groups
{ SYSTEMZ_GRP_INVALID, NULL },
{ SYSTEMZ_GRP_JUMP, "jump" },
{ SYSTEMZ_GRP_CALL, "call" },
{ SYSTEMZ_GRP_RET, "return" },
{ SYSTEMZ_GRP_INT, "int" },
{ SYSTEMZ_GRP_IRET, "iret" },
{ SYSTEMZ_GRP_PRIVILEGE, "privilege" },
{ SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" },
#include "SystemZGenCSFeatureName.inc"
};
#endif
const char *SystemZ_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
void SystemZ_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
va_list args)
{
#ifndef CAPSTONE_DIET
if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
return;
unsigned op_num = va_arg(args, unsigned);
switch (op_group) {
default:
printf("Operand group %d not handled\n", op_group);
break;
case SystemZ_OP_GROUP_Operand: {
cs_op_type secondary_op_type = map_get_op_type(MI, op_num) &
~(CS_OP_MEM | CS_OP_BOUND);
if (secondary_op_type == CS_OP_IMM) {
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 0);
} else if (secondary_op_type == CS_OP_REG) {
SystemZ_set_detail_op_reg(MI, op_num,
MCInst_getOpVal(MI, op_num));
} else {
CS_ASSERT_RET(0 && "Op type not handled.");
}
break;
}
case SystemZ_OP_GROUP_Cond4Operand: {
systemz_cc cc = MCInst_getOpVal(MI, op_num);
SystemZ_get_detail(MI)->cc = cc;
break;
}
case SystemZ_OP_GROUP_BDAddrOperand:
CS_ASSERT_RET(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
CS_ASSERT_RET(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
CS_ASSERT_RET(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
CS_ASSERT_RET(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
SystemZ_set_detail_op_mem(MI,
op_num,
MCInst_getOpVal(MI, (op_num)),
MCInst_getOpVal(MI, (op_num + 1)),
0,
0,
SYSTEMZ_AM_BD
);
break;
case SystemZ_OP_GROUP_BDVAddrOperand:
case SystemZ_OP_GROUP_BDXAddrOperand: {
CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
SystemZ_set_detail_op_mem(MI,
op_num,
MCInst_getOpVal(MI, (op_num)),
MCInst_getOpVal(MI, (op_num + 1)),
0,
MCInst_getOpVal(MI, (op_num + 2)),
(op_group == SystemZ_OP_GROUP_BDXAddrOperand ? SYSTEMZ_AM_BDX : SYSTEMZ_AM_BDV)
);
break;
}
case SystemZ_OP_GROUP_BDLAddrOperand:
CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2))));
SystemZ_set_detail_op_mem(MI,
op_num,
MCInst_getOpVal(MI, (op_num)),
MCInst_getOpVal(MI, (op_num + 1)),
MCInst_getOpVal(MI, (op_num + 2)),
0,
SYSTEMZ_AM_BDL
);
break;
case SystemZ_OP_GROUP_BDRAddrOperand:
CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
SystemZ_set_detail_op_mem(MI,
op_num,
MCInst_getOpVal(MI, (op_num)),
MCInst_getOpVal(MI, (op_num + 1)),
MCInst_getOpVal(MI, (op_num + 2)),
0,
SYSTEMZ_AM_BDL
);
break;
case SystemZ_OP_GROUP_PCRelOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 0);
break;
case SystemZ_OP_GROUP_U1ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 1);
break;
case SystemZ_OP_GROUP_U2ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 2);
break;
case SystemZ_OP_GROUP_U3ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 3);
break;
case SystemZ_OP_GROUP_U4ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 4);
break;
case SystemZ_OP_GROUP_U8ImmOperand:
case SystemZ_OP_GROUP_S8ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 8);
break;
case SystemZ_OP_GROUP_U12ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 12);
break;
case SystemZ_OP_GROUP_U16ImmOperand:
case SystemZ_OP_GROUP_S16ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 16);
break;
case SystemZ_OP_GROUP_U32ImmOperand:
case SystemZ_OP_GROUP_S32ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 32);
break;
case SystemZ_OP_GROUP_U48ImmOperand:
SystemZ_set_detail_op_imm(MI, op_num,
MCInst_getOpVal(MI, op_num), 48);
break;
}
#endif
}
#ifndef CAPSTONE_DIET
void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm, size_t width)
{
if (!detail_is_set(MI))
return;
CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM);
SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
SystemZ_get_detail_op(MI, 0)->imm = Imm;
SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
SystemZ_get_detail_op(MI, 0)->imm_width = width;
SystemZ_inc_op_count(MI);
}
void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg)
{
if (!detail_is_set(MI))
return;
CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG);
SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG;
SystemZ_get_detail_op(MI, 0)->reg = Reg;
SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
SystemZ_inc_op_count(MI);
}
void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am)
{
if (!detail_is_set(MI))
return;
SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM;
SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
SystemZ_get_detail_op(MI, 0)->mem.am = am;
switch(am) {
default:
CS_ASSERT(0 && "Address mode not handled\n");
break;
case SYSTEMZ_AM_BD:
SystemZ_get_detail_op(MI, 0)->mem.base = base;
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
break;
case SYSTEMZ_AM_BDX:
case SYSTEMZ_AM_BDV:
SystemZ_get_detail_op(MI, 0)->mem.base = base;
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
SystemZ_get_detail_op(MI, 0)->mem.index = index;
break;
case SYSTEMZ_AM_BDL:
SystemZ_get_detail_op(MI, 0)->mem.base = base;
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
SystemZ_get_detail_op(MI, 0)->mem.length = length;
break;
case SYSTEMZ_AM_BDR:
SystemZ_get_detail_op(MI, 0)->mem.base = base;
SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
SystemZ_get_detail_op(MI, 0)->mem.length = length;
break;
}
SystemZ_inc_op_count(MI);
}
#endif
#endif