5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
369 lines
11 KiB
C
369 lines
11 KiB
C
/* Capstone Disassembly Engine */
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/* By Rot127 <unisono@quyllur.org> 2022-2023 */
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#ifdef CAPSTONE_HAS_SYSTEMZ
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#include <stdio.h> // debug
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#include <string.h>
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#include "../../Mapping.h"
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#include "../../utils.h"
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#include "../../cs_simple_types.h"
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#include <capstone/cs_operand.h>
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#include "SystemZMCTargetDesc.h"
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#include "SystemZMapping.h"
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#include "SystemZLinkage.h"
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#ifndef CAPSTONE_DIET
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static const char *const insn_name_maps[] = {
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#include "SystemZGenCSMappingInsnName.inc"
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};
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static const name_map insn_alias_mnem_map[] = {
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#include "SystemZGenCSAliasMnemMap.inc"
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{ SYSTEMZ_INS_ALIAS_END, NULL },
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};
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static const map_insn_ops insn_operands[] = {
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#include "SystemZGenCSMappingInsnOp.inc"
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};
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#endif
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#define GET_REGINFO_MC_DESC
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#include "SystemZGenRegisterInfo.inc"
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const insn_map systemz_insns[] = {
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#include "SystemZGenCSMappingInsn.inc"
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};
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void SystemZ_set_instr_map_data(MCInst *MI, const uint8_t *Bytes, size_t BytesLen)
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{
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map_cs_id(MI, systemz_insns, ARR_SIZE(systemz_insns));
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map_implicit_reads(MI, systemz_insns);
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map_implicit_writes(MI, systemz_insns);
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map_groups(MI, systemz_insns);
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const systemz_suppl_info *suppl_info =
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map_get_suppl_info(MI, systemz_insns);
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if (suppl_info) {
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SystemZ_get_detail(MI)->format = suppl_info->form;
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}
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}
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void SystemZ_init_mri(MCRegisterInfo *MRI)
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{
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MCRegisterInfo_InitMCRegisterInfo(
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MRI, SystemZRegDesc, AARCH64_REG_ENDING, 0, 0,
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SystemZMCRegisterClasses, ARR_SIZE(SystemZMCRegisterClasses), 0,
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0, SystemZRegDiffLists, 0, SystemZSubRegIdxLists,
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ARR_SIZE(SystemZSubRegIdxLists), 0);
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}
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const char *SystemZ_reg_name(csh handle, unsigned int reg)
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{
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return SystemZ_LLVM_getRegisterName(reg);
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}
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void SystemZ_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
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{
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MI->MRI = (MCRegisterInfo *)info;
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MI->fillDetailOps = detail_is_set(MI);
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SystemZ_LLVM_printInstruction(MI, "", O);
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#ifndef CAPSTONE_DIET
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map_set_alias_id(MI, O, insn_alias_mnem_map,
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ARR_SIZE(insn_alias_mnem_map));
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#endif
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}
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void SystemZ_init_cs_detail(MCInst *MI) {
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if (!detail_is_set(MI)) {
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return;
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}
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memset(get_detail(MI), 0, sizeof(cs_detail));
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if (detail_is_set(MI)) {
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SystemZ_get_detail(MI)->cc = SYSTEMZ_CC_INVALID;
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}
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}
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bool SystemZ_getInstruction(csh handle, const uint8_t *bytes, size_t bytes_len,
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MCInst *MI, uint16_t *size, uint64_t address,
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void *info)
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{
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SystemZ_init_cs_detail(MI);
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MI->MRI = (MCRegisterInfo *)info;
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DecodeStatus Result = SystemZ_LLVM_getInstruction(
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handle, bytes, bytes_len, MI, size, address, info);
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SystemZ_set_instr_map_data(MI, bytes, bytes_len);
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if (Result == MCDisassembler_SoftFail) {
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MCInst_setSoftFail(MI);
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}
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return Result != MCDisassembler_Fail;
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}
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// given internal insn id, return public instruction info
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void SystemZ_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
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{
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// We do this after Instruction disassembly.
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}
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const char *SystemZ_insn_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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if (id < SYSTEMZ_INS_ALIAS_END && id > SYSTEMZ_INS_ALIAS_BEGIN) {
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if (id - SYSTEMZ_INS_ALIAS_BEGIN >=
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ARR_SIZE(insn_alias_mnem_map))
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return NULL;
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return insn_alias_mnem_map[id - SYSTEMZ_INS_ALIAS_BEGIN - 1]
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.name;
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}
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if (id >= SYSTEMZ_INS_ENDING)
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return NULL;
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if (id < ARR_SIZE(insn_name_maps))
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return insn_name_maps[id];
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// not found
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return NULL;
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#else
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return NULL;
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#endif
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}
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#ifndef CAPSTONE_DIET
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static const name_map group_name_maps[] = {
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// generic groups
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{ SYSTEMZ_GRP_INVALID, NULL },
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{ SYSTEMZ_GRP_JUMP, "jump" },
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{ SYSTEMZ_GRP_CALL, "call" },
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{ SYSTEMZ_GRP_RET, "return" },
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{ SYSTEMZ_GRP_INT, "int" },
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{ SYSTEMZ_GRP_IRET, "iret" },
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{ SYSTEMZ_GRP_PRIVILEGE, "privilege" },
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{ SYSTEMZ_GRP_BRANCH_RELATIVE, "branch_relative" },
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#include "SystemZGenCSFeatureName.inc"
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};
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#endif
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const char *SystemZ_group_name(csh handle, unsigned int id)
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{
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#ifndef CAPSTONE_DIET
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return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
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#else
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return NULL;
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#endif
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}
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void SystemZ_add_cs_detail(MCInst *MI, int /* aarch64_op_group */ op_group,
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va_list args)
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{
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#ifndef CAPSTONE_DIET
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if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
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return;
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unsigned op_num = va_arg(args, unsigned);
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switch (op_group) {
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default:
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printf("Operand group %d not handled\n", op_group);
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break;
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case SystemZ_OP_GROUP_Operand: {
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cs_op_type secondary_op_type = map_get_op_type(MI, op_num) &
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~(CS_OP_MEM | CS_OP_BOUND);
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if (secondary_op_type == CS_OP_IMM) {
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 0);
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} else if (secondary_op_type == CS_OP_REG) {
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SystemZ_set_detail_op_reg(MI, op_num,
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MCInst_getOpVal(MI, op_num));
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} else {
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CS_ASSERT_RET(0 && "Op type not handled.");
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}
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break;
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}
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case SystemZ_OP_GROUP_Cond4Operand: {
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systemz_cc cc = MCInst_getOpVal(MI, op_num);
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SystemZ_get_detail(MI)->cc = cc;
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break;
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}
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case SystemZ_OP_GROUP_BDAddrOperand:
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CS_ASSERT_RET(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT_RET(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT_RET(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT_RET(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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0,
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0,
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SYSTEMZ_AM_BD
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);
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break;
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case SystemZ_OP_GROUP_BDVAddrOperand:
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case SystemZ_OP_GROUP_BDXAddrOperand: {
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CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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0,
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MCInst_getOpVal(MI, (op_num + 2)),
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(op_group == SystemZ_OP_GROUP_BDXAddrOperand ? SYSTEMZ_AM_BDX : SYSTEMZ_AM_BDV)
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);
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break;
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}
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case SystemZ_OP_GROUP_BDLAddrOperand:
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CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 2))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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MCInst_getOpVal(MI, (op_num + 2)),
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0,
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SYSTEMZ_AM_BDL
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);
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break;
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case SystemZ_OP_GROUP_BDRAddrOperand:
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CS_ASSERT(map_get_op_type(MI, (op_num)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 1)) & CS_OP_MEM);
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CS_ASSERT(map_get_op_type(MI, (op_num + 2)) & CS_OP_MEM);
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num))));
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CS_ASSERT(MCOperand_isImm(MCInst_getOperand(MI, (op_num + 1))));
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CS_ASSERT(MCOperand_isReg(MCInst_getOperand(MI, (op_num + 2))));
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SystemZ_set_detail_op_mem(MI,
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op_num,
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MCInst_getOpVal(MI, (op_num)),
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MCInst_getOpVal(MI, (op_num + 1)),
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MCInst_getOpVal(MI, (op_num + 2)),
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0,
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SYSTEMZ_AM_BDL
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);
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break;
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case SystemZ_OP_GROUP_PCRelOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 0);
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break;
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case SystemZ_OP_GROUP_U1ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 1);
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break;
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case SystemZ_OP_GROUP_U2ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 2);
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break;
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case SystemZ_OP_GROUP_U3ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 3);
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break;
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case SystemZ_OP_GROUP_U4ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 4);
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break;
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case SystemZ_OP_GROUP_U8ImmOperand:
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case SystemZ_OP_GROUP_S8ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 8);
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break;
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case SystemZ_OP_GROUP_U12ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 12);
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break;
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case SystemZ_OP_GROUP_U16ImmOperand:
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case SystemZ_OP_GROUP_S16ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 16);
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break;
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case SystemZ_OP_GROUP_U32ImmOperand:
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case SystemZ_OP_GROUP_S32ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 32);
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break;
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case SystemZ_OP_GROUP_U48ImmOperand:
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SystemZ_set_detail_op_imm(MI, op_num,
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MCInst_getOpVal(MI, op_num), 48);
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break;
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}
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#endif
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}
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#ifndef CAPSTONE_DIET
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void SystemZ_set_detail_op_imm(MCInst *MI, unsigned op_num, int64_t Imm, size_t width)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_IMM);
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SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_IMM;
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SystemZ_get_detail_op(MI, 0)->imm = Imm;
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SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
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SystemZ_get_detail_op(MI, 0)->imm_width = width;
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SystemZ_inc_op_count(MI);
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}
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void SystemZ_set_detail_op_reg(MCInst *MI, unsigned op_num, systemz_reg Reg)
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{
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if (!detail_is_set(MI))
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return;
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CS_ASSERT((map_get_op_type(MI, op_num) & ~CS_OP_MEM) == CS_OP_REG);
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SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_REG;
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SystemZ_get_detail_op(MI, 0)->reg = Reg;
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SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
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SystemZ_inc_op_count(MI);
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}
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void SystemZ_set_detail_op_mem(MCInst *MI, unsigned op_num, systemz_reg base, int64_t disp, uint64_t length, systemz_reg index, systemz_addr_mode am)
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{
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if (!detail_is_set(MI))
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return;
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SystemZ_get_detail_op(MI, 0)->type = SYSTEMZ_OP_MEM;
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SystemZ_get_detail_op(MI, 0)->access = map_get_op_access(MI, op_num);
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SystemZ_get_detail_op(MI, 0)->mem.am = am;
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switch(am) {
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default:
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CS_ASSERT(0 && "Address mode not handled\n");
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break;
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case SYSTEMZ_AM_BD:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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break;
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case SYSTEMZ_AM_BDX:
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case SYSTEMZ_AM_BDV:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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SystemZ_get_detail_op(MI, 0)->mem.index = index;
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break;
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case SYSTEMZ_AM_BDL:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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SystemZ_get_detail_op(MI, 0)->mem.length = length;
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break;
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case SYSTEMZ_AM_BDR:
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SystemZ_get_detail_op(MI, 0)->mem.base = base;
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SystemZ_get_detail_op(MI, 0)->mem.disp = disp;
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SystemZ_get_detail_op(MI, 0)->mem.length = length;
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break;
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}
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SystemZ_inc_op_count(MI);
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}
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#endif
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#endif
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