16a2cf3873
5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
1752 lines
47 KiB
C
1752 lines
47 KiB
C
//===------ TriCoreDisassembler.cpp - Disassembler for TriCore --*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2014 */
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#ifdef CAPSTONE_HAS_TRICORE
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#include <stdio.h> // DEBUG
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#include <stdlib.h>
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#include <string.h>
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "../../MCInst.h"
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#include "../../MCInstrDesc.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../MCRegisterInfo.h"
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#include "../../MCDisassembler.h"
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#include "../../MathExtras.h"
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#include "TriCoreDisassembler.h"
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#include "TriCoreMapping.h"
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#include "TriCoreLinkage.h"
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static unsigned getReg(const MCRegisterInfo *MRI, unsigned RC, unsigned RegNo)
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{
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const MCRegisterClass *rc = MCRegisterInfo_getRegClass(MRI, RC);
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return MCRegisterClass_getRegister(rc, RegNo);
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}
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#define tryDecodeReg(i, x) \
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status = DecodeRegisterClass(Inst, (x), &desc->OpInfo[(i)]); \
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if (status != MCDisassembler_Success) \
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return status;
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#define decodeImm(x) MCOperand_CreateImm0(Inst, (x));
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static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder);
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#define GET_SUBTARGETINFO_ENUM
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#include "TriCoreGenSubtargetInfo.inc"
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bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature)
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{
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switch (mode) {
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case CS_MODE_TRICORE_110: {
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return feature == TriCore_HasV110Ops;
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}
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case CS_MODE_TRICORE_120: {
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return feature == TriCore_HasV120Ops;
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}
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case CS_MODE_TRICORE_130: {
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return feature == TriCore_HasV130Ops;
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}
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case CS_MODE_TRICORE_131: {
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return feature == TriCore_HasV131Ops;
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}
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case CS_MODE_TRICORE_160: {
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return feature == TriCore_HasV160Ops;
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}
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case CS_MODE_TRICORE_161: {
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return feature == TriCore_HasV161Ops;
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}
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case CS_MODE_TRICORE_162: {
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return feature == TriCore_HasV162Ops;
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}
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case CS_MODE_TRICORE_180: {
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return feature == TriCore_HasV180Ops;
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}
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default:
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return false;
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}
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}
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#include "TriCoreGenDisassemblerTables.inc"
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#define GET_REGINFO_ENUM
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#define GET_REGINFO_MC_DESC
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#include "TriCoreGenRegisterInfo.inc"
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static DecodeStatus DecodeRegisterClass(MCInst *Inst, unsigned RegNo,
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const MCOperandInfo *MCOI)
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{
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unsigned Reg;
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unsigned RegHalfNo = RegNo / 2;
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if (!MCOI || MCOI->OperandType != MCOI_OPERAND_REGISTER) {
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return MCDisassembler_Fail;
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}
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if (RegHalfNo > 15)
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return MCDisassembler_Fail;
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if (MCOI->RegClass < 3) {
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Reg = getReg(Inst->MRI, MCOI->RegClass, RegNo);
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} else {
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Reg = getReg(Inst->MRI, MCOI->RegClass, RegHalfNo);
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}
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MCOperand_CreateReg0(Inst, Reg);
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return MCDisassembler_Success;
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}
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_MC_DESC
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#include "TriCoreGenInstrInfo.inc"
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static const MCInstrDesc *get_desc(MCInst *MI)
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{
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return TriCoreDescs.Insts +
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(ARR_SIZE(TriCoreDescs.Insts) - 1 - MCInst_getOpcode(MI));
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}
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static DecodeStatus DecodeSBInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder)
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{
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unsigned disp8 = fieldFromInstruction_2(Insn, 8, 8);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if (is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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DecodeStatus status = MCDisassembler_Success;
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const MCInstrDesc *desc = get_desc(Inst);
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if (desc->NumOperands == 2) {
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tryDecodeReg(0, 15);
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}
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MCOperand_CreateImm0(Inst, disp8);
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return status;
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}
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static DecodeStatus DecodeSBRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder)
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{
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DecodeStatus status;
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unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
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unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if (is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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const MCInstrDesc *desc = get_desc(Inst);
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if (desc->NumOperands == 3) {
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tryDecodeReg(0, 15);
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tryDecodeReg(1, s2);
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MCOperand_CreateImm0(Inst, disp4);
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} else {
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tryDecodeReg(0, s2);
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MCOperand_CreateImm0(Inst, disp4);
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}
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return status;
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}
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static DecodeStatus DecodeSCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder)
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{
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unsigned const8 = fieldFromInstruction_2(Insn, 8, 8);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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DecodeStatus status = MCDisassembler_Success;
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if (is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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const MCInstrDesc *desc = get_desc(Inst);
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switch (Insn & 0xff) {
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case 0xd8:
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case 0x58: {
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CS_ASSERT(desc->NumOperands == 3);
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tryDecodeReg(0, 15);
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tryDecodeReg(1, 10);
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decodeImm(const8);
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break;
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}
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case 0xf8:
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case 0x78: {
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CS_ASSERT(desc->NumOperands == 3);
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tryDecodeReg(0, 10);
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decodeImm(const8);
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tryDecodeReg(2, 15);
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break;
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}
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case 0x20:
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case 0x40: {
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//A[10], const8 (SC)
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CS_ASSERT(desc->NumOperands == 2);
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tryDecodeReg(0, 10);
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decodeImm(const8);
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break;
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}
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case 0x15:
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case 0xda:
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case 0x96:
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case 0x16:
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case 0xc6:
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case 0xd6: {
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CS_ASSERT(desc->NumOperands == 2);
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tryDecodeReg(0, 15);
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decodeImm(const8);
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break;
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}
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default:
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// CS_ASSERT(desc->NumOperands == 1);
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decodeImm(const8);
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break;
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}
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder)
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{
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DecodeStatus status;
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unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if (is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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const MCInstrDesc *desc = get_desc(Inst);
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if (desc->NumOperands > 0) {
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status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0]);
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if (status != MCDisassembler_Success)
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return status;
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}
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if (desc->NumOperands > 1) {
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status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1]);
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if (status != MCDisassembler_Success)
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return status;
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}
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSRCInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder)
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{
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DecodeStatus status = MCDisassembler_Success;
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unsigned const4 = fieldFromInstruction_2(Insn, 12, 4);
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unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if (is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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const MCInstrDesc *desc = get_desc(Inst);
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if (desc->NumOperands == 2) {
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tryDecodeReg(0, s1_d);
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MCOperand_CreateImm0(Inst, const4);
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} else if (desc->NumOperands == 3) {
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switch (Insn & 0xff) {
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//D[a], D[15], const4 (SRC)
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case 0x92:
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case 0x8a:
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case 0xca:
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case 0xaa:
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case 0xea: {
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tryDecodeReg(0, s1_d);
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tryDecodeReg(1, 15);
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MCOperand_CreateImm0(Inst, const4);
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break;
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}
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//D[15], D[a], const4 (SRC)
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case 0x9a:
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case 0xba:
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case 0xfa:
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case 0x86: {
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tryDecodeReg(0, 15);
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tryDecodeReg(1, s1_d);
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MCOperand_CreateImm0(Inst, const4);
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break;
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}
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}
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}
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return status;
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}
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static DecodeStatus DecodeSRRInstruction(MCInst *Inst, unsigned Insn,
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uint64_t Address, const void *Decoder)
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{
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DecodeStatus status = MCDisassembler_Success;
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unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
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unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
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unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
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if (is32Bit) // This instruction is 16-bit
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return MCDisassembler_Fail;
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const MCInstrDesc *desc = get_desc(Inst);
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if (desc->NumOperands == 2) {
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tryDecodeReg(0, s1_d);
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tryDecodeReg(1, s2);
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} else if (desc->NumOperands == 3) {
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switch (Insn & 0xff) {
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case 0x12:
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case 0x52:
|
|
case 0x2a:
|
|
case 0x6a:
|
|
case 0xa:
|
|
case 0x4a: {
|
|
//D[a], D[15], D[b] (SRR)
|
|
tryDecodeReg(0, s1_d);
|
|
tryDecodeReg(1, 15);
|
|
tryDecodeReg(2, s2);
|
|
break;
|
|
}
|
|
case 0x1a:
|
|
case 0x3a:
|
|
case 0x5a:
|
|
case 0x7a:
|
|
case 0x6: {
|
|
//D[15], D[a], D[b] (SRR)
|
|
tryDecodeReg(0, 15);
|
|
tryDecodeReg(1, s1_d);
|
|
tryDecodeReg(2, s2);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeABSInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned off18_0 = fieldFromInstruction_4(Insn, 16, 6);
|
|
unsigned off18_1 = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned off18_2 = fieldFromInstruction_4(Insn, 22, 4);
|
|
unsigned off18_3 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned off18 = (off18_0 << 0) | (off18_1 << 6) | (off18_2 << 10) |
|
|
(off18_3 << 14);
|
|
|
|
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
|
|
if (desc->NumOperands > 1) {
|
|
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
|
|
status = DecodeRegisterClass(Inst, s1_d,
|
|
&desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
MCOperand_CreateImm0(Inst, off18);
|
|
} else {
|
|
MCOperand_CreateImm0(Inst, off18);
|
|
status = DecodeRegisterClass(Inst, s1_d,
|
|
&desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
} else {
|
|
MCOperand_CreateImm0(Inst, off18);
|
|
}
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
unsigned disp24_0 = fieldFromInstruction_4(Insn, 16, 16);
|
|
unsigned disp24_1 = fieldFromInstruction_4(Insn, 8, 8);
|
|
unsigned disp24 = (disp24_0 << 0) | (disp24_1 << 16);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
// Decode disp24.
|
|
MCOperand_CreateImm0(Inst, disp24);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBOInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned off10_0 = fieldFromInstruction_4(Insn, 16, 6);
|
|
unsigned off10_1 = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned off10 = (off10_0 << 0) | (off10_1 << 6);
|
|
bool is_store = false;
|
|
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
|
|
if (desc->NumOperands == 1) {
|
|
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[0]);
|
|
}
|
|
|
|
switch (MCInst_getOpcode(Inst)) {
|
|
case TriCore_ST_A_bo_r:
|
|
case TriCore_ST_A_bo_c:
|
|
case TriCore_ST_B_bo_r:
|
|
case TriCore_ST_B_bo_c:
|
|
case TriCore_ST_D_bo_r:
|
|
case TriCore_ST_D_bo_c:
|
|
case TriCore_ST_DA_bo_r:
|
|
case TriCore_ST_DA_bo_c:
|
|
case TriCore_ST_H_bo_r:
|
|
case TriCore_ST_H_bo_c:
|
|
case TriCore_ST_Q_bo_r:
|
|
case TriCore_ST_Q_bo_c:
|
|
case TriCore_ST_W_bo_r:
|
|
case TriCore_ST_W_bo_c:
|
|
case TriCore_SWAP_W_bo_r:
|
|
case TriCore_SWAP_W_bo_c:
|
|
case TriCore_SWAPMSK_W_bo_c:
|
|
case TriCore_SWAPMSK_W_bo_r: {
|
|
is_store = true;
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (desc->NumOperands == 2) {
|
|
if (desc->OpInfo[1].OperandType == MCOI_OPERAND_REGISTER) {
|
|
// we have [reg+r] instruction
|
|
if (is_store) {
|
|
status = DecodeRegisterClass(Inst, s2,
|
|
&desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
return DecodeRegisterClass(Inst, s1_d,
|
|
&desc->OpInfo[1]);
|
|
} else {
|
|
status = DecodeRegisterClass(Inst, s1_d,
|
|
&desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
return DecodeRegisterClass(Inst, s2,
|
|
&desc->OpInfo[1]);
|
|
}
|
|
} else {
|
|
// we have one of the CACHE instructions without destination reg
|
|
status =
|
|
DecodeRegisterClass(Inst, s2, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
MCOperand_CreateImm0(Inst, off10);
|
|
}
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
if (desc->NumOperands > 2) {
|
|
if (is_store) {
|
|
// we have [reg+c] instruction
|
|
status =
|
|
DecodeRegisterClass(Inst, s2, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
status = DecodeRegisterClass(Inst, s1_d,
|
|
&desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
} else {
|
|
status = DecodeRegisterClass(Inst, s1_d,
|
|
&desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
status =
|
|
DecodeRegisterClass(Inst, s2, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
MCOperand_CreateImm0(Inst, off10);
|
|
}
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBOLInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned off16_0 = fieldFromInstruction_4(Insn, 16, 6);
|
|
unsigned off16_1 = fieldFromInstruction_4(Insn, 22, 6);
|
|
unsigned off16_2 = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned off16 = (off16_0 << 0) | (off16_1 << 10) | (off16_2 << 6);
|
|
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
|
|
switch (MCInst_getOpcode(Inst)) {
|
|
case TriCore_LD_A_bol:
|
|
case TriCore_LD_B_bol:
|
|
case TriCore_LD_BU_bol:
|
|
case TriCore_LD_H_bol:
|
|
case TriCore_LD_HU_bol:
|
|
case TriCore_LD_W_bol:
|
|
case TriCore_LEA_bol: {
|
|
// Decode s1_d.
|
|
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
break;
|
|
}
|
|
case TriCore_ST_A_bol:
|
|
case TriCore_ST_B_bol:
|
|
case TriCore_ST_H_bol:
|
|
case TriCore_ST_W_bol: {
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1_d.
|
|
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
break;
|
|
}
|
|
default:
|
|
return MCDisassembler_Fail;
|
|
}
|
|
|
|
// Decode off16.
|
|
MCOperand_CreateImm0(Inst, off16);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRCInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned const9 = fieldFromInstruction_4(Insn, 12, 9);
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
if (desc->NumOperands > 1) {
|
|
// Decode d.
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
|
|
// Decode const9.
|
|
MCOperand_CreateImm0(Inst, const9);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRCPWInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned pos = fieldFromInstruction_4(Insn, 23, 5);
|
|
unsigned width = fieldFromInstruction_4(Insn, 16, 5);
|
|
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
// Decode d.
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode const4.
|
|
MCOperand_CreateImm0(Inst, const4);
|
|
|
|
// Decode pos.
|
|
MCOperand_CreateImm0(Inst, pos);
|
|
|
|
// Decode width.
|
|
MCOperand_CreateImm0(Inst, width);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRLCInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned const16 = fieldFromInstruction_4(Insn, 12, 16);
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
if (desc->NumOperands == 3) {
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
MCOperand_CreateImm0(Inst, const16);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
MCOperand_CreateImm0(Inst, const16);
|
|
} else {
|
|
MCOperand_CreateImm0(Inst, const16);
|
|
if (MCInst_getOpcode(Inst) == TriCore_MTCR_rlc) {
|
|
status =
|
|
DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
} else {
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[1]);
|
|
}
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned n = fieldFromInstruction_4(Insn, 16, 2);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
/// But even if the instruction is in RR format and has only one operand,
|
|
/// we cannot be sure whether the operand is s1 or s2
|
|
if (desc->NumOperands == 1) {
|
|
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
|
|
switch (MCInst_getOpcode(Inst)) {
|
|
case TriCore_CALLI_rr_v110: {
|
|
return DecodeRegisterClass(Inst, s2,
|
|
&desc->OpInfo[0]);
|
|
}
|
|
default: {
|
|
return DecodeRegisterClass(Inst, s1,
|
|
&desc->OpInfo[0]);
|
|
}
|
|
}
|
|
}
|
|
return MCDisassembler_Fail;
|
|
}
|
|
|
|
if (desc->NumOperands > 0) {
|
|
// Decode d.
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
|
|
if (desc->NumOperands > 1) {
|
|
if (desc->OpInfo[0].OperandType == MCOI_OPERAND_REGISTER) {
|
|
switch (MCInst_getOpcode(Inst)) {
|
|
case TriCore_ABSS_rr:
|
|
case TriCore_ABSS_H_rr:
|
|
case TriCore_ABS_H_rr:
|
|
case TriCore_ABS_B_rr:
|
|
case TriCore_ABS_rr: {
|
|
status = DecodeRegisterClass(Inst, s2,
|
|
&desc->OpInfo[1]);
|
|
break;
|
|
}
|
|
default:
|
|
status = DecodeRegisterClass(Inst, s1,
|
|
&desc->OpInfo[1]);
|
|
}
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
}
|
|
|
|
if (desc->NumOperands > 2) {
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
|
|
if (desc->NumOperands > 3) {
|
|
MCOperand_CreateImm0(Inst, n);
|
|
}
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRR2Instruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
// Decode d.
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRRPWInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status;
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned pos = fieldFromInstruction_4(Insn, 23, 5);
|
|
unsigned width = fieldFromInstruction_4(Insn, 16, 5);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
tryDecodeReg(0, d);
|
|
tryDecodeReg(1, s1);
|
|
tryDecodeReg(2, s2);
|
|
decodeImm(pos);
|
|
decodeImm(width);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSLRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned d = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
// Decode d.
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSLROInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned d = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned off4 = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
tryDecodeReg(0, d);
|
|
if (desc->NumOperands == 3) {
|
|
tryDecodeReg(1, 15);
|
|
}
|
|
decodeImm(off4);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSROInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned off4 = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
|
|
switch (Insn & 0xff) {
|
|
case 0xcc:
|
|
case 0x0c:
|
|
case 0x8c:
|
|
case 0x4c:
|
|
case 0x48:
|
|
case 0xc8:
|
|
case 0x8:
|
|
case 0x88:
|
|
case 0x28: {
|
|
tryDecodeReg(0, 15);
|
|
tryDecodeReg(1, s2);
|
|
MCOperand_CreateImm0(Inst, off4);
|
|
break;
|
|
}
|
|
case 0xec:
|
|
case 0x2c:
|
|
case 0xac:
|
|
case 0x6c:
|
|
case 0x18:
|
|
case 0xa8:
|
|
case 0x68:
|
|
case 0xe8: {
|
|
tryDecodeReg(0, s2);
|
|
MCOperand_CreateImm0(Inst, off4);
|
|
tryDecodeReg(2, 15);
|
|
break;
|
|
}
|
|
default: {
|
|
tryDecodeReg(0, s2);
|
|
MCOperand_CreateImm0(Inst, off4);
|
|
break;
|
|
}
|
|
}
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSRRSInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned n = fieldFromInstruction_2(Insn, 6, 2);
|
|
unsigned s1_d = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
|
|
tryDecodeReg(0, s1_d);
|
|
tryDecodeReg(1, s2);
|
|
if (desc->NumOperands == 4) {
|
|
tryDecodeReg(2, 15);
|
|
}
|
|
MCOperand_CreateImm0(Inst, n);
|
|
|
|
return status;
|
|
}
|
|
|
|
static DecodeStatus DecodeSBCInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned const4 = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
if (desc->NumOperands == 3) {
|
|
tryDecodeReg(0, 15);
|
|
decodeImm(disp4);
|
|
decodeImm(const4);
|
|
} else if (desc->NumOperands == 2) {
|
|
decodeImm(disp4);
|
|
decodeImm(const4);
|
|
status = MCDisassembler_Success;
|
|
}
|
|
|
|
return status;
|
|
}
|
|
|
|
static DecodeStatus DecodeSBRNInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
unsigned disp4 = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned n = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
if (desc->NumOperands == 3) {
|
|
tryDecodeReg(0, 15);
|
|
}
|
|
|
|
// Decode n.
|
|
MCOperand_CreateImm0(Inst, n);
|
|
// Decode disp4.
|
|
MCOperand_CreateImm0(Inst, disp4);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSSRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeSSROInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_2(Insn, 8, 4);
|
|
unsigned off4 = fieldFromInstruction_2(Insn, 12, 4);
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (is32Bit) // This instruction is 16-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
CS_ASSERT_RET_VAL(desc->NumOperands == 3, MCDisassembler_Fail);
|
|
|
|
tryDecodeReg(0, 15);
|
|
tryDecodeReg(1, s1);
|
|
MCOperand_CreateImm0(Inst, off4);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
/// 32-bit Opcode Format
|
|
|
|
static DecodeStatus DecodeSYSInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1_d = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
if (desc->NumOperands > 0) {
|
|
status = DecodeRegisterClass(Inst, s1_d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRRR2Instruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s3.
|
|
status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRRR1Instruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned n = fieldFromInstruction_4(Insn, 16, 2);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s3.
|
|
status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode n.
|
|
MCOperand_CreateImm0(Inst, n);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBITInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned pos1 = fieldFromInstruction_4(Insn, 16, 5);
|
|
unsigned pos2 = fieldFromInstruction_4(Insn, 23, 5);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode pos1.
|
|
MCOperand_CreateImm0(Inst, pos1);
|
|
|
|
// Decode pos2.
|
|
MCOperand_CreateImm0(Inst, pos2);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRR1Instruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned n = fieldFromInstruction_4(Insn, 16, 2);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode n.
|
|
MCOperand_CreateImm0(Inst, n);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRCRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned const9 = fieldFromInstruction_4(Insn, 12, 9);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s3.
|
|
status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode const9.
|
|
MCOperand_CreateImm0(Inst, const9);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRRRWInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned width = fieldFromInstruction_4(Insn, 16, 5);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s3.
|
|
status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode width.
|
|
MCOperand_CreateImm0(Inst, width);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRCRRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode const4.
|
|
MCOperand_CreateImm0(Inst, const4);
|
|
|
|
// Decode s3.
|
|
status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRRRRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
if (desc->NumOperands == 3) {
|
|
switch (MCInst_getOpcode(Inst)) {
|
|
case TriCore_EXTR_rrrr:
|
|
case TriCore_EXTR_U_rrrr:
|
|
return DecodeRegisterClass(Inst, s3, &desc->OpInfo[2]);
|
|
default:
|
|
return DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
}
|
|
}
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
// Decode s3.
|
|
status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBRRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
if (MCInst_getOpcode(Inst) == TriCore_LOOP_brr) {
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
MCOperand_CreateImm0(Inst, disp15);
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
if (desc->NumOperands >= 2) {
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
if (desc->NumOperands >= 3) {
|
|
status =
|
|
DecodeRegisterClass(Inst, s2, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
}
|
|
}
|
|
|
|
// Decode disp15.
|
|
MCOperand_CreateImm0(Inst, disp15);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBRCInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode const4.
|
|
MCOperand_CreateImm0(Inst, const4);
|
|
|
|
// Decode disp15.
|
|
MCOperand_CreateImm0(Inst, disp15);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRRRInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned s2 = fieldFromInstruction_4(Insn, 12, 4);
|
|
// unsigned n = fieldFromInstruction_4(Insn, 16, 2);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, d, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s1.
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[1]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s2.
|
|
status = DecodeRegisterClass(Inst, s2, &desc->OpInfo[2]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode s3.
|
|
status = DecodeRegisterClass(Inst, s3, &desc->OpInfo[3]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeABSBInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
unsigned bpos3 = fieldFromInstruction_4(Insn, 8, 3);
|
|
unsigned b = fieldFromInstruction_4(Insn, 12, 1);
|
|
|
|
unsigned off18_0_5 = fieldFromInstruction_4(Insn, 16, 6);
|
|
unsigned off18_6_9 = fieldFromInstruction_4(Insn, 28, 4);
|
|
unsigned off18_10_13 = fieldFromInstruction_4(Insn, 22, 4);
|
|
unsigned off18_14_17 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned off18 = (off18_0_5 << 0) | (off18_6_9 << 6) |
|
|
(off18_10_13 << 10) | (off18_14_17 << 14);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
decodeImm(off18) decodeImm(bpos3) decodeImm(b)
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeRCRWInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
unsigned const4 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned width = fieldFromInstruction_4(Insn, 16, 5);
|
|
unsigned s3 = fieldFromInstruction_4(Insn, 24, 4);
|
|
unsigned d = fieldFromInstruction_4(Insn, 28, 4);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
tryDecodeReg(0, d);
|
|
tryDecodeReg(1, s1);
|
|
tryDecodeReg(2, s3);
|
|
decodeImm(const4);
|
|
decodeImm(width);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus DecodeBRNInstruction(MCInst *Inst, unsigned Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
DecodeStatus status = MCDisassembler_Success;
|
|
unsigned s1 = fieldFromInstruction_4(Insn, 8, 4);
|
|
|
|
unsigned n_0_3 = fieldFromInstruction_4(Insn, 12, 4);
|
|
unsigned n_4 = fieldFromInstruction_4(Insn, 7, 1);
|
|
unsigned n = (n_0_3 << 0) | (n_4 << 4);
|
|
|
|
unsigned disp15 = fieldFromInstruction_4(Insn, 16, 15);
|
|
|
|
unsigned is32Bit = fieldFromInstruction_4(Insn, 0, 1);
|
|
if (!is32Bit) // This instruction is 32-bit
|
|
return MCDisassembler_Fail;
|
|
|
|
const MCInstrDesc *desc = get_desc(Inst);
|
|
status = DecodeRegisterClass(Inst, s1, &desc->OpInfo[0]);
|
|
if (status != MCDisassembler_Success)
|
|
return status;
|
|
|
|
// Decode n.
|
|
MCOperand_CreateImm0(Inst, n);
|
|
|
|
// Decode disp15.
|
|
MCOperand_CreateImm0(Inst, disp15);
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
#define GET_SUBTARGETINFO_ENUM
|
|
|
|
#include "TriCoreGenInstrInfo.inc"
|
|
|
|
static inline bool decodeInstruction2_or_4(const uint8_t *code, size_t code_len,
|
|
MCInst *MI, uint16_t *size,
|
|
uint64_t address,
|
|
const uint8_t *tbl2,
|
|
const uint8_t *tbl4)
|
|
{
|
|
if (tbl2) {
|
|
if (code_len < 2) {
|
|
return false;
|
|
}
|
|
uint16_t insn2 = readBytes16(MI, code);
|
|
DecodeStatus Result =
|
|
decodeInstruction_2(tbl2, MI, insn2, address, NULL);
|
|
if (Result == MCDisassembler_Success) {
|
|
*size = 2;
|
|
return true;
|
|
}
|
|
}
|
|
|
|
if (tbl4) {
|
|
if (code_len < 4) {
|
|
return false;
|
|
}
|
|
uint32_t insn4 = readBytes32(MI, code);
|
|
DecodeStatus Result =
|
|
decodeInstruction_4(tbl4, MI, insn4, address, NULL);
|
|
if (Result == MCDisassembler_Success) {
|
|
*size = 4;
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
static bool getInstruction(csh ud, const uint8_t *code, size_t code_len,
|
|
MCInst *MI, uint16_t *size, uint64_t address)
|
|
{
|
|
if (!ud) {
|
|
return false;
|
|
}
|
|
|
|
struct cs_struct *cs = (struct cs_struct *)ud;
|
|
switch (cs->mode) {
|
|
case CS_MODE_TRICORE_110: {
|
|
if (decodeInstruction2_or_4(code, code_len, MI, size, address,
|
|
DecoderTablev11016,
|
|
DecoderTablev11032)) {
|
|
return true;
|
|
}
|
|
break;
|
|
}
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return decodeInstruction2_or_4(code, code_len, MI, size, address,
|
|
DecoderTable16, DecoderTable32);
|
|
}
|
|
|
|
bool TriCore_LLVM_getInstruction(csh handle, const uint8_t *Bytes,
|
|
size_t ByteLen, MCInst *MI, uint16_t *Size,
|
|
uint64_t Address)
|
|
{
|
|
return getInstruction(handle, Bytes, ByteLen, MI, Size, Address);
|
|
}
|
|
|
|
void TriCore_init_mri(MCRegisterInfo *MRI)
|
|
{
|
|
/*
|
|
InitMCRegisterInfo(TriCoreRegDesc, 45, RA, PC,
|
|
TriCoreMCRegisterClasses, 4,
|
|
TriCoreRegUnitRoots,
|
|
16,
|
|
TriCoreRegDiffLists,
|
|
TriCoreRegStrings,
|
|
TriCoreSubRegIdxLists,
|
|
1,
|
|
TriCoreSubRegIdxRanges,
|
|
TriCoreRegEncodingTable);
|
|
*/
|
|
|
|
MCRegisterInfo_InitMCRegisterInfo(
|
|
MRI, TriCoreRegDesc, ARR_SIZE(TriCoreRegDesc), 0, 0,
|
|
TriCoreMCRegisterClasses, ARR_SIZE(TriCoreMCRegisterClasses), 0,
|
|
0, TriCoreRegDiffLists, 0, TriCoreSubRegIdxLists,
|
|
ARR_SIZE(TriCoreSubRegIdxLists), TriCoreRegEncodingTable);
|
|
}
|
|
|
|
#endif
|