5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
160 lines
3.9 KiB
Python
160 lines
3.9 KiB
Python
# Capstone Python bindings, by Nguyen Anh Quynnh <aquynh@gmail.com>
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import ctypes
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from . import copy_ctypes_list
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from .aarch64_const import *
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# define the API
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class AArch64OpMem(ctypes.Structure):
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_fields_ = (
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('base', ctypes.c_uint),
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('index', ctypes.c_uint),
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('disp', ctypes.c_int32),
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)
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class AArch64ImmRange(ctypes.Structure):
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_fields_ = (
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('first', ctypes.c_int8),
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('offset', ctypes.c_int8),
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)
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class AArch64SMESliceOffset(ctypes.Union):
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_fields_ = (
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('imm', ctypes.c_int8),
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('imm_range', AArch64ImmRange)
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)
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class AArch64OpSme(ctypes.Structure):
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_fields_ = (
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('type', ctypes.c_uint),
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('tile', ctypes.c_uint),
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('slice_reg', ctypes.c_uint),
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('slice_offset', AArch64SMESliceOffset),
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('has_range_offset', ctypes.c_bool),
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('is_vertical', ctypes.c_bool),
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)
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class AArch64OpPred(ctypes.Structure):
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_fields_ = (
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('reg', ctypes.c_uint),
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('vec_select', ctypes.c_uint),
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('imm_index', ctypes.c_int),
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)
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class AArch64OpShift(ctypes.Structure):
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_fields_ = (
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('type', ctypes.c_uint),
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('value', ctypes.c_uint),
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)
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class AArch64SysOpSysReg(ctypes.Union):
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_fields_ = (
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('sysreg', ctypes.c_uint),
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('tlbi', ctypes.c_uint),
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('ic', ctypes.c_uint),
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('raw_val', ctypes.c_int),
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)
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class AArch64SysOpSysImm(ctypes.Union):
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_fields_ = (
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('dbnxs', ctypes.c_uint),
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('exactfpimm', ctypes.c_uint),
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('raw_val', ctypes.c_int),
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)
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class AArch64SysOpSysAlias(ctypes.Union):
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_fields_ = (
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('svcr', ctypes.c_uint),
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('at', ctypes.c_uint),
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('db', ctypes.c_uint),
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('dc', ctypes.c_uint),
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('isb', ctypes.c_uint),
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('tsb', ctypes.c_uint),
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('prfm', ctypes.c_uint),
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('sveprfm', ctypes.c_uint),
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('rprfm', ctypes.c_uint),
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('pstateimm0_15', ctypes.c_uint),
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('pstateimm0_1', ctypes.c_uint),
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('psb', ctypes.c_uint),
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('bti', ctypes.c_uint),
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('svepredpat', ctypes.c_uint),
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('sveveclenspecifier', ctypes.c_uint),
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('raw_val', ctypes.c_int),
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)
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class AArch64SysOp(ctypes.Structure):
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_fields_ = (
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('reg', AArch64SysOpSysReg),
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('imm', AArch64SysOpSysImm),
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('alias', AArch64SysOpSysAlias),
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('sub_type', ctypes.c_uint),
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)
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class AArch64OpValue(ctypes.Union):
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_fields_ = (
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('reg', ctypes.c_uint),
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('imm', ctypes.c_int64),
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('imm_range', AArch64ImmRange),
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('fp', ctypes.c_double),
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('mem', AArch64OpMem),
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('sme', AArch64OpSme),
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('pred', AArch64OpPred),
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)
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class AArch64Op(ctypes.Structure):
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_fields_ = (
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('vector_index', ctypes.c_int),
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('vas', ctypes.c_uint),
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('shift', AArch64OpShift),
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('ext', ctypes.c_uint),
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('type', ctypes.c_uint),
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('is_vreg', ctypes.c_bool),
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('value', AArch64OpValue),
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('sysop', AArch64SysOp),
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('access', ctypes.c_uint),
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('is_list_member', ctypes.c_bool),
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)
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@property
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def imm(self):
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return self.value.imm
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@property
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def reg(self):
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return self.value.reg
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@property
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def fp(self):
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return self.value.fp
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@property
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def mem(self):
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return self.value.mem
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@property
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def imm_range(self):
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return self.value.imm_range
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@property
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def sysop(self):
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return self.sysop
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@property
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def sme(self):
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return self.value.sme
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class CsAArch64(ctypes.Structure):
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_fields_ = (
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('cc', ctypes.c_uint),
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('update_flags', ctypes.c_bool),
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('post_index', ctypes.c_bool),
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('is_doing_sme', ctypes.c_bool),
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('op_count', ctypes.c_uint8),
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('operands', AArch64Op * 8),
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)
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def get_arch_info(a):
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return (a.cc, a.update_flags, a.post_index, copy_ctypes_list(a.operands[:a.op_count]))
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