5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
153 lines
4.6 KiB
C
153 lines
4.6 KiB
C
/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
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#ifndef CS_PRIV_H
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#define CS_PRIV_H
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#ifdef CAPSTONE_DEBUG
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#include <assert.h>
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#endif
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#include <capstone/capstone.h>
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#include "MCInst.h"
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#include "SStream.h"
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typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info);
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// function to be called after Printer_t
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// this is the best time to gather insn's characteristics
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typedef void (*PostPrinter_t)(csh handle, cs_insn *, SStream *mnem, MCInst *mci);
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typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
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typedef const char *(*GetName_t)(csh handle, unsigned int id);
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typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
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// return registers accessed by instruction
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typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
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cs_regs regs_read, uint8_t *regs_read_count,
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cs_regs regs_write, uint8_t *regs_write_count);
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// for ARM only
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typedef struct ARM_ITBlock {
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unsigned char ITStates[8];
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unsigned int size;
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} ARM_ITBlock;
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typedef struct ARM_VPTBlock {
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unsigned char VPTStates[8];
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unsigned int size;
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} ARM_VPTBlock;
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// Customize mnemonic for instructions with alternative name.
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struct customized_mnem {
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// ID of instruction to be customized.
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unsigned int id;
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// Customized instruction mnemonic.
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char mnemonic[CS_MNEMONIC_SIZE];
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};
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struct insn_mnem {
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struct customized_mnem insn;
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struct insn_mnem *next; // linked list of customized mnemonics
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};
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struct cs_struct {
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cs_arch arch;
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cs_mode mode;
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Printer_t printer; // asm printer
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void *printer_info; // aux info for printer
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Disasm_t disasm; // disassembler
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void *getinsn_info; // auxiliary info for printer
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GetName_t reg_name;
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GetName_t insn_name;
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GetName_t group_name;
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GetID_t insn_id;
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PostPrinter_t post_printer;
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cs_err errnum;
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ARM_ITBlock ITBlock; // for Arm only
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ARM_VPTBlock VPTBlock; // for ARM only
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bool PrintBranchImmAsAddress;
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bool ShowVSRNumsAsVR;
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cs_opt_value detail_opt, imm_unsigned;
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int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
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bool doing_mem; // handling memory operand in InstPrinter code
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bool doing_SME_Index; // handling a SME instruction that has index
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unsigned short *insn_cache; // index caching for mapping.c
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bool skipdata; // set this to True if we skip data when disassembling
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uint8_t skipdata_size; // how many bytes to skip
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cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
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const uint8_t *regsize_map; // map to register size (x86-only for now)
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GetRegisterAccess_t reg_access;
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struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic
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uint32_t LITBASE; ///< The LITBASE register content. Bit 0 (LSB) indicatess if it is set. Bit[23:8] are the literal base address.
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};
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#define MAX_ARCH CS_ARCH_MAX
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// Returns a bool (0 or 1) whether big endian is enabled for a mode
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#define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0)
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/// Returns true of the 16bit flag is set.
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#define IS_16BIT(mode) ((mode & CS_MODE_16) != 0)
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/// Returns true of the 32bit flag is set.
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#define IS_32BIT(mode) ((mode & CS_MODE_32) != 0)
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/// Returns true of the 64bit flag is set.
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#define IS_64BIT(mode) ((mode & CS_MODE_64) != 0)
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extern cs_malloc_t cs_mem_malloc;
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extern cs_calloc_t cs_mem_calloc;
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extern cs_realloc_t cs_mem_realloc;
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extern cs_free_t cs_mem_free;
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extern cs_vsnprintf_t cs_vsnprintf;
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/// By defining CAPSTONE_DEBUG assertions can be used.
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/// For the release build the @expr is not included.
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#ifdef CAPSTONE_DEBUG
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#define CS_ASSERT(expr) assert(expr)
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#elif CAPSTONE_ASSERTION_WARNINGS
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#define CS_ASSERT(expr) \
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do { \
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if (!(expr)) { \
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fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
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} \
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} while(0)
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#else
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#define CS_ASSERT(expr)
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#endif
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/// If compiled in debug mode it will assert(@expr).
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/// In the release build it will check the @expr and return @val if false.
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#ifdef CAPSTONE_DEBUG
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#define CS_ASSERT_RET_VAL(expr, val) assert(expr)
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#elif CAPSTONE_ASSERTION_WARNINGS
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#define CS_ASSERT_RET_VAL(expr, val) \
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do { \
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if (!(expr)) { \
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fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
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return val; \
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} \
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} while(0)
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#else
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#define CS_ASSERT_RET_VAL(expr, val)
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#endif
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/// If compiled in debug mode it will assert(@expr).
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/// In the release build it will check the @expr and return if false.
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#ifdef CAPSTONE_DEBUG
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#define CS_ASSERT_RET(expr) assert(expr)
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#elif CAPSTONE_ASSERTION_WARNINGS
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#define CS_ASSERT_RET(expr) \
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do { \
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if (!(expr)) { \
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fprintf(stderr, "Capstone hit the assert: \"" #expr "\": %s:%" PRIu32 "\n", __FILE__, __LINE__); \
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return; \
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} \
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} while(0)
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#else
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#define CS_ASSERT_RET(expr)
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#endif
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#endif
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