Files
kaizen/cstool/cstool_powerpc.c
irisz64 16a2cf3873 Squashed 'external/capstone/' changes from b102f1b8..5af28808
5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705)
99f018ac Python binding: (#2742)
a07baf83 Auto-Sync update Sparc LLVM-18 (#2704)
81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733)
a25d4980 Add warning about naive search and replace to patch reg names. (#2728)
7ac87d17 Print immediate only memory operands for AArch64. (#2732)
c34034c8 Add x30 implicit read to the RET alias. (#2739)
95a4ca3e Update source list before installing valgrind. (#2730)
6909724e Make assertion hit warnings optional in release builds. (#2729)
fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723)
21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721)
df26583f clang-format: change license to BSD-3-Clause (#2724)
280b749e Remove unused files. (#2709)
87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707)
efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720)
2ae64133 Fix missing sp register read in ret instruction (#2719)
8df252a6 Fix arm pop reg access (#2718)
14612272 ARM: fix typo, cspr -> cpsr (#2716)
f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701)
829be2bf LoongArch: Compute absolute address for address operand (#2699)
42fbce6c Add jump group for generic jirl (#2698)
fc525c73 Apple AArch64 proprietary (#2692)
895f2f2e Build PDB for debugging on Windows (#2685)
5c3aef03 Version: Update to v6.0.0-alpha4 (#2682)
106f7d3b Update read/written registers for x87 comparison instructions (#2680)
ebe3ef2a Add workflow for building on Windows (#2675)
72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678)
5b5c5ed8 Fix nanomips decoding of jalrc (#2672)
ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673)
21178aea Add a script to compare the inc file content with the latest generated ones. (#2667)
81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665)
98a393e3 Stringify BH fields when printing ppc details (#2663)
2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661)
5058c634 Decode BH field in print_insn_detail_ppc (#2662)
6461ed08 Add Call group to svc, smc and hvc. (#2651)
e2f1dc8d Tms32c64x Little Endian (#2648)
5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645)
bb2f6579 Enhance shift value and types of shift instructions. (#2638)
cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633)
dc0c0909 cmake: Fix building capstone as sub-project (#2629)
cd8dd20c - Added missing files for sdist archive (#2624)
9affd99b Give the user some guidance where to add missing enumeration values. (#2639)
1bea3fab Add checks for MIPS details on cstest_py (#2640)
ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635)
1abe1868 Build Tarball before DEB/RPM package. (#2627)
0a012190 Switch to ubuntu-24.04-arm runner image (#2625)
4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620)
8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616)
d7ef910b Rebased #2570 (#2614)
c831cd5e Fix SystemZ macro in Makefile (#2603)
30601176 Apply new EVM opcode updates (#2602)
3c4d7fc8 Add tricore tc1.8 instructions (#2595)
5f290cad Create debian and rpm package on releases (#2590)
0f09210a delete travis (#2600)
5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598)

git-subtree-dir: external/capstone
git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
2025-06-26 22:15:44 +02:00

200 lines
5.0 KiB
C

/* Capstone Disassembler Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013> */
#include <stdio.h>
#include <capstone/capstone.h>
#include "capstone/ppc.h"
#include "cstool.h"
static const char* get_pred_name(ppc_pred pred)
{
switch(pred) {
default:
return ("invalid");
case PPC_PRED_LT:
case PPC_PRED_LT_MINUS:
case PPC_PRED_LT_PLUS:
case PPC_PRED_LT_RESERVED:
return ("lt");
case PPC_PRED_LE:
case PPC_PRED_LE_MINUS:
case PPC_PRED_LE_PLUS:
case PPC_PRED_LE_RESERVED:
return ("le");
case PPC_PRED_EQ:
case PPC_PRED_EQ_MINUS:
case PPC_PRED_EQ_PLUS:
case PPC_PRED_EQ_RESERVED:
return ("eq");
case PPC_PRED_GE:
case PPC_PRED_GE_MINUS:
case PPC_PRED_GE_PLUS:
case PPC_PRED_GE_RESERVED:
return ("ge");
case PPC_PRED_GT:
case PPC_PRED_GT_MINUS:
case PPC_PRED_GT_PLUS:
case PPC_PRED_GT_RESERVED:
return ("gt");
case PPC_PRED_NE:
case PPC_PRED_NE_MINUS:
case PPC_PRED_NE_PLUS:
case PPC_PRED_NE_RESERVED:
return ("ne");
case PPC_PRED_UN: // PPC_PRED_SO
case PPC_PRED_UN_MINUS:
case PPC_PRED_UN_PLUS:
case PPC_PRED_UN_RESERVED:
return ("so/un");
case PPC_PRED_NU: // PPC_PRED_NS
case PPC_PRED_NU_MINUS:
case PPC_PRED_NU_PLUS:
case PPC_PRED_NU_RESERVED:
return ("ns/nu");
case PPC_PRED_NZ:
case PPC_PRED_NZ_MINUS:
case PPC_PRED_NZ_PLUS:
case PPC_PRED_NZ_RESERVED:
return ("nz");
case PPC_PRED_Z:
case PPC_PRED_Z_MINUS:
case PPC_PRED_Z_PLUS:
case PPC_PRED_Z_RESERVED:
return ("z");
case PPC_PRED_BIT_SET:
return "bit-set";
case PPC_PRED_BIT_UNSET:
return "bit-unset";
}
}
static const char *get_pred_hint(ppc_br_hint at) {
switch (at) {
default:
return "invalid";
case PPC_BR_NOT_GIVEN:
return "not-given";
case PPC_BR_TAKEN:
return "likely-taken";
case PPC_BR_NOT_TAKEN:
return "likely-not-taken";
case PPC_BR_RESERVED:
return "reserved";
}
}
void print_insn_detail_ppc(csh handle, cs_insn *ins)
{
cs_ppc *ppc;
int i;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
ppc = &(ins->detail->ppc);
if (ppc->op_count)
printf("\top_count: %u\n", ppc->op_count);
for (i = 0; i < ppc->op_count; i++) {
cs_ppc_op *op = &(ppc->operands[i]);
switch((int)op->type) {
default:
break;
case PPC_OP_REG:
printf("\t\toperands[%u].type: REG = %s\n", i, cs_reg_name(handle, op->reg));
break;
case PPC_OP_IMM:
printf("\t\toperands[%u].type: IMM = 0x%"PRIx64"\n", i, op->imm);
break;
case PPC_OP_MEM:
printf("\t\toperands[%u].type: MEM\n", i);
if (op->mem.base != PPC_REG_INVALID)
printf("\t\t\toperands[%u].mem.base: REG = %s\n",
i, cs_reg_name(handle, op->mem.base));
if (op->mem.offset != PPC_REG_INVALID)
printf("\t\t\toperands[%u].mem.offset: REG = %s\n", i,
cs_reg_name(handle, op->mem.offset));
if (op->mem.disp != 0)
printf("\t\t\toperands[%u].mem.disp: 0x%x\n", i, op->mem.disp);
break;
}
switch(op->access) {
default:
break;
case CS_AC_READ:
printf("\t\toperands[%u].access: READ\n", i);
break;
case CS_AC_WRITE:
printf("\t\toperands[%u].access: WRITE\n", i);
break;
case CS_AC_READ_WRITE:
printf("\t\toperands[%u].access: READ | WRITE\n", i);
break;
}
}
if (ppc->bc.pred_cr != PPC_PRED_INVALID ||
ppc->bc.pred_ctr != PPC_PRED_INVALID) {
printf("\tBranch:\n");
printf("\t\tbi: %u\n", ppc->bc.bi);
printf("\t\tbo: %u\n", ppc->bc.bo);
if (ppc->bc.bh != PPC_BH_INVALID) {
char const* msg = NULL;
switch(ppc->bc.bh) {
case PPC_BH_SUBROUTINE_RET:
msg = "subroutine return";
break;
case PPC_BH_NO_SUBROUTINE_RET:
msg = "not a subroutine return";
break;
case PPC_BH_NOT_PREDICTABLE:
msg = "unpredictable";
break;
case PPC_BH_RESERVED:
msg = "reserved";
break;
case PPC_BH_INVALID: break;
}
printf("\t\tbh: %s\n", msg);
}
if (ppc->bc.pred_cr != PPC_PRED_INVALID) {
printf("\t\tcrX: %s\n", cs_reg_name(handle, ppc->bc.crX));
printf("\t\tpred CR-bit: %s\n", get_pred_name(ppc->bc.pred_cr));
}
if (ppc->bc.pred_ctr != PPC_PRED_INVALID)
printf("\t\tpred CTR: %s\n", get_pred_name(ppc->bc.pred_ctr));
if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
printf("\t\thint: %s\n", get_pred_hint(ppc->bc.hint));
}
if (ppc->bc.hint != PPC_BR_NOT_GIVEN)
printf("\tBranch hint (at bits): %u\n", ppc->bc.hint);
if (ppc->update_cr0)
printf("\tUpdate-CR0: True\n");
uint16_t *regs_read = ins->detail->regs_read;
uint16_t *regs_write = ins->detail->regs_write;
uint8_t regs_read_count = ins->detail->regs_read_count;
uint8_t regs_write_count = ins->detail->regs_write_count;
// Print out all registers accessed by this instruction (either implicit or explicit)
if (regs_read_count) {
printf("\tImplicit registers read:");
for(i = 0; i < regs_read_count; i++) {
printf(" %s", cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tImplicit registers modified:");
for(i = 0; i < regs_write_count; i++) {
printf(" %s", cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}