Files
kaizen/cstool/cstool_xtensa.c
irisz64 16a2cf3873 Squashed 'external/capstone/' changes from b102f1b8..5af28808
5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705)
99f018ac Python binding: (#2742)
a07baf83 Auto-Sync update Sparc LLVM-18 (#2704)
81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733)
a25d4980 Add warning about naive search and replace to patch reg names. (#2728)
7ac87d17 Print immediate only memory operands for AArch64. (#2732)
c34034c8 Add x30 implicit read to the RET alias. (#2739)
95a4ca3e Update source list before installing valgrind. (#2730)
6909724e Make assertion hit warnings optional in release builds. (#2729)
fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723)
21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721)
df26583f clang-format: change license to BSD-3-Clause (#2724)
280b749e Remove unused files. (#2709)
87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707)
efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720)
2ae64133 Fix missing sp register read in ret instruction (#2719)
8df252a6 Fix arm pop reg access (#2718)
14612272 ARM: fix typo, cspr -> cpsr (#2716)
f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701)
829be2bf LoongArch: Compute absolute address for address operand (#2699)
42fbce6c Add jump group for generic jirl (#2698)
fc525c73 Apple AArch64 proprietary (#2692)
895f2f2e Build PDB for debugging on Windows (#2685)
5c3aef03 Version: Update to v6.0.0-alpha4 (#2682)
106f7d3b Update read/written registers for x87 comparison instructions (#2680)
ebe3ef2a Add workflow for building on Windows (#2675)
72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678)
5b5c5ed8 Fix nanomips decoding of jalrc (#2672)
ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673)
21178aea Add a script to compare the inc file content with the latest generated ones. (#2667)
81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665)
98a393e3 Stringify BH fields when printing ppc details (#2663)
2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661)
5058c634 Decode BH field in print_insn_detail_ppc (#2662)
6461ed08 Add Call group to svc, smc and hvc. (#2651)
e2f1dc8d Tms32c64x Little Endian (#2648)
5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645)
bb2f6579 Enhance shift value and types of shift instructions. (#2638)
cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633)
dc0c0909 cmake: Fix building capstone as sub-project (#2629)
cd8dd20c - Added missing files for sdist archive (#2624)
9affd99b Give the user some guidance where to add missing enumeration values. (#2639)
1bea3fab Add checks for MIPS details on cstest_py (#2640)
ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635)
1abe1868 Build Tarball before DEB/RPM package. (#2627)
0a012190 Switch to ubuntu-24.04-arm runner image (#2625)
4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620)
8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616)
d7ef910b Rebased #2570 (#2614)
c831cd5e Fix SystemZ macro in Makefile (#2603)
30601176 Apply new EVM opcode updates (#2602)
3c4d7fc8 Add tricore tc1.8 instructions (#2595)
5f290cad Create debian and rpm package on releases (#2590)
0f09210a delete travis (#2600)
5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598)

git-subtree-dir: external/capstone
git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
2025-06-26 22:15:44 +02:00

93 lines
2.9 KiB
C

/* Capstone Disassembly Engine */
/* By billow <billow.fun@gmail.com>, 2024 */
#include <stdio.h>
#include <capstone/capstone.h>
#include <capstone/xtensa.h>
static const char *xtensa_insn_form_strs[] = {
[XTENSA_INSN_FORM_INVALID] = "XTENSA_INSN_FORM_INVALID",
[XTENSA_INSN_FORM_RRR] = "XTENSA_INSN_FORM_RRR",
[XTENSA_INSN_FORM_RRI8] = "XTENSA_INSN_FORM_RRI8",
[XTENSA_INSN_FORM_RRRN] = "XTENSA_INSN_FORM_RRRN",
[XTENSA_INSN_FORM_AEINST24] = "XTENSA_INSN_FORM_AEINST24",
[XTENSA_INSN_FORM_BRI12] = "XTENSA_INSN_FORM_BRI12",
[XTENSA_INSN_FORM_CALL] = "XTENSA_INSN_FORM_CALL",
[XTENSA_INSN_FORM_CALLX] = "XTENSA_INSN_FORM_CALLX",
[XTENSA_INSN_FORM_EE_INST24] = "XTENSA_INSN_FORM_EE_INST24",
[XTENSA_INSN_FORM_RRI4] = "XTENSA_INSN_FORM_RRI4",
[XTENSA_INSN_FORM_RI16] = "XTENSA_INSN_FORM_RI16",
[XTENSA_INSN_FORM_RI7] = "XTENSA_INSN_FORM_RI7",
[XTENSA_INSN_FORM_RSR] = "XTENSA_INSN_FORM_RSR",
};
void print_insn_detail_xtensa(csh handle, cs_insn *ins)
{
int i;
cs_regs regs_read, regs_write;
uint8_t regs_read_count, regs_write_count;
// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
if (ins->detail == NULL)
return;
cs_xtensa *detail = &(ins->detail->xtensa);
if (detail->format && detail->format < XTENSA_INSN_FORM_MAX) {
printf("\tformat: %s\n", xtensa_insn_form_strs[detail->format]);
}
if (detail->op_count)
printf("\top_count: %u\n", detail->op_count);
for (i = 0; i < detail->op_count; i++) {
cs_xtensa_op *op = &(detail->operands[i]);
if (op->type == XTENSA_OP_REG)
printf("\t\toperands[%u].type: REG = %s\n", i,
cs_reg_name(handle, op->reg));
else if (op->type == XTENSA_OP_IMM)
printf("\t\toperands[%u].type: IMM = 0x%" PRIx32 "\n",
i, op->imm);
else if (op->type == XTENSA_OP_MEM)
printf("\t\toperands[%u].type: MEM\n"
"\t\t\t.mem.base: REG = %s\n"
"\t\t\t.mem.disp: 0x%" PRIx32 "\n",
i, cs_reg_name(handle, op->mem.base),
op->mem.disp);
else if (op->type == XTENSA_OP_L32R) {
printf("\t\toperands[%u].type: L32R\n"
"\t\t\t.l32r = %" PRIx32 "\n",
i, op->imm);
}
if (op->access & CS_AC_READ)
printf("\t\t\t.access: READ\n");
else if (op->access & CS_AC_WRITE)
printf("\t\t\t.access: WRITE\n");
else if (op->access & (CS_AC_READ | CS_AC_WRITE))
printf("\t\t\t.access: READ | WRITE\n");
}
// Print out all registers accessed by this instruction (either implicit or
// explicit)
if (!cs_regs_access(handle, ins, regs_read, &regs_read_count,
regs_write, &regs_write_count)) {
if (regs_read_count) {
printf("\tRegisters read:");
for (i = 0; i < regs_read_count; i++) {
printf(" %s",
cs_reg_name(handle, regs_read[i]));
}
printf("\n");
}
if (regs_write_count) {
printf("\tRegisters modified:");
for (i = 0; i < regs_write_count; i++) {
printf(" %s",
cs_reg_name(handle, regs_write[i]));
}
printf("\n");
}
}
}