5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705) 99f018ac Python binding: (#2742) a07baf83 Auto-Sync update Sparc LLVM-18 (#2704) 81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733) a25d4980 Add warning about naive search and replace to patch reg names. (#2728) 7ac87d17 Print immediate only memory operands for AArch64. (#2732) c34034c8 Add x30 implicit read to the RET alias. (#2739) 95a4ca3e Update source list before installing valgrind. (#2730) 6909724e Make assertion hit warnings optional in release builds. (#2729) fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723) 21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721) df26583f clang-format: change license to BSD-3-Clause (#2724) 280b749e Remove unused files. (#2709) 87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707) efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720) 2ae64133 Fix missing sp register read in ret instruction (#2719) 8df252a6 Fix arm pop reg access (#2718) 14612272 ARM: fix typo, cspr -> cpsr (#2716) f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701) 829be2bf LoongArch: Compute absolute address for address operand (#2699) 42fbce6c Add jump group for generic jirl (#2698) fc525c73 Apple AArch64 proprietary (#2692) 895f2f2e Build PDB for debugging on Windows (#2685) 5c3aef03 Version: Update to v6.0.0-alpha4 (#2682) 106f7d3b Update read/written registers for x87 comparison instructions (#2680) ebe3ef2a Add workflow for building on Windows (#2675) 72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678) 5b5c5ed8 Fix nanomips decoding of jalrc (#2672) ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673) 21178aea Add a script to compare the inc file content with the latest generated ones. (#2667) 81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665) 98a393e3 Stringify BH fields when printing ppc details (#2663) 2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661) 5058c634 Decode BH field in print_insn_detail_ppc (#2662) 6461ed08 Add Call group to svc, smc and hvc. (#2651) e2f1dc8d Tms32c64x Little Endian (#2648) 5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645) bb2f6579 Enhance shift value and types of shift instructions. (#2638) cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633) dc0c0909 cmake: Fix building capstone as sub-project (#2629) cd8dd20c - Added missing files for sdist archive (#2624) 9affd99b Give the user some guidance where to add missing enumeration values. (#2639) 1bea3fab Add checks for MIPS details on cstest_py (#2640) ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635) 1abe1868 Build Tarball before DEB/RPM package. (#2627) 0a012190 Switch to ubuntu-24.04-arm runner image (#2625) 4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620) 8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616) d7ef910b Rebased #2570 (#2614) c831cd5e Fix SystemZ macro in Makefile (#2603) 30601176 Apply new EVM opcode updates (#2602) 3c4d7fc8 Add tricore tc1.8 instructions (#2595) 5f290cad Create debian and rpm package on releases (#2590) 0f09210a delete travis (#2600) 5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598) git-subtree-dir: external/capstone git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
/* Capstone Disassembly Engine */
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/* By billow <billow.fun@gmail.com>, 2024 */
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#include <stdio.h>
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#include <capstone/capstone.h>
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#include <capstone/xtensa.h>
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static const char *xtensa_insn_form_strs[] = {
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[XTENSA_INSN_FORM_INVALID] = "XTENSA_INSN_FORM_INVALID",
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[XTENSA_INSN_FORM_RRR] = "XTENSA_INSN_FORM_RRR",
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[XTENSA_INSN_FORM_RRI8] = "XTENSA_INSN_FORM_RRI8",
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[XTENSA_INSN_FORM_RRRN] = "XTENSA_INSN_FORM_RRRN",
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[XTENSA_INSN_FORM_AEINST24] = "XTENSA_INSN_FORM_AEINST24",
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[XTENSA_INSN_FORM_BRI12] = "XTENSA_INSN_FORM_BRI12",
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[XTENSA_INSN_FORM_CALL] = "XTENSA_INSN_FORM_CALL",
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[XTENSA_INSN_FORM_CALLX] = "XTENSA_INSN_FORM_CALLX",
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[XTENSA_INSN_FORM_EE_INST24] = "XTENSA_INSN_FORM_EE_INST24",
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[XTENSA_INSN_FORM_RRI4] = "XTENSA_INSN_FORM_RRI4",
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[XTENSA_INSN_FORM_RI16] = "XTENSA_INSN_FORM_RI16",
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[XTENSA_INSN_FORM_RI7] = "XTENSA_INSN_FORM_RI7",
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[XTENSA_INSN_FORM_RSR] = "XTENSA_INSN_FORM_RSR",
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};
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void print_insn_detail_xtensa(csh handle, cs_insn *ins)
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{
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int i;
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cs_regs regs_read, regs_write;
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uint8_t regs_read_count, regs_write_count;
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// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
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if (ins->detail == NULL)
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return;
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cs_xtensa *detail = &(ins->detail->xtensa);
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if (detail->format && detail->format < XTENSA_INSN_FORM_MAX) {
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printf("\tformat: %s\n", xtensa_insn_form_strs[detail->format]);
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}
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if (detail->op_count)
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printf("\top_count: %u\n", detail->op_count);
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for (i = 0; i < detail->op_count; i++) {
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cs_xtensa_op *op = &(detail->operands[i]);
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if (op->type == XTENSA_OP_REG)
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printf("\t\toperands[%u].type: REG = %s\n", i,
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cs_reg_name(handle, op->reg));
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else if (op->type == XTENSA_OP_IMM)
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printf("\t\toperands[%u].type: IMM = 0x%" PRIx32 "\n",
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i, op->imm);
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else if (op->type == XTENSA_OP_MEM)
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printf("\t\toperands[%u].type: MEM\n"
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"\t\t\t.mem.base: REG = %s\n"
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"\t\t\t.mem.disp: 0x%" PRIx32 "\n",
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i, cs_reg_name(handle, op->mem.base),
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op->mem.disp);
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else if (op->type == XTENSA_OP_L32R) {
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printf("\t\toperands[%u].type: L32R\n"
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"\t\t\t.l32r = %" PRIx32 "\n",
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i, op->imm);
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}
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if (op->access & CS_AC_READ)
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printf("\t\t\t.access: READ\n");
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else if (op->access & CS_AC_WRITE)
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printf("\t\t\t.access: WRITE\n");
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else if (op->access & (CS_AC_READ | CS_AC_WRITE))
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printf("\t\t\t.access: READ | WRITE\n");
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}
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// Print out all registers accessed by this instruction (either implicit or
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// explicit)
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if (!cs_regs_access(handle, ins, regs_read, ®s_read_count,
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regs_write, ®s_write_count)) {
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if (regs_read_count) {
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printf("\tRegisters read:");
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for (i = 0; i < regs_read_count; i++) {
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printf(" %s",
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cs_reg_name(handle, regs_read[i]));
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}
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printf("\n");
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}
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if (regs_write_count) {
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printf("\tRegisters modified:");
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for (i = 0; i < regs_write_count; i++) {
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printf(" %s",
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cs_reg_name(handle, regs_write[i]));
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}
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printf("\n");
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}
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}
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}
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