Files
kaizen/suite/fuzz/platform.c
irisz64 16a2cf3873 Squashed 'external/capstone/' changes from b102f1b8..5af28808
5af28808 Update Auto-Sync to Python 3.13 and tree-sitter-py 24.0 (#2705)
99f018ac Python binding: (#2742)
a07baf83 Auto-Sync update Sparc LLVM-18 (#2704)
81c5c93d Enable to generate legacy MC tests for the fuzzer. (#2733)
a25d4980 Add warning about naive search and replace to patch reg names. (#2728)
7ac87d17 Print immediate only memory operands for AArch64. (#2732)
c34034c8 Add x30 implicit read to the RET alias. (#2739)
95a4ca3e Update source list before installing valgrind. (#2730)
6909724e Make assertion hit warnings optional in release builds. (#2729)
fe6bdc6e Make SStream respect the CS_OPT_UNSIGNED flag. (#2723)
21ce3624 Use cs_ac_type for operand access mode in all arches and use cs_xtensa_op_type for Xtensa operand type (#2721)
df26583f clang-format: change license to BSD-3-Clause (#2724)
280b749e Remove unused files. (#2709)
87908ece Add flag for the SoftFail case of the LLVM disassembler. (#2707)
efc0ba44 Fix missing operand for smstart, due to space replaced by tab (#2720)
2ae64133 Fix missing sp register read in ret instruction (#2719)
8df252a6 Fix arm pop reg access (#2718)
14612272 ARM: fix typo, cspr -> cpsr (#2716)
f2f0a3c3 Fix LoongArch ld/st instructions register info (#2701)
829be2bf LoongArch: Compute absolute address for address operand (#2699)
42fbce6c Add jump group for generic jirl (#2698)
fc525c73 Apple AArch64 proprietary (#2692)
895f2f2e Build PDB for debugging on Windows (#2685)
5c3aef03 Version: Update to v6.0.0-alpha4 (#2682)
106f7d3b Update read/written registers for x87 comparison instructions (#2680)
ebe3ef2a Add workflow for building on Windows (#2675)
72f7d305 Revert "Add a script to compare the inc file content with the latest generate…" (#2678)
5b5c5ed8 Fix nanomips decoding of jalrc (#2672)
ae03cca4 Mips32r6_64r632 is for both mips32r6 and mips64r6 (#2673)
21178aea Add a script to compare the inc file content with the latest generated ones. (#2667)
81a6ba03 MIPS: Fix MIPS16 decoding, wrong flags and ghost registers (#2665)
98a393e3 Stringify BH fields when printing ppc details (#2663)
2607d0f3 Remove undefined constants in riscv_const.py (#2660) (#2661)
5058c634 Decode BH field in print_insn_detail_ppc (#2662)
6461ed08 Add Call group to svc, smc and hvc. (#2651)
e2f1dc8d Tms32c64x Little Endian (#2648)
5464c91d Fix build for compilers requiring explicit static for inline functions.. (#2645)
bb2f6579 Enhance shift value and types of shift instructions. (#2638)
cd282ef5 Update operand type enums of all arch modules to the one in `capstone.h` (#2633)
dc0c0909 cmake: Fix building capstone as sub-project (#2629)
cd8dd20c - Added missing files for sdist archive (#2624)
9affd99b Give the user some guidance where to add missing enumeration values. (#2639)
1bea3fab Add checks for MIPS details on cstest_py (#2640)
ace8056c Add aliases mapping for MIPS & test for id, alias_id (#2635)
1abe1868 Build Tarball before DEB/RPM package. (#2627)
0a012190 Switch to ubuntu-24.04-arm runner image (#2625)
4e0b8c48 Fix wrong version requirement of tricore instructions: (#2620)
8ac2843b chore(version): Update Version to 6.0.0-Alpha3 (#2616)
d7ef910b Rebased #2570 (#2614)
c831cd5e Fix SystemZ macro in Makefile (#2603)
30601176 Apply new EVM opcode updates (#2602)
3c4d7fc8 Add tricore tc1.8 instructions (#2595)
5f290cad Create debian and rpm package on releases (#2590)
0f09210a delete travis (#2600)
5c5f756f Downgrade labeler to v4 due to https://github.com/actions/labeler/issues/710. (#2598)

git-subtree-dir: external/capstone
git-subtree-split: 5af288083e9f03e32723f9708c305692f866b666
2025-06-26 22:15:44 +02:00

439 lines
6.9 KiB
C

#include "platform.h"
struct platform platforms[] = {
{
// item 0
CS_ARCH_X86,
CS_MODE_32,
"X86 32 (Intel syntax)",
"x32"
},
{
// item 1
CS_ARCH_X86,
CS_MODE_64,
"X86 64 (Intel syntax)",
"x64"
},
{
// item 2
CS_ARCH_ARM,
CS_MODE_ARM,
"ARM",
"arm"
},
{
// item 3
CS_ARCH_ARM,
CS_MODE_THUMB,
"THUMB",
"thumb"
},
{
// item 4
CS_ARCH_ARM,
(cs_mode) (CS_MODE_ARM + CS_MODE_V8),
"Arm-V8",
"armv8"
},
{
// item 5
CS_ARCH_ARM,
(cs_mode) (CS_MODE_THUMB + CS_MODE_V8),
"THUMB+V8",
"thumbv8"
},
{
// item 6
CS_ARCH_ARM,
(cs_mode) (CS_MODE_THUMB + CS_MODE_MCLASS),
"Thumb-MClass",
"cortexm"
},
{
// item 7
CS_ARCH_AARCH64,
(cs_mode) 0,
"AARCH64",
"aarch64"
},
{
// item 8
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32 + CS_MODE_BIG_ENDIAN),
"MIPS-32 (Big-endian)",
"mipsbe"
},
{
// item 9
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO),
"MIPS-32 (micro)",
"mipsmicro"
},
{
//item 10
CS_ARCH_MIPS,
CS_MODE_MIPS64,
"MIPS-64-EL (Little-endian)",
"mips64"
},
{
//item 11
CS_ARCH_MIPS,
CS_MODE_MIPS32,
"MIPS-32-EL (Little-endian)",
"mips"
},
{
//item 12
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS64 + CS_MODE_BIG_ENDIAN),
"MIPS-64 (Big-endian)",
"mips64be"
},
{
//item 13
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
"MIPS-32 | Micro (Big-endian)",
"mipsbemicro"
},
{
//item 14
CS_ARCH_PPC,
CS_MODE_64 | CS_MODE_BIG_ENDIAN,
"PPC-64",
"ppc64be"
},
{
//item 15
CS_ARCH_SPARC,
CS_MODE_BIG_ENDIAN,
"Sparc",
"sparc"
},
{
//item 16
CS_ARCH_SPARC,
(cs_mode) (CS_MODE_BIG_ENDIAN + CS_MODE_V9),
"SparcV9",
"sparcv9"
},
{
//item 17
CS_ARCH_SYSTEMZ,
(cs_mode) CS_MODE_BIG_ENDIAN,
"SystemZ",
"systemz"
},
{
//item 18
CS_ARCH_XCORE,
(cs_mode) 0,
"XCore",
"xcore"
},
{
//item 19
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_BIG_ENDIAN),
"MIPS-32R6 (Big-endian)",
"mipsbe32r6"
},
{
//item 20
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO + CS_MODE_BIG_ENDIAN),
"MIPS-32R6 (Micro+Big-endian)",
"mipsbe32r6micro"
},
{
//item 21
CS_ARCH_MIPS,
CS_MODE_MIPS32R6,
"MIPS-32R6 (Little-endian)",
"mips32r6"
},
{
//item 22
CS_ARCH_MIPS,
(cs_mode) (CS_MODE_MIPS32R6 + CS_MODE_MICRO),
"MIPS-32R6 (Micro+Little-endian)",
"mips32r6micro"
},
{
//item 23
CS_ARCH_M68K,
(cs_mode) 0,
"M68K",
"m68k"
},
{
//item 24
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6809,
"M680X_M6809",
"m6809"
},
{
//item 25
CS_ARCH_EVM,
(cs_mode) 0,
"EVM",
"evm"
},
{
//item 26
CS_ARCH_MOS65XX,
(cs_mode) 0,
"MOS65XX",
"mos65xx"
},
{
//item 27
CS_ARCH_TMS320C64X,
CS_MODE_BIG_ENDIAN,
"tms320c64x",
"tms320c64x"
},
{
//item 28
CS_ARCH_WASM,
(cs_mode) 0,
"WASM",
"wasm"
},
{
//item 29
CS_ARCH_BPF,
CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_CLASSIC,
"cBPF",
"bpf"
},
{
//item 30
CS_ARCH_BPF,
CS_MODE_LITTLE_ENDIAN | CS_MODE_BPF_EXTENDED,
"eBPF",
"ebpf"
},
{
//item 31
CS_ARCH_BPF,
CS_MODE_BIG_ENDIAN | CS_MODE_BPF_CLASSIC,
"cBPF",
"bpfbe"
},
{
//item 32
CS_ARCH_BPF,
CS_MODE_BIG_ENDIAN | CS_MODE_BPF_EXTENDED,
"eBPF",
"ebpfbe"
},
{
// item 33
CS_ARCH_X86,
CS_MODE_16,
"X86 16 (Intel syntax)",
"x16"
},
{
// item 34
CS_ARCH_M68K,
CS_MODE_M68K_040,
"M68K mode 40",
"m68k40"
},
{
//item 35
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6800,
"M680X_M6800",
"m6800"
},
{
//item 36
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6801,
"M680X_M6801",
"m6801"
},
{
//item 37
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6805,
"M680X_M6805",
"m6805"
},
{
//item 38
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6808,
"M680X_M6808",
"m6808"
},
{
//item 39
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6811,
"M680X_M6811",
"m6811"
},
{
//item 40
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_CPU12,
"M680X_cpu12",
"cpu12"
},
{
//item 41
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6301,
"M680X_M6808",
"hd6301"
},
{
//item 42
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_6309,
"M680X_M6808",
"hd6309"
},
{
//item 43
CS_ARCH_M680X,
(cs_mode) CS_MODE_M680X_HCS08,
"M680X_M6808",
"hcs08"
},
{
//item 44
CS_ARCH_RISCV,
CS_MODE_RISCV32,
"RISCV",
"riscv32"
},
{
//item 45
CS_ARCH_RISCV,
CS_MODE_RISCV64,
"RISCV",
"riscv64"
},
{
//item 46
CS_ARCH_PPC,
CS_MODE_64 | CS_MODE_BIG_ENDIAN | CS_MODE_QPX,
"ppc+qpx",
"ppc64beqpx"
},
{
//item 46
CS_ARCH_PPC,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_PS,
"ppc+ps",
"ppc32beps"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_110,
"TRICORE",
"tc110"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_120,
"TRICORE",
"tc120"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_130,
"TRICORE",
"tc130"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_131,
"TRICORE",
"tc131"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_160,
"TRICORE",
"tc160"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_161,
"TRICORE",
"tc161"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_162,
"TRICORE",
"tc162"
},
{
CS_ARCH_TRICORE,
CS_MODE_32 | CS_MODE_BIG_ENDIAN | CS_MODE_TRICORE_180,
"TRICORE",
"tc180"
},
{
CS_ARCH_XTENSA,
CS_MODE_XTENSA_ESP32,
"XTENSA ESP32",
"esp32"
},
{
CS_ARCH_XTENSA,
CS_MODE_XTENSA_ESP32S2,
"XTENSA ESP32S2",
"esp32s2"
},
{
CS_ARCH_XTENSA,
CS_MODE_XTENSA_ESP8266,
"XTENSA ESP8266",
"esp8266"
},
// dummy entry to mark the end of this array.
// DO NOT DELETE THIS
{
0,
0,
NULL,
NULL,
},
};
// get length of platforms[]
unsigned int platform_len(void) {
unsigned int c;
for (c = 0; platforms[c].cstoolname; c++);
return c;
}
// get platform entry encoded n (first byte for input data of OSS fuzz)
unsigned int get_platform_entry(uint8_t n) {
unsigned len = platform_len();
if (len == 0) {
return 0;
}
return n % len;
}
// get cstoolname from encoded n (first byte for input data of OSS fuzz)
const char *get_platform_cstoolname(uint8_t n) {
return platforms[get_platform_entry(n)].cstoolname;
}