475 lines
15 KiB
C++
475 lines
15 KiB
C++
#include <log.hpp>
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#include <core/registers/Registers.hpp>
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#include <core/Interpreter.hpp>
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namespace n64 {
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Cop0::Cop0() {
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Reset();
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}
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void Cop0::Reset() {
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cause.raw = 0xB000007C;
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status.raw = 0;
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status.cu0 = 1;
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status.cu1 = 1;
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status.fr = 1;
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PRId = 0x00000B22;
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Config = 0x7006E463;
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EPC = 0xFFFFFFFFFFFFFFFFll;
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ErrorEPC = 0xFFFFFFFFFFFFFFFFll;
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wired = 0;
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index.raw = 63;
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badVaddr = 0xFFFFFFFFFFFFFFFF;
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}
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u32 Cop0::GetReg32(u8 addr) {
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switch(addr) {
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case COP0_REG_INDEX: return index.raw & INDEX_MASK;
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case COP0_REG_RANDOM: return GetRandom();
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case COP0_REG_ENTRYLO0: return entryLo0.raw;
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case COP0_REG_ENTRYLO1: return entryLo1.raw;
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case COP0_REG_CONTEXT: return context.raw;
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case COP0_REG_PAGEMASK: return pageMask.raw;
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case COP0_REG_WIRED: return wired;
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case COP0_REG_BADVADDR: return badVaddr;
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case COP0_REG_COUNT: return GetCount();
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case COP0_REG_ENTRYHI: return entryHi.raw;
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case COP0_REG_COMPARE: return compare;
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case COP0_REG_STATUS: return status.raw;
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case COP0_REG_CAUSE: return cause.raw;
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case COP0_REG_EPC: return EPC;
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case COP0_REG_PRID: return PRId;
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case COP0_REG_CONFIG: return Config;
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case COP0_REG_LLADDR: return LLAddr;
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case COP0_REG_WATCHLO: return WatchLo;
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case COP0_REG_WATCHHI: return WatchHi;
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case COP0_REG_XCONTEXT: return xcontext.raw;
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case COP0_REG_PARITY_ERR: return ParityError;
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case COP0_REG_CACHE_ERR: return CacheError;
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case COP0_REG_TAGLO: return TagLo;
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case COP0_REG_TAGHI: return TagHi;
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case COP0_REG_ERROREPC: return ErrorEPC;
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case 7: case 21: case 22:
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case 23: case 24: case 25:
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case 31: return openbus;
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default:
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Util::panic("Unsupported word read from COP0 register {}", addr);
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}
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}
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u64 Cop0::GetReg64(u8 addr) const {
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switch(addr) {
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case COP0_REG_ENTRYLO0: return entryLo0.raw;
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case COP0_REG_ENTRYLO1: return entryLo1.raw;
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case COP0_REG_CONTEXT: return context.raw;
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case COP0_REG_BADVADDR: return badVaddr;
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case COP0_REG_ENTRYHI: return entryHi.raw;
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case COP0_REG_STATUS: return status.raw;
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case COP0_REG_EPC: return EPC;
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case COP0_REG_PRID: return PRId;
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case COP0_REG_LLADDR: return LLAddr;
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case COP0_REG_XCONTEXT: return xcontext.raw & 0xFFFFFFFFFFFFFFF0;
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case COP0_REG_ERROREPC: return ErrorEPC;
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case 7: case 21: case 22:
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case 23: case 24: case 25:
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case 31: return openbus;
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default:
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Util::panic("Unsupported dword read from COP0 register {}", addr);
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}
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}
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void Cop0::SetReg32(u8 addr, u32 value) {
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openbus = value & 0xFFFFFFFF;
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switch(addr) {
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case COP0_REG_INDEX: index.raw = value & INDEX_MASK; break;
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case COP0_REG_RANDOM: break;
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case COP0_REG_ENTRYLO0:
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entryLo0.raw = value & ENTRY_LO_MASK;
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break;
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case COP0_REG_ENTRYLO1:
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entryLo1.raw = value & ENTRY_LO_MASK;
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break;
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case COP0_REG_CONTEXT:
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context.raw = (s64(s32(value)) & 0xFFFFFFFFFF800000) | (context.raw & 0x7FFFFF);
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break;
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case COP0_REG_PAGEMASK: pageMask.raw = value & PAGEMASK_MASK; break;
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case COP0_REG_WIRED: wired = value & 63; break;
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case COP0_REG_BADVADDR: break;
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case COP0_REG_COUNT: count = (u64)value << 1; break;
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case COP0_REG_ENTRYHI:
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entryHi.raw = s64(s32(value)) & ENTRY_HI_MASK;
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break;
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case COP0_REG_COMPARE:
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compare = value;
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cause.ip7 = false;
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break;
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case COP0_REG_STATUS:
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status.raw &= ~STATUS_MASK;
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status.raw |= (value & STATUS_MASK);
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Update();
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break;
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case COP0_REG_CAUSE: {
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Cop0Cause tmp{};
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tmp.raw = value;
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cause.ip0 = tmp.ip0;
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cause.ip1 = tmp.ip1;
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} break;
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case COP0_REG_EPC:
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EPC = s64(s32(value));
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break;
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case COP0_REG_PRID: break;
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case COP0_REG_CONFIG: {
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Config &= ~CONFIG_MASK;
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Config |= (value & CONFIG_MASK);
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} break;
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case COP0_REG_LLADDR: LLAddr = value; break;
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case COP0_REG_WATCHLO: WatchLo = value; break;
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case COP0_REG_WATCHHI: WatchHi = value; break;
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case COP0_REG_XCONTEXT:
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xcontext.raw = (s64(s32(value)) & 0xFFFFFFFE00000000) | (xcontext.raw & 0x1FFFFFFFF);
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break;
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case COP0_REG_PARITY_ERR: ParityError = value & 0xff; break;
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case COP0_REG_CACHE_ERR: break;
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case COP0_REG_TAGLO: TagLo = value; break;
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case COP0_REG_TAGHI: TagHi = value; break;
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case COP0_REG_ERROREPC: ErrorEPC = s64(s32(value)); break;
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case 7: case 21: case 22:
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case 23: case 24: case 25:
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case 31: break;
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default:
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Util::panic("Unsupported word write from COP0 register {}", addr);
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}
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}
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void Cop0::SetReg64(u8 addr, u64 value) {
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openbus = value;
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switch(addr) {
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case COP0_REG_ENTRYLO0: entryLo0.raw = value & ENTRY_LO_MASK; break;
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case COP0_REG_ENTRYLO1: entryLo1.raw = value & ENTRY_LO_MASK; break;
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case COP0_REG_CONTEXT:
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context.raw = (value & 0xFFFFFFFFFF800000) | (context.raw & 0x7FFFFF);
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break;
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case COP0_REG_XCONTEXT:
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xcontext.raw = (value & 0xFFFFFFFE00000000) | (xcontext.raw & 0x1FFFFFFFF);
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break;
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case COP0_REG_ENTRYHI: entryHi.raw = value & ENTRY_HI_MASK; break;
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case COP0_REG_STATUS: status.raw = value; break;
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case COP0_REG_CAUSE: {
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Cop0Cause tmp{};
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tmp.raw = value;
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cause.ip0 = tmp.ip0;
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cause.ip1 = tmp.ip1;
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} break;
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case COP0_REG_BADVADDR: break;
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case COP0_REG_EPC: EPC = (s64)value; break;
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case COP0_REG_LLADDR: LLAddr = value; break;
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case COP0_REG_ERROREPC: ErrorEPC = (s64)value; break;
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default:
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Util::panic("Unsupported dword write to COP0 register {}", addr);
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}
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}
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static FORCE_INLINE u64 getVPN(u64 addr, u64 pageMask) {
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u64 mask = pageMask | 0x1fff;
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u64 vpn = (addr & 0xFFFFFFFFFF) | ((addr >> 22) & 0x30000000000);
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return vpn & ~mask;
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}
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TLBEntry* TLBTryMatch(Registers& regs, u64 vaddr, int* match) {
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for(int i = 0; i < 32; i++) {
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TLBEntry *entry = ®s.cop0.tlb[i];
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if(entry->initialized) {
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u64 entry_vpn = getVPN(entry->entryHi.raw, entry->pageMask.raw);
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u64 vaddr_vpn = getVPN(vaddr, entry->pageMask.raw);
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bool vpn_match = entry_vpn == vaddr_vpn;
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bool asid_match = entry->global || (regs.cop0.entryHi.asid == entry->entryHi.asid);
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if (vpn_match && asid_match) {
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if (match) {
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*match = i;
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}
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return entry;
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}
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}
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}
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return nullptr;
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}
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bool ProbeTLB(Registers& regs, TLBAccessType access_type, u64 vaddr, u32& paddr, int* match) {
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TLBEntry* entry = TLBTryMatch(regs, vaddr, match);
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if(!entry) {
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regs.cop0.tlbError = MISS;
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return false;
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}
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u32 mask = (entry->pageMask.mask << 12) | 0xFFF;
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u32 odd = vaddr & (mask + 1);
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u32 pfn;
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if(!odd) {
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if(!entry->entryLo0.v) {
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regs.cop0.tlbError = INVALID;
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return false;
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}
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if(access_type == STORE && !entry->entryLo0.d) {
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regs.cop0.tlbError = MODIFICATION;
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return false;
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}
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pfn = entry->entryLo0.pfn;
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} else {
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if(!entry->entryLo1.v) {
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regs.cop0.tlbError = INVALID;
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return false;
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}
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if(access_type == STORE && !entry->entryLo1.d) {
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regs.cop0.tlbError = MODIFICATION;
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return false;
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}
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pfn = entry->entryLo1.pfn;
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}
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paddr = (pfn << 12) | (vaddr & mask);
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return true;
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}
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FORCE_INLINE bool Is64BitAddressing(Cop0& cp0, u64 addr) {
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u8 region = (addr >> 62) & 3;
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switch(region) {
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case 0b00: return cp0.status.ux;
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case 0b01: return cp0.status.sx;
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case 0b11: return cp0.status.kx;
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default: return false;
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}
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}
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void FireException(Registers& regs, ExceptionCode code, int cop, s64 pc) {
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bool old_exl = regs.cop0.status.exl;
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if(!regs.cop0.status.exl) {
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if(regs.cop0.cause.branchDelay = regs.prevDelaySlot) {
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pc -= 4;
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}
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regs.cop0.status.exl = true;
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regs.cop0.EPC = pc;
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}
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regs.cop0.cause.copError = cop;
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regs.cop0.cause.exceptionCode = static_cast<u8>(code);
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if(regs.cop0.status.bev) {
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Util::panic("BEV bit set!");
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} else {
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switch(code) {
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case ExceptionCode::Interrupt: case ExceptionCode::TLBModification:
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case ExceptionCode::AddressErrorLoad: case ExceptionCode::AddressErrorStore:
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case ExceptionCode::InstructionBusError: case ExceptionCode::DataBusError:
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case ExceptionCode::Syscall: case ExceptionCode::Breakpoint:
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case ExceptionCode::ReservedInstruction: case ExceptionCode::CoprocessorUnusable:
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case ExceptionCode::Overflow: case ExceptionCode::Trap:
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case ExceptionCode::FloatingPointError: case ExceptionCode::Watch:
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regs.SetPC32(s32(0x80000180));
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break;
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case ExceptionCode::TLBLoad: case ExceptionCode::TLBStore:
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if(old_exl || regs.cop0.tlbError == INVALID) {
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regs.SetPC32(s32(0x80000180));
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} else if(Is64BitAddressing(regs.cop0, regs.cop0.badVaddr)) {
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regs.SetPC32(s32(0x80000080));
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} else {
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regs.SetPC32(s32(0x80000000));
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}
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break;
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default: Util::panic("Unhandled exception! {}", static_cast<u8>(code));
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}
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}
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regs.cop0.Update();
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}
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void HandleTLBException(Registers& regs, u64 vaddr) {
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u64 vpn2 = (vaddr >> 13) & 0x7FFFF;
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u64 xvpn2 = (vaddr >> 13) & 0x7FFFFFF;
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regs.cop0.badVaddr = vaddr;
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regs.cop0.context.badvpn2 = vpn2;
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regs.cop0.xcontext.badvpn2 = xvpn2;
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regs.cop0.xcontext.r = (vaddr >> 62) & 3;
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regs.cop0.entryHi.vpn2 = xvpn2;
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regs.cop0.entryHi.r = (vaddr >> 62) & 3;
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}
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ExceptionCode GetTLBExceptionCode(TLBError error, TLBAccessType accessType) {
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switch(error) {
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case NONE: Util::panic("Getting TLB exception with error NONE");
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case INVALID: case MISS:
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return accessType == LOAD ?
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ExceptionCode::TLBLoad : ExceptionCode::TLBStore;
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case MODIFICATION:
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return ExceptionCode::TLBModification;
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case DISALLOWED_ADDRESS:
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return accessType == LOAD ?
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ExceptionCode::AddressErrorLoad : ExceptionCode::AddressErrorStore;
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default:
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Util::panic("Getting TLB exception for unknown error code! ({})", static_cast<u8>(error));
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}
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}
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template<class T>
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void Cop0::decode(T& cpu, u32 instr) {
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if constexpr (std::is_same_v<decltype(cpu), Interpreter&>) {
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decodeInterp(cpu.regs, instr);
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} else if constexpr (std::is_same_v<decltype(cpu), JIT&>) {
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decodeJIT(cpu, instr);
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} else {
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Util::panic("What the fuck did you just give me?!!");
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}
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}
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template void Cop0::decode<Interpreter>(Interpreter&, u32);
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template void Cop0::decode<JIT>(JIT&, u32);
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void Cop0::decodeJIT(JIT& cpu, u32 instr) {
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}
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void Cop0::decodeInterp(Registers& regs, u32 instr) {
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u8 mask_cop = (instr >> 21) & 0x1F;
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u8 mask_cop2 = instr & 0x3F;
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switch(mask_cop) {
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case 0x00: mfc0(regs, instr); break;
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case 0x01: dmfc0(regs, instr); break;
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case 0x04: mtc0(regs, instr); break;
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case 0x05: dmtc0(regs, instr); break;
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case 0x10 ... 0x1F:
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switch(mask_cop2) {
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case 0x01: tlbr(); break;
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case 0x02: tlbw(index.i); break;
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case 0x06: tlbw(GetRandom()); break;
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case 0x08: tlbp(regs); break;
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case 0x18: eret(regs); break;
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default: Util::panic("Unimplemented COP0 function {} {} ({:08X}) ({:016lX})", mask_cop2 >> 3, mask_cop2 & 7, instr, regs.oldPC);
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}
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break;
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default: Util::panic("Unimplemented COP0 instruction {} {}", mask_cop >> 4, mask_cop & 7);
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}
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}
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bool MapVAddr(Registers& regs, TLBAccessType accessType, u64 vaddr, u32& paddr) {
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if(regs.cop0.is_64bit_addressing) [[unlikely]] {
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if (regs.cop0.kernel_mode) [[likely]] {
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return MapVAddr64(regs, accessType, vaddr, paddr);
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} else if (regs.cop0.user_mode) {
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return UserMapVAddr64(regs, accessType, vaddr, paddr);
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} else if (regs.cop0.supervisor_mode) {
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Util::panic("Supervisor mode memory access, 64 bit mode");
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} else {
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Util::panic("Unknown mode! This should never happen!");
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}
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} else {
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if (regs.cop0.kernel_mode) [[likely]] {
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return MapVAddr32(regs, accessType, vaddr, paddr);
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} else if (regs.cop0.user_mode) {
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return UserMapVAddr32(regs, accessType, vaddr, paddr);
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} else if (regs.cop0.supervisor_mode) {
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Util::panic("Supervisor mode memory access, 32 bit mode");
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} else {
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Util::panic("Unknown mode! This should never happen!");
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}
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}
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}
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bool UserMapVAddr32(Registers& regs, TLBAccessType accessType, u64 vaddr, u32& paddr) {
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switch (vaddr) {
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case VREGION_KUSEG:
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return ProbeTLB(regs, accessType, s64(s32(vaddr)), paddr, nullptr);
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default:
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regs.cop0.tlbError = DISALLOWED_ADDRESS;
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return false;
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}
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}
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bool MapVAddr32(Registers& regs, TLBAccessType accessType, u64 vaddr, u32& paddr) {
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switch((u32(vaddr) >> 29) & 7) {
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case 0 ... 3: case 7:
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return ProbeTLB(regs, accessType, s64(s32(vaddr)), paddr, nullptr);
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case 4 ... 5:
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paddr = vaddr & 0x1FFFFFFF;
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return true;
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case 6: Util::panic("Unimplemented virtual mapping in KSSEG! ({:08X})", vaddr);
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default:
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Util::panic("Should never end up in default case in map_vaddr! ({:08X})", vaddr);
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}
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return false;
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}
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bool UserMapVAddr64(Registers& regs, TLBAccessType accessType, u64 vaddr, u32& paddr) {
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switch (vaddr) {
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case VREGION_XKUSEG:
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return ProbeTLB(regs, accessType, vaddr, paddr, nullptr);
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default:
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regs.cop0.tlbError = DISALLOWED_ADDRESS;
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return false;
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}
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}
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bool MapVAddr64(Registers& regs, TLBAccessType accessType, u64 vaddr, u32& paddr) {
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switch (vaddr) {
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case VREGION_XKUSEG: case VREGION_XKSSEG:
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return ProbeTLB(regs, accessType, vaddr, paddr, nullptr);
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case VREGION_XKPHYS: {
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if (!regs.cop0.kernel_mode) {
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Util::panic("Access to XKPHYS address 0x{:016X} when outside kernel mode!", vaddr);
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}
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u8 high_two_bits = (vaddr >> 62) & 0b11;
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if (high_two_bits != 0b10) {
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Util::panic("Access to XKPHYS address 0x{:016X} with high two bits != 0b10!", vaddr);
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}
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u8 subsegment = (vaddr >> 59) & 0b11;
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bool cached = subsegment != 2; // do something with this eventually
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// If any bits in the range of 58:32 are set, the address is invalid.
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bool valid = (vaddr & 0x07FFFFFF00000000) == 0;
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if (!valid) {
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regs.cop0.tlbError = DISALLOWED_ADDRESS;
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return false;
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}
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paddr = vaddr & 0xFFFFFFFF;
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return true;
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}
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case VREGION_XKSEG:
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return ProbeTLB(regs, accessType, vaddr, paddr, nullptr);
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case VREGION_CKSEG0:
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// Identical to kseg0 in 32 bit mode.
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// Unmapped translation. Subtract the base address of the space to get the physical address.
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paddr = vaddr - START_VREGION_KSEG0; // Implies cutting off the high 32 bits
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Util::trace("CKSEG0: Translated 0x{:016X} to 0x{:08X}", vaddr, paddr);
|
|
return true;
|
|
case VREGION_CKSEG1:
|
|
// Identical to kseg1 in 32 bit mode.
|
|
// Unmapped translation. Subtract the base address of the space to get the physical address.
|
|
paddr = vaddr - START_VREGION_KSEG1; // Implies cutting off the high 32 bits
|
|
Util::trace("KSEG1: Translated 0x{:016X} to 0x{:08X}", vaddr, paddr);
|
|
return true;
|
|
case VREGION_CKSSEG:
|
|
Util::panic("Resolving virtual address 0x{:016X} (VREGION_CKSSEG) in 64 bit mode", vaddr);
|
|
case VREGION_CKSEG3:
|
|
return ProbeTLB(regs, accessType, vaddr, paddr, nullptr);
|
|
case VREGION_XBAD1:
|
|
case VREGION_XBAD2:
|
|
case VREGION_XBAD3:
|
|
regs.cop0.tlbError = DISALLOWED_ADDRESS;
|
|
return false;
|
|
default:
|
|
Util::panic("Resolving virtual address 0x{:016X} in 64 bit mode", vaddr);
|
|
}
|
|
|
|
return false;
|
|
}
|
|
} |