352a52804d
git-subtree-dir: external/capstone git-subtree-split: 5430745e9623786f65c0d773a417f389ebb43395
303 lines
6.0 KiB
C
303 lines
6.0 KiB
C
#ifndef CAPSTONE_ALPHA_H
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#define CAPSTONE_ALPHA_H
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/* Capstone Disassembly Engine */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2014 */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !defined(_MSC_VER) || !defined(_KERNEL_MODE)
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#include <stdint.h>
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#endif
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#include "cs_operand.h"
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#include "platform.h"
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#ifdef _MSC_VER
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#pragma warning(disable : 4201)
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#endif
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#define NUM_ALPHA_OPS 3
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//> Operand type for instruction's operands
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typedef enum alpha_op_type {
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ALPHA_OP_INVALID = CS_OP_INVALID, ///< CS_OP_INVALID (Uninitialized).
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ALPHA_OP_REG = CS_OP_REG, ///< CS_OP_REG (Register operand).
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ALPHA_OP_IMM = CS_OP_IMM, ///< CS_OP_IMM (Immediate operand).
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} alpha_op_type;
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// Instruction operand
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typedef struct cs_alpha_op {
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alpha_op_type type; // operand type
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union {
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unsigned int reg; // register value for REG operand
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int32_t imm; // immediate value for IMM operand
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};
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enum cs_ac_type access;
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} cs_alpha_op;
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// Instruction structure
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typedef struct cs_alpha {
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// Number of operands of this instruction,
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// or 0 when instruction has no operand.
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uint8_t op_count;
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cs_alpha_op operands[NUM_ALPHA_OPS]; // operands for this instruction.
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} cs_alpha;
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//> Alpha registers
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typedef enum alpha_reg {
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// generated content <AlphaGenCSRegEnum.inc> begin
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// clang-format off
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Alpha_REG_INVALID = 0,
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Alpha_REG_F0 = 1,
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Alpha_REG_F1 = 2,
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Alpha_REG_F2 = 3,
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Alpha_REG_F3 = 4,
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Alpha_REG_F4 = 5,
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Alpha_REG_F5 = 6,
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Alpha_REG_F6 = 7,
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Alpha_REG_F7 = 8,
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Alpha_REG_F8 = 9,
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Alpha_REG_F9 = 10,
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Alpha_REG_F10 = 11,
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Alpha_REG_F11 = 12,
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Alpha_REG_F12 = 13,
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Alpha_REG_F13 = 14,
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Alpha_REG_F14 = 15,
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Alpha_REG_F15 = 16,
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Alpha_REG_F16 = 17,
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Alpha_REG_F17 = 18,
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Alpha_REG_F18 = 19,
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Alpha_REG_F19 = 20,
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Alpha_REG_F20 = 21,
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Alpha_REG_F21 = 22,
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Alpha_REG_F22 = 23,
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Alpha_REG_F23 = 24,
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Alpha_REG_F24 = 25,
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Alpha_REG_F25 = 26,
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Alpha_REG_F26 = 27,
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Alpha_REG_F27 = 28,
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Alpha_REG_F28 = 29,
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Alpha_REG_F29 = 30,
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Alpha_REG_F30 = 31,
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Alpha_REG_F31 = 32,
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Alpha_REG_R0 = 33,
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Alpha_REG_R1 = 34,
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Alpha_REG_R2 = 35,
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Alpha_REG_R3 = 36,
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Alpha_REG_R4 = 37,
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Alpha_REG_R5 = 38,
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Alpha_REG_R6 = 39,
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Alpha_REG_R7 = 40,
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Alpha_REG_R8 = 41,
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Alpha_REG_R9 = 42,
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Alpha_REG_R10 = 43,
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Alpha_REG_R11 = 44,
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Alpha_REG_R12 = 45,
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Alpha_REG_R13 = 46,
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Alpha_REG_R14 = 47,
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Alpha_REG_R15 = 48,
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Alpha_REG_R16 = 49,
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Alpha_REG_R17 = 50,
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Alpha_REG_R18 = 51,
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Alpha_REG_R19 = 52,
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Alpha_REG_R20 = 53,
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Alpha_REG_R21 = 54,
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Alpha_REG_R22 = 55,
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Alpha_REG_R23 = 56,
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Alpha_REG_R24 = 57,
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Alpha_REG_R25 = 58,
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Alpha_REG_R26 = 59,
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Alpha_REG_R27 = 60,
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Alpha_REG_R28 = 61,
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Alpha_REG_R29 = 62,
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Alpha_REG_R30 = 63,
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Alpha_REG_R31 = 64,
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Alpha_REG_ENDING, // 65
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// clang-format on
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// generated content <AlphaGenCSRegEnum.inc> end
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} alpha_reg;
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//> Alpha instruction
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typedef enum alpha_insn {
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// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> begin
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// clang-format off
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Alpha_INS_INVALID,
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Alpha_INS_ADDL,
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Alpha_INS_ADDQ,
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Alpha_INS_ADDSsSU,
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Alpha_INS_ADDTsSU,
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Alpha_INS_AND,
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Alpha_INS_BEQ,
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Alpha_INS_BGE,
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Alpha_INS_BGT,
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Alpha_INS_BIC,
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Alpha_INS_BIS,
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Alpha_INS_BLBC,
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Alpha_INS_BLBS,
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Alpha_INS_BLE,
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Alpha_INS_BLT,
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Alpha_INS_BNE,
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Alpha_INS_BR,
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Alpha_INS_BSR,
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Alpha_INS_CMOVEQ,
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Alpha_INS_CMOVGE,
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Alpha_INS_CMOVGT,
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Alpha_INS_CMOVLBC,
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Alpha_INS_CMOVLBS,
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Alpha_INS_CMOVLE,
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Alpha_INS_CMOVLT,
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Alpha_INS_CMOVNE,
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Alpha_INS_CMPBGE,
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Alpha_INS_CMPEQ,
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Alpha_INS_CMPLE,
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Alpha_INS_CMPLT,
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Alpha_INS_CMPTEQsSU,
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Alpha_INS_CMPTLEsSU,
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Alpha_INS_CMPTLTsSU,
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Alpha_INS_CMPTUNsSU,
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Alpha_INS_CMPULE,
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Alpha_INS_CMPULT,
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Alpha_INS_COND_BRANCH,
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Alpha_INS_CPYSE,
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Alpha_INS_CPYSN,
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Alpha_INS_CPYS,
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Alpha_INS_CTLZ,
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Alpha_INS_CTPOP,
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Alpha_INS_CTTZ,
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Alpha_INS_CVTQSsSUI,
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Alpha_INS_CVTQTsSUI,
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Alpha_INS_CVTSTsS,
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Alpha_INS_CVTTQsSVC,
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Alpha_INS_CVTTSsSUI,
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Alpha_INS_DIVSsSU,
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Alpha_INS_DIVTsSU,
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Alpha_INS_ECB,
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Alpha_INS_EQV,
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Alpha_INS_EXCB,
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Alpha_INS_EXTBL,
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Alpha_INS_EXTLH,
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Alpha_INS_EXTLL,
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Alpha_INS_EXTQH,
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Alpha_INS_EXTQL,
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Alpha_INS_EXTWH,
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Alpha_INS_EXTWL,
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Alpha_INS_FBEQ,
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Alpha_INS_FBGE,
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Alpha_INS_FBGT,
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Alpha_INS_FBLE,
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Alpha_INS_FBLT,
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Alpha_INS_FBNE,
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Alpha_INS_FCMOVEQ,
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Alpha_INS_FCMOVGE,
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Alpha_INS_FCMOVGT,
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Alpha_INS_FCMOVLE,
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Alpha_INS_FCMOVLT,
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Alpha_INS_FCMOVNE,
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Alpha_INS_FETCH,
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Alpha_INS_FETCH_M,
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Alpha_INS_FTOIS,
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Alpha_INS_FTOIT,
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Alpha_INS_INSBL,
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Alpha_INS_INSLH,
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Alpha_INS_INSLL,
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Alpha_INS_INSQH,
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Alpha_INS_INSQL,
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Alpha_INS_INSWH,
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Alpha_INS_INSWL,
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Alpha_INS_ITOFS,
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Alpha_INS_ITOFT,
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Alpha_INS_JMP,
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Alpha_INS_JSR,
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Alpha_INS_JSR_COROUTINE,
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Alpha_INS_LDA,
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Alpha_INS_LDAH,
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Alpha_INS_LDBU,
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Alpha_INS_LDL,
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Alpha_INS_LDL_L,
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Alpha_INS_LDQ,
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Alpha_INS_LDQ_L,
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Alpha_INS_LDQ_U,
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Alpha_INS_LDS,
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Alpha_INS_LDT,
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Alpha_INS_LDWU,
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Alpha_INS_MB,
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Alpha_INS_MSKBL,
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Alpha_INS_MSKLH,
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Alpha_INS_MSKLL,
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Alpha_INS_MSKQH,
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Alpha_INS_MSKQL,
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Alpha_INS_MSKWH,
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Alpha_INS_MSKWL,
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Alpha_INS_MULL,
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Alpha_INS_MULQ,
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Alpha_INS_MULSsSU,
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Alpha_INS_MULTsSU,
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Alpha_INS_ORNOT,
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Alpha_INS_RC,
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Alpha_INS_RET,
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Alpha_INS_RPCC,
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Alpha_INS_RS,
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Alpha_INS_S4ADDL,
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Alpha_INS_S4ADDQ,
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Alpha_INS_S4SUBL,
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Alpha_INS_S4SUBQ,
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Alpha_INS_S8ADDL,
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Alpha_INS_S8ADDQ,
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Alpha_INS_S8SUBL,
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Alpha_INS_S8SUBQ,
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Alpha_INS_SEXTB,
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Alpha_INS_SEXTW,
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Alpha_INS_SLL,
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Alpha_INS_SQRTSsSU,
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Alpha_INS_SQRTTsSU,
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Alpha_INS_SRA,
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Alpha_INS_SRL,
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Alpha_INS_STB,
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Alpha_INS_STL,
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Alpha_INS_STL_C,
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Alpha_INS_STQ,
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Alpha_INS_STQ_C,
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Alpha_INS_STQ_U,
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Alpha_INS_STS,
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Alpha_INS_STT,
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Alpha_INS_STW,
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Alpha_INS_SUBL,
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Alpha_INS_SUBQ,
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Alpha_INS_SUBSsSU,
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Alpha_INS_SUBTsSU,
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Alpha_INS_TRAPB,
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Alpha_INS_UMULH,
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Alpha_INS_WH64,
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Alpha_INS_WH64EN,
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Alpha_INS_WMB,
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Alpha_INS_XOR,
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Alpha_INS_ZAPNOT,
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// clang-format on
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// generated content <AlphaGenCSInsnEnum.inc:GET_INSTR_ENUM> end
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ALPHA_INS_ENDING, // <-- mark the end of the list of instructions
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} alpha_insn;
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//> Group of Alpha instructions
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typedef enum alpha_insn_group {
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Alpha_GRP_INVALID, ///< = CS_GRP_INVALID
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//> Generic groups
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Alpha_GRP_CALL, ///< = CS_GRP_CALL
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Alpha_GRP_JUMP, ///< = CS_GRP_JUMP
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Alpha_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
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Alpha_GRP_ENDING, ///< = mark the end of the list of groups
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} alpha_insn_group;
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#ifdef __cplusplus
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}
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#endif
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#endif
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