3621a6c080
b102f1b8 Update Actions (#2593) 86293136 Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support (#2594) 27da950c Clarify between machine used vs. Capstone module affected. (#2586) 186f7aa0 Fix linking issue on Windows. (#2587) e160cbc5 Fix complex atomic instructions handling (#2584) 9907b22d Update v6 to have Debian Packages (#2579) efbbc3bb cstest: use DOWNLOAD_EXTRACT_TIMESTAMP conditionally (#2581) be6be784 x86: update read/write registers for transfer instructions (#2578) 812e654c Update BPF arch (#2568) 2c4b05f6 Clean up the cstest documentation and build instructions. (#2580) 4dc14ba1 Fix 2572 (#2574) b25aa841 PPC regressions (#2575) 0a29bf80 Small arm64 compat header fixes (#2563) b42e0903 Make thumb, v8 and m-class positional cstool arguments. (#2557) 89aee400 Add arm64 and sysz compatibility layer to Python bindings (#2559) a4281337 Python bindings: Enable more archs + bump cibuildwheel action to the v2.22.0 (#2558) ef74d449 Arm regressions (#2556) 93a104c0 PPC LLVM 18 (#2540) e46838ed Merge branch 'v6' into next cf3600e7 Update Changelog Version to 6.0.0-Alpha2 (#2553) b295cf57 Prepare for update (#2552) fc59da4d fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551) 7d01d7e7 Auto-Sync reproducability + ARM update (#2532) 6ad2608d Python package building rework (#2538) e3bc578d Move debian package generation to a dispatch only workflow (#2543) abbf32b4 fix coverity (#2546) 1ecfb5b0 xtensa: update to espressif/llvm-project (#2533) 379e2a41 Rename build arguments: (#2534) d7be5f9f Change CI to create Debian Package to Release (#2521) f6f96796 tricore: fixes #2474 (#2523) 09f35961 This time actually fix big endian issue. (#2530) 306d5716 Fix endianess issue during assignment. (#2528) 2cfca35e Add CC and VAS compatibility macros (#2525) 32519c01 Fix stringop-truncation warning some compilers raise. (#2522) 5026c2c4 Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64 cecb5ede Fix #2509. (#2510) f97e2705 xtensa: Fix Branch Target (#2516) 1d13a12f AArch64: Replace vararg add_cs_detail by multiple concrete functions 8b618528 Update libcyaml dependency in cstest to 1.4.2 (#2508) ea081286 Tricore EA calculation (#2504) 7db9a080 Fix cstest build with Ninja (#2506) 76242699 Only trigger on released action. (#2497) 981d648b Add hard asserts to all SStream functions and memset MCInst. (#2501) d667a627 Update labeler with Xtensa and v6 files. (#2500) 52b54ee3 Fixing UB santizer, `LITBASE` and assert errors. (#2499) 97db712c Remove irrelevant changes. (#2496) 5bd05e34 Remove irrelevant changes. (#2495) 616488c7 Update changelog for V6.0.0-Alpha1 (#2493) (#2494) c5955b92 Update changelog for V6.0.0-Alpha1 (#2493) a424e709 Be ready for V6-Alpha1 (#2492) 235ba8e0 SystemZ fixes (#2488) 5dffa75b Fix LDR not assigning immediate as memory offset. (#2487) 21f7bc85 Xtensa Support (#2380) 29d87734 Several small fixups (#2489) a34901e9 Update sponsors and remove empty file. (#2485) 3120932d Fix Coverity CID 509730: overflow before widen (#2486) 1014864d Rename CS_OPT_NO_BRANCH_OFFSET and corresponding flag to better name. (#2482) 0c90fe13 Replace `assert` with `CS_ASSERT` in modules (#2478) 823bfd53 AArch64 issues (#2473) git-subtree-dir: external/capstone git-subtree-split: b102f1b89e0455c072a751d287ab64378c14205f
384 lines
12 KiB
C
384 lines
12 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===- SystemZInstPrinter.cpp - Convert SystemZ MCInst to assembly syntax -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include <ctype.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../MathExtras.h"
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#include "../../MCAsmInfo.h"
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#include "SystemZMapping.h"
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#include "SystemZInstPrinter.h"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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static void printAddress(const MCAsmInfo *MAI, MCRegister Base,
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const MCOperand *DispMO, MCRegister Index, SStream *O);
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static void printMCOperandMAI(const MCOperand *MO, const MCAsmInfo *MAI,
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SStream *O);
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static void printRegName(const MCInst *MI, SStream *O, MCRegister Reg);
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static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O);
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static void printOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O);
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static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O);
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static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O);
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static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O);
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static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O);
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static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O);
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static void printPCRelOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
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static void printPCRelTLSOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
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// This forms part of the instruction name rather than the operand list.
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// Print the mnemonic for a condition-code mask ("ne", "lh", etc.)
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static void printCond4Operand(MCInst *MI, int OpNum, SStream *O);
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#include "SystemZGenAsmWriter.inc"
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#define DECLARE_printUImmOperand(N) \
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static void CONCAT(printUImmOperand, N)(MCInst * MI, int OpNum, SStream *O);
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DECLARE_printUImmOperand(1);
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DECLARE_printUImmOperand(2);
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DECLARE_printUImmOperand(3);
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DECLARE_printUImmOperand(4);
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DECLARE_printUImmOperand(8);
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DECLARE_printUImmOperand(12);
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DECLARE_printUImmOperand(16);
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DECLARE_printUImmOperand(32);
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DECLARE_printUImmOperand(48);
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#define DECLARE_printSImmOperand(N) \
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static void CONCAT(printSImmOperand, N)(MCInst * MI, int OpNum, SStream *O);
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DECLARE_printSImmOperand(8);
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DECLARE_printSImmOperand(16);
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DECLARE_printSImmOperand(32);
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static void printAddress(const MCAsmInfo *MAI, MCRegister Base,
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const MCOperand *DispMO, MCRegister Index, SStream *O)
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{
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printMCOperandMAI(DispMO, MAI, O);
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if (Base || Index) {
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SStream_concat0(O, "(");
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if (Index) {
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printFormattedRegName(MAI, Index, O);
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SStream_concat0(O, ",");
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}
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if (Base)
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printFormattedRegName(MAI, Base, O);
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else
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SStream_concat0(O, "0");
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SStream_concat0(O, ")");
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}
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}
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static void printMCOperandMAI(const MCOperand *MO, const MCAsmInfo *MAI,
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SStream *O) {
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if (MCOperand_isReg(MO)) {
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if (!MCOperand_getReg(MO))
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SStream_concat1(O, '0');
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else
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printFormattedRegName(MAI, MCOperand_getReg(MO), O);
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}
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else if (MCOperand_isImm(MO))
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printInt64(markup_OS(O, Markup_Immediate), MCOperand_getImm(MO));
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else if (MCOperand_isExpr(MO))
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printExpr(O, MCOperand_getExpr(MO));
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else
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CS_ASSERT(0 && "Invalid operand");
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}
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static void printMCOperand(const MCInst *MI, const MCOperand *MO, SStream *O)
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{
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if (MCOperand_isReg(MO)) {
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if (!MCOperand_getReg(MO))
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SStream_concat0(O, "0");
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else
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printFormattedRegName(&MI->MAI, MCOperand_getReg(MO), O);
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} else if (MCOperand_isImm(MO))
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printInt64(markup_OS(O, Markup_Immediate),
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MCOperand_getImm(MO));
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else if (MCOperand_isExpr(MO))
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printExpr(O, MCOperand_getExpr(MO)); \
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else
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CS_ASSERT_RET(0 && "Invalid operand");
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}
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void printFormattedRegName(const MCAsmInfo *MAI, MCRegister Reg, SStream *O)
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{
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const char *RegName = getRegisterName(Reg);
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if (MAI->assemblerDialect == SYSTEMZASMDIALECT_AD_ATT) {
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// Skip register prefix so that only register number is left
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CS_ASSERT((isalpha(RegName[0]) && isdigit(RegName[1])));
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SStream_concat0(markup_OS(O, Markup_Register), (RegName + 1));
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} else
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SStream_concat1(markup_OS(O, Markup_Register), '%');
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SStream_concat0(markup_OS(O, Markup_Register), RegName);
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}
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static void printRegName(const MCInst *MI, SStream *O, MCRegister Reg)
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{
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printFormattedRegName(&MI->MAI, Reg, O);
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}
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static void printInst(MCInst *MI, uint64_t Address, const char *Annot, SStream *O)
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{
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printInstruction(MI, Address, O);
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}
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#define DEFINE_printUImmOperand(N) \
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void CONCAT(printUImmOperand, N)(MCInst * MI, int OpNum, SStream *O) \
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{ \
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MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \
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if (MCOperand_isExpr(MO)) { \
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printExpr(O, MCOperand_getExpr(MO)); \
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return; \
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} \
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uint64_t Value = (uint64_t)(MCOperand_getImm(MO)); \
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CS_ASSERT((isUIntN(N, Value) && "Invalid uimm argument")); \
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printUInt64(markup_OS(O, Markup_Immediate), Value); \
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}
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DEFINE_printUImmOperand(1);
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DEFINE_printUImmOperand(2);
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DEFINE_printUImmOperand(3);
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DEFINE_printUImmOperand(4);
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DEFINE_printUImmOperand(8);
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DEFINE_printUImmOperand(12);
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DEFINE_printUImmOperand(16);
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DEFINE_printUImmOperand(32);
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DEFINE_printUImmOperand(48);
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#define DEFINE_printSImmOperand(N) \
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void CONCAT(printSImmOperand, N)(MCInst * MI, int OpNum, SStream *O) \
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{ \
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MCOperand *MO = MCInst_getOperand(MI, (OpNum)); \
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if (MCOperand_isExpr(MO)) { \
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printExpr(O, MCOperand_getExpr(MO)); \
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return; \
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} \
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int64_t Value = \
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MCOperand_getImm(MCInst_getOperand(MI, (OpNum))); \
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if (N == 8) \
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printInt8(markup_OS(O, Markup_Immediate), Value); \
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else if (N == 16) \
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printInt16(markup_OS(O, Markup_Immediate), Value); \
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else if (N == 32) \
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printInt32(markup_OS(O, Markup_Immediate), Value); \
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else \
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CS_ASSERT(0 && "Unreachable"); \
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}
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DEFINE_printSImmOperand(8);
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DEFINE_printSImmOperand(16);
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DEFINE_printSImmOperand(32);
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static void printU1ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U1ImmOperand, OpNum);
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CONCAT(printUImmOperand, 1)(MI, OpNum, O);
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}
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static void printU2ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U2ImmOperand, OpNum);
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CONCAT(printUImmOperand, 2)(MI, OpNum, O);
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}
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static void printU3ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U3ImmOperand, OpNum);
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CONCAT(printUImmOperand, 3)(MI, OpNum, O);
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}
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static void printU4ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U4ImmOperand, OpNum);
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CONCAT(printUImmOperand, 4)(MI, OpNum, O);
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}
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static void printS8ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_S8ImmOperand, OpNum);
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CONCAT(printSImmOperand, 8)(MI, OpNum, O);
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}
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static void printU8ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U8ImmOperand, OpNum);
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CONCAT(printUImmOperand, 8)(MI, OpNum, O);
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}
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static void printU12ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U12ImmOperand, OpNum);
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CONCAT(printUImmOperand, 12)(MI, OpNum, O);
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}
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static void printS16ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_S16ImmOperand, OpNum);
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CONCAT(printSImmOperand, 16)(MI, OpNum, O);
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}
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static void printU16ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U16ImmOperand, OpNum);
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CONCAT(printUImmOperand, 16)(MI, OpNum, O);
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}
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static void printS32ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_S32ImmOperand, OpNum);
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CONCAT(printSImmOperand, 32)(MI, OpNum, O);
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}
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static void printU32ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U32ImmOperand, OpNum);
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CONCAT(printUImmOperand, 32)(MI, OpNum, O);
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}
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static void printU48ImmOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_U48ImmOperand, OpNum);
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CONCAT(printUImmOperand, 48)(MI, OpNum, O);
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}
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static void printPCRelOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_PCRelOperand, OpNum);
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MCOperand *MO = MCInst_getOperand(MI, (OpNum));
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if (MCOperand_isImm(MO)) {
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printInt64(O, MCOperand_getImm(MO));
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} else
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printExpr(O, MCOperand_getExpr(MO));
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}
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static void printPCRelTLSOperand(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
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{
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// Output the PC-relative operand.
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printPCRelOperand(MI, MI->address, OpNum, O);
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// Output the TLS marker if present.
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if ((unsigned)OpNum + 1 < MCInst_getNumOperands(MI)) {
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// Expressions not supported
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}
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}
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static void printOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_Operand, OpNum);
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printMCOperand(MI, MCInst_getOperand(MI, (OpNum)), O);
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}
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static void printBDAddrOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_BDAddrOperand, OpNum);
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printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))),
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MCInst_getOperand(MI, (OpNum + 1)), 0, O);
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}
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static void printBDXAddrOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_BDXAddrOperand, OpNum);
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printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))),
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MCInst_getOperand(MI, (OpNum + 1)),
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MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O);
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}
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static void printBDLAddrOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_BDLAddrOperand, OpNum);
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unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
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MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1));
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uint64_t Length = MCOperand_getImm(MCInst_getOperand(MI, (OpNum + 2)));
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printMCOperandMAI(DispMO, &MI->MAI, O);
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SStream_concat1(O, '(');
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printUInt64(O, Length);
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if (Base) {
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SStream_concat0(O, ",");
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printRegName(MI, O, Base);
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}
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SStream_concat0(O, ")");
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}
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static void printBDRAddrOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_BDRAddrOperand, OpNum);
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unsigned Base = MCOperand_getReg(MCInst_getOperand(MI, (OpNum)));
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MCOperand *DispMO = MCInst_getOperand(MI, (OpNum + 1));
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unsigned Length = MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2)));
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printMCOperandMAI(DispMO, &MI->MAI, O);
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SStream_concat0(O, "(");
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printRegName(MI, O, Length);
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if (Base) {
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SStream_concat0(O, ",");
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printRegName(MI, O, Base);
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}
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SStream_concat0(O, ")");
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}
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static void printBDVAddrOperand(MCInst *MI, int OpNum, SStream *O)
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{
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add_cs_detail(MI, SystemZ_OP_GROUP_BDVAddrOperand, OpNum);
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printAddress(&MI->MAI, MCOperand_getReg(MCInst_getOperand(MI, (OpNum))),
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MCInst_getOperand(MI, (OpNum + 1)),
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MCOperand_getReg(MCInst_getOperand(MI, (OpNum + 2))), O);
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}
|
|
|
|
static void printCond4Operand(MCInst *MI, int OpNum, SStream *O)
|
|
{
|
|
add_cs_detail(MI, SystemZ_OP_GROUP_Cond4Operand, OpNum);
|
|
static const char *const CondNames[] = { "o", "h", "nle", "l",
|
|
"nhe", "lh", "ne", "e",
|
|
"nlh", "he", "nl", "le",
|
|
"nh", "no" };
|
|
uint64_t Imm = MCOperand_getImm(MCInst_getOperand(MI, (OpNum)));
|
|
CS_ASSERT((Imm > 0 && Imm < 15 && "Invalid condition"));
|
|
SStream_concat0(O, CondNames[Imm - 1]);
|
|
}
|
|
|
|
const char *SystemZ_LLVM_getRegisterName(unsigned RegNo)
|
|
{
|
|
return getRegisterName(RegNo);
|
|
}
|
|
|
|
void SystemZ_LLVM_printInstruction(MCInst *MI, const char *Annotation, SStream *O)
|
|
{
|
|
printInst(MI, MI->address, Annotation, O);
|
|
}
|