Files
kaizen/cs_priv.h
Simone 3621a6c080 Squashed 'external/capstone/' changes from 5430745e..b102f1b8
b102f1b8 Update Actions (#2593)
86293136 Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support (#2594)
27da950c Clarify between machine used vs. Capstone module affected. (#2586)
186f7aa0 Fix linking issue on Windows. (#2587)
e160cbc5 Fix complex atomic instructions handling (#2584)
9907b22d Update v6 to have Debian Packages (#2579)
efbbc3bb cstest: use DOWNLOAD_EXTRACT_TIMESTAMP conditionally (#2581)
be6be784 x86: update read/write registers for transfer instructions (#2578)
812e654c Update BPF arch (#2568)
2c4b05f6 Clean up the cstest documentation and build instructions. (#2580)
4dc14ba1 Fix 2572 (#2574)
b25aa841 PPC regressions (#2575)
0a29bf80 Small arm64 compat header fixes (#2563)
b42e0903 Make thumb, v8 and m-class positional cstool arguments. (#2557)
89aee400 Add arm64 and sysz compatibility layer to Python bindings (#2559)
a4281337 Python bindings: Enable more archs + bump cibuildwheel action to the v2.22.0 (#2558)
ef74d449 Arm regressions (#2556)
93a104c0 PPC LLVM 18 (#2540)
e46838ed Merge branch 'v6' into next
cf3600e7 Update Changelog Version to 6.0.0-Alpha2 (#2553)
b295cf57 Prepare for update (#2552)
fc59da4d fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551)
7d01d7e7 Auto-Sync reproducability + ARM update (#2532)
6ad2608d Python package building rework (#2538)
e3bc578d Move debian package generation to a dispatch only workflow (#2543)
abbf32b4 fix coverity (#2546)
1ecfb5b0 xtensa: update to espressif/llvm-project (#2533)
379e2a41 Rename build arguments: (#2534)
d7be5f9f Change CI to create Debian Package to Release (#2521)
f6f96796 tricore: fixes #2474 (#2523)
09f35961 This time actually fix big endian issue. (#2530)
306d5716 Fix endianess issue during assignment. (#2528)
2cfca35e Add CC and VAS compatibility macros (#2525)
32519c01 Fix stringop-truncation warning some compilers raise. (#2522)
5026c2c4 Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64
cecb5ede Fix #2509. (#2510)
f97e2705 xtensa: Fix Branch Target (#2516)
1d13a12f AArch64: Replace vararg add_cs_detail by multiple concrete functions
8b618528 Update libcyaml dependency in cstest to 1.4.2 (#2508)
ea081286 Tricore EA calculation (#2504)
7db9a080 Fix cstest build with Ninja (#2506)
76242699 Only trigger on released action. (#2497)
981d648b Add hard asserts to all SStream functions and memset MCInst. (#2501)
d667a627 Update labeler with Xtensa and v6 files. (#2500)
52b54ee3 Fixing UB santizer, `LITBASE` and assert errors. (#2499)
97db712c Remove irrelevant changes. (#2496)
5bd05e34 Remove irrelevant changes. (#2495)
616488c7 Update changelog for V6.0.0-Alpha1 (#2493) (#2494)
c5955b92 Update changelog for V6.0.0-Alpha1 (#2493)
a424e709 Be ready for V6-Alpha1 (#2492)
235ba8e0 SystemZ fixes (#2488)
5dffa75b Fix LDR not assigning immediate as memory offset. (#2487)
21f7bc85 Xtensa Support (#2380)
29d87734 Several small fixups (#2489)
a34901e9 Update sponsors and remove empty file. (#2485)
3120932d Fix Coverity CID 509730: overflow before widen (#2486)
1014864d Rename CS_OPT_NO_BRANCH_OFFSET and corresponding flag to better name. (#2482)
0c90fe13 Replace `assert` with `CS_ASSERT` in modules (#2478)
823bfd53 AArch64 issues (#2473)

git-subtree-dir: external/capstone
git-subtree-split: b102f1b89e0455c072a751d287ab64378c14205f
2025-01-07 15:08:55 +00:00

142 lines
4.2 KiB
C

/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2019 */
#ifndef CS_PRIV_H
#define CS_PRIV_H
#ifdef CAPSTONE_DEBUG
#include <assert.h>
#endif
#include <capstone/capstone.h>
#include "MCInst.h"
#include "SStream.h"
typedef void (*Printer_t)(MCInst *MI, SStream *OS, void *info);
// function to be called after Printer_t
// this is the best time to gather insn's characteristics
typedef void (*PostPrinter_t)(csh handle, cs_insn *, SStream *mnem, MCInst *mci);
typedef bool (*Disasm_t)(csh handle, const uint8_t *code, size_t code_len, MCInst *instr, uint16_t *size, uint64_t address, void *info);
typedef const char *(*GetName_t)(csh handle, unsigned int id);
typedef void (*GetID_t)(cs_struct *h, cs_insn *insn, unsigned int id);
// return registers accessed by instruction
typedef void (*GetRegisterAccess_t)(const cs_insn *insn,
cs_regs regs_read, uint8_t *regs_read_count,
cs_regs regs_write, uint8_t *regs_write_count);
// for ARM only
typedef struct ARM_ITBlock {
unsigned char ITStates[8];
unsigned int size;
} ARM_ITBlock;
typedef struct ARM_VPTBlock {
unsigned char VPTStates[8];
unsigned int size;
} ARM_VPTBlock;
// Customize mnemonic for instructions with alternative name.
struct customized_mnem {
// ID of instruction to be customized.
unsigned int id;
// Customized instruction mnemonic.
char mnemonic[CS_MNEMONIC_SIZE];
};
struct insn_mnem {
struct customized_mnem insn;
struct insn_mnem *next; // linked list of customized mnemonics
};
struct cs_struct {
cs_arch arch;
cs_mode mode;
Printer_t printer; // asm printer
void *printer_info; // aux info for printer
Disasm_t disasm; // disassembler
void *getinsn_info; // auxiliary info for printer
GetName_t reg_name;
GetName_t insn_name;
GetName_t group_name;
GetID_t insn_id;
PostPrinter_t post_printer;
cs_err errnum;
ARM_ITBlock ITBlock; // for Arm only
ARM_VPTBlock VPTBlock; // for ARM only
bool PrintBranchImmAsAddress;
bool ShowVSRNumsAsVR;
cs_opt_value detail_opt, imm_unsigned;
int syntax; // asm syntax for simple printer such as ARM, Mips & PPC
bool doing_mem; // handling memory operand in InstPrinter code
bool doing_SME_Index; // handling a SME instruction that has index
unsigned short *insn_cache; // index caching for mapping.c
bool skipdata; // set this to True if we skip data when disassembling
uint8_t skipdata_size; // how many bytes to skip
cs_opt_skipdata skipdata_setup; // user-defined skipdata setup
const uint8_t *regsize_map; // map to register size (x86-only for now)
GetRegisterAccess_t reg_access;
struct insn_mnem *mnem_list; // linked list of customized instruction mnemonic
uint32_t LITBASE; ///< The LITBASE register content. Bit 0 (LSB) indicatess if it is set. Bit[23:8] are the literal base address.
};
#define MAX_ARCH CS_ARCH_MAX
// Returns a bool (0 or 1) whether big endian is enabled for a mode
#define MODE_IS_BIG_ENDIAN(mode) (((mode) & CS_MODE_BIG_ENDIAN) != 0)
/// Returns true of the 16bit flag is set.
#define IS_16BIT(mode) ((mode & CS_MODE_16) != 0)
/// Returns true of the 32bit flag is set.
#define IS_32BIT(mode) ((mode & CS_MODE_32) != 0)
/// Returns true of the 64bit flag is set.
#define IS_64BIT(mode) ((mode & CS_MODE_64) != 0)
extern cs_malloc_t cs_mem_malloc;
extern cs_calloc_t cs_mem_calloc;
extern cs_realloc_t cs_mem_realloc;
extern cs_free_t cs_mem_free;
extern cs_vsnprintf_t cs_vsnprintf;
/// By defining CAPSTONE_DEBUG assertions can be used.
/// For the release build the @expr is not included.
#ifdef CAPSTONE_DEBUG
#define CS_ASSERT(expr) assert(expr)
#else
#define CS_ASSERT(expr)
#endif
/// If compiled in debug mode it will assert(@expr).
/// In the release build it will check the @expr and return @val if false.
#ifdef CAPSTONE_DEBUG
#define CS_ASSERT_RET_VAL(expr, val) assert(expr)
#else
#define CS_ASSERT_RET_VAL(expr, val) \
do { \
if (!(expr)) { \
fprintf(stderr, "Hit assert: " #expr "\n"); \
return val; \
} \
} while(0)
#endif
/// If compiled in debug mode it will assert(@expr).
/// In the release build it will check the @expr and return if false.
#ifdef CAPSTONE_DEBUG
#define CS_ASSERT_RET(expr) assert(expr)
#else
#define CS_ASSERT_RET(expr) \
do { \
if (!(expr)) { \
fprintf(stderr, "Hit assert: " #expr "\n"); \
return; \
} \
} while(0)
#endif
#endif