b102f1b8 Update Actions (#2593) 86293136 Fix LoongArch aliases and CS_OPT_SYNTAX_NO_DOLLAR support (#2594) 27da950c Clarify between machine used vs. Capstone module affected. (#2586) 186f7aa0 Fix linking issue on Windows. (#2587) e160cbc5 Fix complex atomic instructions handling (#2584) 9907b22d Update v6 to have Debian Packages (#2579) efbbc3bb cstest: use DOWNLOAD_EXTRACT_TIMESTAMP conditionally (#2581) be6be784 x86: update read/write registers for transfer instructions (#2578) 812e654c Update BPF arch (#2568) 2c4b05f6 Clean up the cstest documentation and build instructions. (#2580) 4dc14ba1 Fix 2572 (#2574) b25aa841 PPC regressions (#2575) 0a29bf80 Small arm64 compat header fixes (#2563) b42e0903 Make thumb, v8 and m-class positional cstool arguments. (#2557) 89aee400 Add arm64 and sysz compatibility layer to Python bindings (#2559) a4281337 Python bindings: Enable more archs + bump cibuildwheel action to the v2.22.0 (#2558) ef74d449 Arm regressions (#2556) 93a104c0 PPC LLVM 18 (#2540) e46838ed Merge branch 'v6' into next cf3600e7 Update Changelog Version to 6.0.0-Alpha2 (#2553) b295cf57 Prepare for update (#2552) fc59da4d fix xtensa DecodeMR23RegisterClass and add tests for MAC16 instru… (#2551) 7d01d7e7 Auto-Sync reproducability + ARM update (#2532) 6ad2608d Python package building rework (#2538) e3bc578d Move debian package generation to a dispatch only workflow (#2543) abbf32b4 fix coverity (#2546) 1ecfb5b0 xtensa: update to espressif/llvm-project (#2533) 379e2a41 Rename build arguments: (#2534) d7be5f9f Change CI to create Debian Package to Release (#2521) f6f96796 tricore: fixes #2474 (#2523) 09f35961 This time actually fix big endian issue. (#2530) 306d5716 Fix endianess issue during assignment. (#2528) 2cfca35e Add CC and VAS compatibility macros (#2525) 32519c01 Fix stringop-truncation warning some compilers raise. (#2522) 5026c2c4 Merge pull request #2507 from thestr4ng3r/no-varargs-aarch64 cecb5ede Fix #2509. (#2510) f97e2705 xtensa: Fix Branch Target (#2516) 1d13a12f AArch64: Replace vararg add_cs_detail by multiple concrete functions 8b618528 Update libcyaml dependency in cstest to 1.4.2 (#2508) ea081286 Tricore EA calculation (#2504) 7db9a080 Fix cstest build with Ninja (#2506) 76242699 Only trigger on released action. (#2497) 981d648b Add hard asserts to all SStream functions and memset MCInst. (#2501) d667a627 Update labeler with Xtensa and v6 files. (#2500) 52b54ee3 Fixing UB santizer, `LITBASE` and assert errors. (#2499) 97db712c Remove irrelevant changes. (#2496) 5bd05e34 Remove irrelevant changes. (#2495) 616488c7 Update changelog for V6.0.0-Alpha1 (#2493) (#2494) c5955b92 Update changelog for V6.0.0-Alpha1 (#2493) a424e709 Be ready for V6-Alpha1 (#2492) 235ba8e0 SystemZ fixes (#2488) 5dffa75b Fix LDR not assigning immediate as memory offset. (#2487) 21f7bc85 Xtensa Support (#2380) 29d87734 Several small fixups (#2489) a34901e9 Update sponsors and remove empty file. (#2485) 3120932d Fix Coverity CID 509730: overflow before widen (#2486) 1014864d Rename CS_OPT_NO_BRANCH_OFFSET and corresponding flag to better name. (#2482) 0c90fe13 Replace `assert` with `CS_ASSERT` in modules (#2478) 823bfd53 AArch64 issues (#2473) git-subtree-dir: external/capstone git-subtree-split: b102f1b89e0455c072a751d287ab64378c14205f
93 lines
2.9 KiB
C
93 lines
2.9 KiB
C
/* Capstone Disassembly Engine */
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/* By billow <billow.fun@gmail.com>, 2024 */
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#include <stdio.h>
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#include <capstone/capstone.h>
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#include <capstone/xtensa.h>
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static const char *xtensa_insn_form_strs[] = {
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[XTENSA_INSN_FORM_INVALID] = "XTENSA_INSN_FORM_INVALID",
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[XTENSA_INSN_FORM_RRR] = "XTENSA_INSN_FORM_RRR",
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[XTENSA_INSN_FORM_RRI8] = "XTENSA_INSN_FORM_RRI8",
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[XTENSA_INSN_FORM_RRRN] = "XTENSA_INSN_FORM_RRRN",
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[XTENSA_INSN_FORM_AEINST24] = "XTENSA_INSN_FORM_AEINST24",
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[XTENSA_INSN_FORM_BRI12] = "XTENSA_INSN_FORM_BRI12",
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[XTENSA_INSN_FORM_CALL] = "XTENSA_INSN_FORM_CALL",
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[XTENSA_INSN_FORM_CALLX] = "XTENSA_INSN_FORM_CALLX",
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[XTENSA_INSN_FORM_EE_INST24] = "XTENSA_INSN_FORM_EE_INST24",
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[XTENSA_INSN_FORM_RRI4] = "XTENSA_INSN_FORM_RRI4",
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[XTENSA_INSN_FORM_RI16] = "XTENSA_INSN_FORM_RI16",
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[XTENSA_INSN_FORM_RI7] = "XTENSA_INSN_FORM_RI7",
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[XTENSA_INSN_FORM_RSR] = "XTENSA_INSN_FORM_RSR",
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};
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void print_insn_detail_xtensa(csh handle, cs_insn *ins)
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{
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int i;
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cs_regs regs_read, regs_write;
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uint8_t regs_read_count, regs_write_count;
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// detail can be NULL on "data" instruction if SKIPDATA option is turned ON
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if (ins->detail == NULL)
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return;
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cs_xtensa *detail = &(ins->detail->xtensa);
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if (detail->format && detail->format < XTENSA_INSN_FORM_MAX) {
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printf("\tformat: %s\n", xtensa_insn_form_strs[detail->format]);
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}
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if (detail->op_count)
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printf("\top_count: %u\n", detail->op_count);
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for (i = 0; i < detail->op_count; i++) {
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cs_xtensa_op *op = &(detail->operands[i]);
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if (op->type == CS_OP_REG)
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printf("\t\toperands[%u].type: REG = %s\n", i,
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cs_reg_name(handle, op->reg));
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else if (op->type == CS_OP_IMM)
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printf("\t\toperands[%u].type: IMM = 0x%" PRIx32 "\n",
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i, op->imm);
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else if (op->type == CS_OP_MEM)
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printf("\t\toperands[%u].type: MEM\n"
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"\t\t\t.mem.base: REG = %s\n"
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"\t\t\t.mem.disp: 0x%" PRIx32 "\n",
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i, cs_reg_name(handle, op->mem.base),
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op->mem.disp);
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else if (op->type == XTENSA_OP_L32R) {
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printf("\t\toperands[%u].type: L32R\n"
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"\t\t\t.l32r = %" PRIx32 "\n",
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i, op->imm);
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}
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if (op->access & CS_AC_READ)
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printf("\t\t\t.access: READ\n");
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else if (op->access & CS_AC_WRITE)
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printf("\t\t\t.access: WRITE\n");
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else if (op->access & (CS_AC_READ | CS_AC_WRITE))
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printf("\t\t\t.access: READ | WRITE\n");
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}
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// Print out all registers accessed by this instruction (either implicit or
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// explicit)
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if (!cs_regs_access(handle, ins, regs_read, ®s_read_count,
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regs_write, ®s_write_count)) {
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if (regs_read_count) {
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printf("\tRegisters read:");
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for (i = 0; i < regs_read_count; i++) {
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printf(" %s",
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cs_reg_name(handle, regs_read[i]));
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}
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printf("\n");
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}
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if (regs_write_count) {
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printf("\tRegisters modified:");
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for (i = 0; i < regs_write_count; i++) {
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printf(" %s",
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cs_reg_name(handle, regs_write[i]));
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}
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printf("\n");
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}
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}
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}
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