97 lines
2.3 KiB
C++
97 lines
2.3 KiB
C++
#include <Scheduler.hpp>
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#include <Core.hpp>
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namespace n64 {
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SI::SI() { Reset(); }
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void SI::Reset() {
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status.raw = 0;
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dramAddr = 0;
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pifAddr = 0;
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toDram = false;
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pif.Reset();
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}
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auto SI::Read(u32 addr) const -> u32 {
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n64::Mem &mem = n64::Core::GetMem();
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switch (addr) {
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case 0x04800000:
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return dramAddr;
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case 0x04800004:
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case 0x04800010:
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return pifAddr;
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case 0x0480000C:
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return 0;
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case 0x04800018:
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{
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Core::SetIdleSkippingStatus(true);
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u32 val = 0;
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val |= status.dmaBusy;
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val |= (0 << 1);
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val |= (0 << 3);
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val |= (mem.mmio.mi.intr.si << 12);
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return val;
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}
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default:
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panic("Unhandled SI[{:08X}] read", addr);
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}
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}
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// pif -> rdram
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template <>
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void SI::DMA<true>() {
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n64::Mem &mem = n64::Core::GetMem();
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pif.ProcessCommands();
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for (int i = 0; i < 64; i++) {
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mem.mmio.rdp.WriteRDRAM<u8>(dramAddr + i, pif.Read(pifAddr + i));
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}
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trace("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})", pifAddr, dramAddr);
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}
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// rdram -> pif
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template <>
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void SI::DMA<false>() {
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n64::Mem &mem = n64::Core::GetMem();
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for (int i = 0; i < 64; i++) {
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pif.Write(pifAddr + i, mem.mmio.rdp.ReadRDRAM<u8>(dramAddr + i));
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}
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trace("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})", dramAddr, pifAddr);
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}
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void SI::DMA() {
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n64::Mem &mem = n64::Core::GetMem();
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status.dmaBusy = false;
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if (toDram)
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DMA<true>();
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else
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DMA<false>();
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mem.mmio.mi.InterruptRaise(MI::Interrupt::SI);
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}
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void SI::Write(u32 addr, u32 val) {
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n64::Mem &mem = n64::Core::GetMem();
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switch (addr) {
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case 0x04800000:
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dramAddr = val & RDRAM_DSIZE;
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break;
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case 0x04800004:
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pifAddr = val & 0x1FFFFFFF;
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status.dmaBusy = true;
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toDram = true;
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Scheduler::GetInstance().EnqueueRelative(SI_DMA_DELAY, SI_DMA);
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break;
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case 0x04800010:
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pifAddr = val & 0x1FFFFFFF;
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status.dmaBusy = true;
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toDram = false;
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Scheduler::GetInstance().EnqueueRelative(SI_DMA_DELAY, SI_DMA);
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break;
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case 0x04800018:
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mem.mmio.mi.InterruptLower(MI::Interrupt::SI);
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break;
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default:
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panic("Unhandled SI[{:08X}] write ({:08X})", addr, val);
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}
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}
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} // namespace n64
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