592 lines
15 KiB
C++
592 lines
15 KiB
C++
#include <core/registers/Cop1.hpp>
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#include <core/registers/Registers.hpp>
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#include <core/Mem.hpp>
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#include <cmath>
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#include <cfenv>
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namespace n64 {
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inline int PushRoundingMode(const FCR31& fcr31) {
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int og = fegetround();
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switch(fcr31.rounding_mode) {
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case 0: fesetround(FE_TONEAREST); break;
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case 1: fesetround(FE_TOWARDZERO); break;
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case 2: fesetround(FE_UPWARD); break;
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case 3: fesetround(FE_DOWNWARD); break;
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}
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return og;
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}
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#define PUSHROUNDINGMODE int og = PushRoundingMode(fcr31)
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#define POPROUNDINGMODE fesetround(og)
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#ifdef _WIN32
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#define isnanf isnan
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#define checknanregsf(fs, ft) \
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if(isnanf(fs) || isnanf(ft)) { \
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regs.cop1.fcr31.flag_invalid_operation = true; \
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regs.cop1.fcr31.cause_invalid_operation = true; \
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FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
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return; \
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}
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#define checknanregsd(fs, ft) \
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if(isnan(fs) || isnan(ft)) { \
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regs.cop1.fcr31.flag_invalid_operation = true; \
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regs.cop1.fcr31.cause_invalid_operation = true; \
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FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
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return; \
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}
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#else
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#define checknanregsf(fs, ft) \
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if(isnanf(fs) || isnanf(ft)) { \
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regs.cop1.fcr31.flag_invalid_operation = true; \
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regs.cop1.fcr31.cause_invalid_operation = true; \
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FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
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return; \
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}
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#define checknanregsd(fs, ft) \
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if(isnan(fs) || isnan(ft)) { \
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regs.cop1.fcr31.flag_invalid_operation = true; \
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regs.cop1.fcr31.cause_invalid_operation = true; \
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FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC); \
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return; \
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}
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#endif
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void Cop1::absd(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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SetCop1Reg<double>(regs.cop0, FD(instr), fabs(fs));
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}
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void Cop1::abss(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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SetCop1Reg<float>(regs.cop0, FD(instr), fabsf(fs));
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}
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void Cop1::absw(Registers& regs, u32 instr) {
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s32 fs = GetReg<s32>(regs.cop0, FS(instr));
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SetReg<u32>(regs.cop0, FD(instr), abs(fs));
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}
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void Cop1::absl(Registers& regs, u32 instr) {
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s64 fs = GetReg<s64>(regs.cop0, FS(instr));
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SetReg(regs.cop0, FD(instr), labs(fs));
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}
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void Cop1::adds(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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float ft = GetCop1Reg<float>(regs.cop0, FT(instr));
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checknanregsf(fs, ft)
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float result = fs + ft;
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SetCop1Reg<float>(regs.cop0, FD(instr), result);
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}
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void Cop1::addd(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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double ft = GetCop1Reg<double>(regs.cop0, FT(instr));
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checknanregsf(fs, ft)
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double result = fs + ft;
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SetCop1Reg<double>(regs.cop0, FD(instr), result);
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}
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void Cop1::ceills(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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s64 result = ceilf(fs);
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SetReg<u64>(regs.cop0, FD(instr), result);
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}
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void Cop1::ceilws(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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s32 result = ceilf(fs);
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SetReg<u32>(regs.cop0, FD(instr), result);
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}
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void Cop1::ceilld(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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s64 result = ceil(fs);
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SetReg<u64>(regs.cop0, FD(instr), result);
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}
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void Cop1::ceilwd(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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s32 result = ceil(fs);
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SetReg<u32>(regs.cop0, FD(instr), result);
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}
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void Cop1::cfc1(Registers& regs, u32 instr) const {
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u8 fd = FD(instr);
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s32 val = 0;
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switch(fd) {
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case 0: val = fcr0; break;
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case 31: val = fcr31.raw; break;
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default: util::panic("Undefined CFC1 with rd != 0 or 31\n");
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}
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regs.gpr[RT(instr)] = val;
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}
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void Cop1::ctc1(Registers& regs, u32 instr) {
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u8 fs = FS(instr);
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u32 val = regs.gpr[RT(instr)];
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switch(fs) {
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case 0: break;
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case 31: {
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val &= 0x183ffff;
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fcr31.raw = val;
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} break;
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default: util::panic("Undefined CTC1 with rd != 0 or 31\n");
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}
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}
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void Cop1::cvtds(Registers& regs, u32 instr) {
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SetCop1Reg<double>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<float>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtsd(Registers& regs, u32 instr) {
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SetCop1Reg<float>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<double>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtwd(Registers& regs, u32 instr) {
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SetReg<u32>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<double>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtws(Registers& regs, u32 instr) {
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SetReg<u32>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<float>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtls(Registers& regs, u32 instr) {
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SetReg<u64>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<float>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtsl(Registers& regs, u32 instr) {
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SetCop1Reg<float>(
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regs.cop0,
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FD(instr),
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(s64)GetReg<u64>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtdw(Registers& regs, u32 instr) {
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SetCop1Reg<double>(
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regs.cop0,
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FD(instr),
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(s32)GetReg<u32>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtsw(Registers& regs, u32 instr) {
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SetCop1Reg<float>(
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regs.cop0,
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FD(instr),
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(s32)GetReg<u32>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtdl(Registers& regs, u32 instr) {
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SetCop1Reg<double>(
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regs.cop0,
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FD(instr),
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(s64)GetReg<u64>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::cvtld(Registers& regs, u32 instr) {
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SetReg<u64>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<double>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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template <typename T>
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inline bool CalculateCondition(Registers& regs, T fs, T ft, CompConds cond) {
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switch(cond) {
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case F: return false;
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case UN: return std::isnan(fs) || std::isnan(ft);
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case EQ: return fs == ft;
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case UEQ: return (std::isnan(fs) || std::isnan(ft)) || (fs == ft);
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case OLT: return (!std::isnan(fs) && !std::isnan(ft)) && (fs < ft);
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case ULT: return (std::isnan(fs) || std::isnan(ft)) || (fs < ft);
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case OLE: return (!std::isnan(fs) && !std::isnan(ft)) && (fs <= ft);
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case ULE: return (std::isnan(fs) || std::isnan(ft)) || (fs <= ft);
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default:
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if(std::isnan(fs) || std::isnan(ft)) {
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regs.cop1.fcr31.flag_invalid_operation = true;
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regs.cop1.fcr31.cause_invalid_operation = true;
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FireException(regs, ExceptionCode::FloatingPointError, 1, regs.oldPC);
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return false;
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}
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return CalculateCondition(regs, fs, ft, static_cast<CompConds>(cond - 8));
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}
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}
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template <typename T>
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void Cop1::ccond(Registers& regs, u32 instr, CompConds cond) {
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T fs = GetCop1Reg<T>(regs.cop0, FS(instr));
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T ft = GetCop1Reg<T>(regs.cop0, FT(instr));
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fcr31.compare = CalculateCondition(regs, fs, ft, cond);
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}
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template void Cop1::ccond<float>(Registers& regs, u32 instr, CompConds cond);
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template void Cop1::ccond<double>(Registers& regs, u32 instr, CompConds cond);
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void Cop1::divs(Registers ®s, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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float ft = GetCop1Reg<float>(regs.cop0, FT(instr));
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SetCop1Reg<float>(regs.cop0, FD(instr), fs / ft);
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}
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void Cop1::divd(Registers ®s, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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double ft = GetCop1Reg<double>(regs.cop0, FT(instr));
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SetCop1Reg<double>(regs.cop0, FD(instr), fs / ft);
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}
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void Cop1::muls(Registers ®s, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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float ft = GetCop1Reg<float>(regs.cop0, FT(instr));
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SetCop1Reg<float>(regs.cop0, FD(instr), fs * ft);
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}
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void Cop1::muld(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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double ft = GetCop1Reg<double>(regs.cop0, FT(instr));
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SetCop1Reg<double>(regs.cop0, FD(instr), fs * ft);
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}
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void Cop1::mulw(Registers ®s, u32 instr) {
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u32 fs = GetReg<u32>(regs.cop0, FS(instr));
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u32 ft = GetReg<u32>(regs.cop0, FT(instr));
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SetReg<u32>(regs.cop0, FD(instr), fs * ft);
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}
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void Cop1::mull(Registers ®s, u32 instr) {
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u64 fs = GetReg<u64>(regs.cop0, FS(instr));
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u64 ft = GetReg<u64>(regs.cop0, FT(instr));
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SetReg<u64>(regs.cop0, FD(instr), fs * ft);
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}
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void Cop1::subs(Registers ®s, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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float ft = GetCop1Reg<float>(regs.cop0, FT(instr));
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SetCop1Reg<float>(regs.cop0, FD(instr), fs - ft);
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}
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void Cop1::subd(Registers ®s, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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double ft = GetCop1Reg<double>(regs.cop0, FT(instr));
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SetCop1Reg<double>(regs.cop0, FD(instr), fs - ft);
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}
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void Cop1::subw(Registers ®s, u32 instr) {
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u32 fs = GetReg<u32>(regs.cop0, FS(instr));
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u32 ft = GetReg<u32>(regs.cop0, FT(instr));
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SetReg<u32>(regs.cop0, FD(instr), fs - ft);
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}
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void Cop1::subl(Registers ®s, u32 instr) {
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u64 fs = GetReg<u64>(regs.cop0, FS(instr));
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u64 ft = GetReg<u64>(regs.cop0, FT(instr));
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SetReg<u64>(regs.cop0, FD(instr), fs - ft);
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}
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void Cop1::movs(Registers& regs, u32 instr) {
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SetCop1Reg<float>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<float>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::movd(Registers& regs, u32 instr) {
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SetCop1Reg<double>(
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regs.cop0,
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FD(instr),
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GetCop1Reg<double>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::movw(Registers& regs, u32 instr) {
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SetReg<u32>(
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regs.cop0,
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FD(instr),
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GetReg<u32>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::movl(Registers& regs, u32 instr) {
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SetReg<u64>(
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regs.cop0,
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FD(instr),
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GetReg<u64>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::negs(Registers ®s, u32 instr) {
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SetCop1Reg<float>(
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regs.cop0,
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FD(instr),
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-GetCop1Reg<float>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::negd(Registers ®s, u32 instr) {
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SetCop1Reg<double>(
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regs.cop0,
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FD(instr),
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-GetCop1Reg<double>(
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regs.cop0,
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FS(instr)
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)
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);
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}
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void Cop1::sqrts(Registers ®s, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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SetCop1Reg<float>(regs.cop0, FD(instr), sqrtf(fs));
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}
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void Cop1::sqrtd(Registers ®s, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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SetCop1Reg<double>(regs.cop0, FD(instr), sqrt(fs));
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}
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void Cop1::roundls(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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PUSHROUNDINGMODE;
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SetReg<u64>(regs.cop0, FD(instr), (s32)nearbyintf(fs));
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POPROUNDINGMODE;
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}
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void Cop1::roundld(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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PUSHROUNDINGMODE;
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SetReg<u64>(regs.cop0, FD(instr), (s64)nearbyint(fs));
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POPROUNDINGMODE;
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}
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void Cop1::roundws(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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PUSHROUNDINGMODE;
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SetReg<u32>(regs.cop0, FD(instr), (s32)nearbyintf(fs));
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POPROUNDINGMODE;
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}
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void Cop1::roundwd(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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PUSHROUNDINGMODE;
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SetReg<u32>(regs.cop0, FD(instr), (s32)nearbyint(fs));
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POPROUNDINGMODE;
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}
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void Cop1::floorls(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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SetReg<u64>(regs.cop0, FD(instr), (s64)floorf(fs));
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}
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void Cop1::floorld(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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SetReg<u64>(regs.cop0, FD(instr), (s64)floor(fs));
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}
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void Cop1::floorws(Registers& regs, u32 instr) {
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float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
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SetReg<u32>(regs.cop0, FD(instr), (s64)floorf(fs));
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}
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void Cop1::floorwd(Registers& regs, u32 instr) {
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double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
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SetReg<u32>(regs.cop0, FD(instr), (s64)floor(fs));
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}
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void Cop1::lwc1(Registers& regs, Mem& mem, u32 instr) {
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if(!regs.cop0.status.cu1) {
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FireException(regs, ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
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return;
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}
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u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
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if(addr & 3) {
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FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
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}
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u32 physical;
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if(!MapVAddr(regs, LOAD, addr, physical)) {
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HandleTLBException(regs, addr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
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} else {
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u32 data = mem.Read32<false>(regs, physical, regs.oldPC);
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SetReg<u32>(regs.cop0, FT(instr), data);
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}
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}
|
|
|
|
void Cop1::swc1(Registers& regs, Mem& mem, u32 instr) {
|
|
if(!regs.cop0.status.cu1) {
|
|
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
|
|
return;
|
|
}
|
|
|
|
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
|
|
if(addr & 3) {
|
|
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
|
|
}
|
|
|
|
u32 physical;
|
|
if(!MapVAddr(regs, STORE, addr, physical)) {
|
|
HandleTLBException(regs, addr);
|
|
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
} else {
|
|
mem.Write32<false>(regs, physical, GetReg<u32>(regs.cop0, FT(instr)), regs.oldPC);
|
|
}
|
|
}
|
|
|
|
void Cop1::ldc1(Registers& regs, Mem& mem, u32 instr) {
|
|
if(!regs.cop0.status.cu1) {
|
|
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
|
|
return;
|
|
}
|
|
|
|
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
|
|
if(addr & 7) {
|
|
FireException(regs, ExceptionCode::AddressErrorLoad, 0, regs.oldPC);
|
|
}
|
|
|
|
u32 physical;
|
|
if(!MapVAddr(regs, LOAD, addr, physical)) {
|
|
HandleTLBException(regs, addr);
|
|
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
|
} else {
|
|
u64 data = mem.Read64<false>(regs, physical, regs.oldPC);
|
|
SetReg<u64>(regs.cop0, FT(instr), data);
|
|
}
|
|
}
|
|
|
|
void Cop1::sdc1(Registers& regs, Mem& mem, u32 instr) {
|
|
if(!regs.cop0.status.cu1) {
|
|
FireException(regs, ExceptionCode::CoprocessorUnusable, 1, regs.oldPC);
|
|
return;
|
|
}
|
|
|
|
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
|
|
if(addr & 7) {
|
|
FireException(regs, ExceptionCode::AddressErrorStore, 0, regs.oldPC);
|
|
}
|
|
|
|
u32 physical;
|
|
if(!MapVAddr(regs, STORE, addr, physical)) {
|
|
HandleTLBException(regs, addr);
|
|
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
} else {
|
|
mem.Write64<false>(regs, physical, GetReg<u64>(regs.cop0, FT(instr)), regs.oldPC);
|
|
}
|
|
}
|
|
|
|
void Cop1::truncws(Registers& regs, u32 instr) {
|
|
float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
|
|
s32 result = (s32)truncf(fs);
|
|
SetReg<u32>(regs.cop0, FD(instr), result);
|
|
}
|
|
|
|
void Cop1::truncwd(Registers& regs, u32 instr) {
|
|
double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
|
|
s32 result = (s32)trunc(fs);
|
|
SetReg<u32>(regs.cop0, FD(instr), result);
|
|
}
|
|
|
|
void Cop1::truncls(Registers& regs, u32 instr) {
|
|
float fs = GetCop1Reg<float>(regs.cop0, FS(instr));
|
|
s64 result = (s64)truncf(fs);
|
|
SetReg<u64>(regs.cop0, FD(instr), result);
|
|
}
|
|
|
|
void Cop1::truncld(Registers& regs, u32 instr) {
|
|
double fs = GetCop1Reg<double>(regs.cop0, FS(instr));
|
|
s64 result = (s64)trunc(fs);
|
|
SetReg<u64>(regs.cop0, FD(instr), result);
|
|
}
|
|
|
|
void Cop1::mfc1(Registers& regs, u32 instr) {
|
|
regs.gpr[RT(instr)] = (s32)GetReg<u32>(regs.cop0, FS(instr));
|
|
}
|
|
|
|
void Cop1::dmfc1(Registers& regs, u32 instr) {
|
|
regs.gpr[RT(instr)] = (s64)GetReg<u64>(regs.cop0, FS(instr));
|
|
}
|
|
|
|
void Cop1::mtc1(Registers& regs, u32 instr) {
|
|
SetReg<u32>(regs.cop0, FS(instr), regs.gpr[RT(instr)]);
|
|
}
|
|
|
|
void Cop1::dmtc1(Registers& regs, u32 instr) {
|
|
SetReg<u64>(regs.cop0, FS(instr), regs.gpr[RT(instr)]);
|
|
}
|
|
|
|
} |