79 lines
2.0 KiB
C++
79 lines
2.0 KiB
C++
#include <core/mmio/SI.hpp>
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#include <core/Mem.hpp>
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#include <Scheduler.hpp>
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namespace n64 {
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SI::SI() {
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Reset();
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}
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void SI::Reset() {
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status.raw = 0;
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dramAddr = 0;
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pifAddr = 0;
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memset(&controller, 0, sizeof(Controller));
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}
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auto SI::Read(MI& mi, u32 addr) const -> u32 {
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switch(addr) {
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case 0x04800000: return dramAddr;
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case 0x04800004: case 0x04800010: return pifAddr;
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case 0x0480000C: return 0;
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case 0x04800018: {
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u32 val = 0;
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val |= status.dmaBusy;
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val |= (0 << 1);
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val |= (0 << 3);
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val |= (mi.miIntr.si << 12);
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return val;
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}
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default:
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util::panic("Unhandled SI[{:08X}] read\n", addr);
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}
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}
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void DMA(Mem& mem, Registers& regs) {
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MMIO& mmio = mem.mmio;
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SI& si = mmio.si;
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si.status.dmaBusy = false;
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if(si.toDram) {
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ProcessPIFCommands(mem.pifRam, si.controller, mem);
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for(int i = 0; i < 64; i++) {
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mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)] = mem.pifRam[i];
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}
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} else {
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for(int i = 0; i < 64; i++) {
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mem.pifRam[i] = mem.mmio.rdp.rdram[BYTE_ADDRESS(si.dramAddr + i)];
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}
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util::debug("SI DMA from PIF RAM to RDRAM ({:08X} to {:08X})\n", si.pifAddr, si.dramAddr);
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ProcessPIFCommands(mem.pifRam, si.controller, mem);
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}
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InterruptRaise(mem.mmio.mi, regs, Interrupt::SI);
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}
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void SI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
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switch(addr) {
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case 0x04800000:
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dramAddr = val & RDRAM_DSIZE;
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break;
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case 0x04800004: {
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pifAddr = val & 0x1FFFFFFF;
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status.dmaBusy = true;
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toDram = true;
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scheduler.enqueueRelative({SI_DMA_DELAY, DMA});
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} break;
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case 0x04800010: {
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pifAddr = val & 0x1FFFFFFF;
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status.dmaBusy = true;
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toDram = false;
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scheduler.enqueueRelative({SI_DMA_DELAY, DMA});
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util::debug("SI DMA from RDRAM to PIF RAM ({:08X} to {:08X})\n", dramAddr, val & 0x1FFFFFFF);
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} break;
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case 0x04800018:
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InterruptLower(mem.mmio.mi, regs, Interrupt::SI);
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break;
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default:
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util::panic("Unhandled SI[%08X] write (%08X)\n", addr, val);
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}
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}
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} |