930 lines
23 KiB
YAML
930 lines
23 KiB
YAML
test_cases:
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-
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input:
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bytes: [ 0x80, 0xa0, 0x40, 0x02 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "cmp %g1, %g2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g1
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-
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type: SPARC_OP_REG
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reg: g2
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-
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input:
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bytes: [ 0x85, 0xc2, 0x60, 0x08 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "jmpl %o1+8, %g2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEM
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mem_base: o1
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mem_disp: 0x8
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-
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type: SPARC_OP_REG
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reg: g2
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-
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input:
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bytes: [ 0x85, 0xe8, 0x20, 0x01 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "restore %g0, 1, %g2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g0
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-
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type: SPARC_OP_IMM
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imm: 0x1
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-
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type: SPARC_OP_REG
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reg: g2
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-
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input:
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bytes: [ 0x81, 0xe8, 0x00, 0x00 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "restore"
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-
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input:
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bytes: [ 0x90, 0x10, 0x20, 0x01 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "mov 1, %o0"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x1
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-
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type: SPARC_OP_REG
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reg: o0
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-
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input:
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bytes: [ 0xd5, 0xf6, 0x10, 0x16 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "casx [%i0], %l6, %o2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEM
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mem_base: i0
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-
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type: SPARC_OP_REG
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reg: l6
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-
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type: SPARC_OP_REG
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reg: o2
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-
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input:
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bytes: [ 0xd5, 0xe6, 0x10, 0x56 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "casa [%i0] #asi_pnf, %l6, %o2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEM
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mem_base: i0
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-
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type: SPARC_OP_ASI
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asi: SPARC_ASITAG_ASI_PNF
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-
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type: SPARC_OP_REG
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reg: l6
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-
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type: SPARC_OP_REG
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reg: o2
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-
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input:
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bytes: [ 0x81, 0x43, 0xe0, 0x01 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "membar #LoadLoad"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEMBAR_TAG
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membar_tag: SPARC_MEMBAR_TAG_LOADLOAD
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-
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input:
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bytes: [ 0x21, 0x00, 0x00, 0x0a ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "sethi 0xa, %l0"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0xa
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-
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type: SPARC_OP_REG
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reg: l0
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-
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input:
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bytes: [ 0x86, 0x00, 0x40, 0x02 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "add %g1, %g2, %g3"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g1
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-
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type: SPARC_OP_REG
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reg: g2
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-
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type: SPARC_OP_REG
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reg: g3
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-
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input:
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bytes: [ 0x01, 0x00, 0x00, 0x00 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "nop"
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-
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input:
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bytes: [ 0x12, 0xbf, 0xff, 0xff ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1020
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expected:
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insns:
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-
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asm_text: "bne 0x101c"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x101c
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cc: SPARC_CC_ICC_NE
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-
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input:
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bytes: [ 0x10, 0xbf, 0xff, 0xff ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1024
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expected:
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insns:
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-
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asm_text: "ba 0x1020"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x1020
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-
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input:
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bytes: [ 0xa0, 0x02, 0x00, 0x09 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "add %o0, %o1, %l0"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: o0
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-
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type: SPARC_OP_REG
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reg: o1
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-
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type: SPARC_OP_REG
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reg: l0
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-
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input:
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bytes: [ 0x0d, 0xbf, 0xff, 0xff ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x102c
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expected:
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insns:
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-
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asm_text: "fbg 0x1028"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x1028
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cc: SPARC_CC_FCC_G
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-
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input:
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bytes: [ 0xd4, 0x20, 0x60, 0x00 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "st %o2, [%g1]"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: o2
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-
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type: SPARC_OP_MEM
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mem_base: g1
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-
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input:
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bytes: [ 0xd4, 0x4e, 0x00, 0x16 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "ldsb [%i0+%l6], %o2"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_MEM
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mem_base: i0
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mem_index: l6
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-
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type: SPARC_OP_REG
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reg: o2
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-
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input:
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bytes: [ 0x2a, 0xc2, 0x80, 0x03 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x1048
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expected:
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insns:
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-
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asm_text: "brnz,a,pn %o2, 0x1054"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: o2
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-
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type: SPARC_OP_IMM
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imm: 0x1054
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hint: SPARC_HINT_A_PN
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cc: SPARC_CC_REG_NZ
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groups: [ jump, SPARC_FEATURE_IS64BIT ]
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-
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input:
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bytes: [ 0x22, 0xc8, 0x40, 0x00 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x10000
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expected:
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insns:
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-
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asm_text: "brz,a %g1, 0x10000"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g1
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-
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type: SPARC_OP_IMM
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imm: 0x10000
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hint: SPARC_HINT_A_PT
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cc: SPARC_CC_REG_Z
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groups: [ jump, SPARC_FEATURE_IS64BIT ]
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-
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input:
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bytes: [ 0x81, 0xa8, 0x0a, 0x24 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "fcmps %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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-
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type: SPARC_OP_REG
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reg: f4
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-
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input:
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bytes: [ 0x89, 0xa0, 0x10, 0x20 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "fstox %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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-
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type: SPARC_OP_REG
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reg: f4
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groups: [ SPARC_FEATURE_IS64BIT ]
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-
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input:
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bytes: [ 0x89, 0xa0, 0x1a, 0x60 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "fqtoi %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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-
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type: SPARC_OP_REG
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reg: f4
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-
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input:
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bytes: [ 0x89, 0xa0, 0x00, 0xe0 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x1000
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expected:
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insns:
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-
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asm_text: "fnegq %f0, %f4"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: f0
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-
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type: SPARC_OP_REG
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reg: f4
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-
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input:
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bytes: [ 0x40, 0x00, 0xb3, 0x12 ]
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arch: "sparc"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
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address: 0x00012d44
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expected:
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insns:
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-
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asm_text: "call 0x3f98c"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_IMM
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imm: 0x3f98c
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-
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input:
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bytes: [ 0x83, 0x88, 0x00, 0x17 ]
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arch: "CS_ARCH_SPARC"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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expected:
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insns:
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-
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asm_text: "pwr %g0, %l7, %psr"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: g0
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access: CS_AC_READ
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-
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type: SPARC_OP_REG
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reg: l7
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access: CS_AC_READ
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-
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type: SPARC_OP_REG
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reg: psr
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access: CS_AC_WRITE
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groups: [ HasPWRPSR ]
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-
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input:
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bytes: [ 0xa3, 0x48, 0x00, 0x00 ]
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arch: "CS_ARCH_SPARC"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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expected:
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insns:
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-
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asm_text: "rd %psr, %l1"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: psr
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access: CS_AC_READ
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-
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type: SPARC_OP_REG
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reg: l1
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access: CS_AC_WRITE
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-
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input:
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bytes: [ 0x81, 0x96, 0x20, 0x05 ]
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arch: "CS_ARCH_SPARC"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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expected:
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insns:
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-
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asm_text: "wr %i0, 5, %wim"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: i0
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access: CS_AC_READ
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-
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type: SPARC_OP_IMM
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imm: 5
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access: CS_AC_READ
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-
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type: SPARC_OP_REG
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reg: wim
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access: CS_AC_WRITE
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-
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input:
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bytes: [ 0xb1, 0x50, 0x00, 0x00 ]
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arch: "CS_ARCH_SPARC"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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expected:
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insns:
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-
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asm_text: "rd %wim, %i0"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: wim
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access: CS_AC_READ
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-
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type: SPARC_OP_REG
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reg: i0
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access: CS_AC_WRITE
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-
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input:
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bytes: [ 0x81, 0x9e, 0x20, 0x05 ]
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arch: "CS_ARCH_SPARC"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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expected:
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insns:
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-
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asm_text: "wr %i0, 5, %tbr"
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details:
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sparc:
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operands:
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-
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type: SPARC_OP_REG
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reg: i0
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access: CS_AC_READ
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-
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type: SPARC_OP_IMM
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imm: 5
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access: CS_AC_READ
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-
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type: SPARC_OP_REG
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reg: tbr
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access: CS_AC_WRITE
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-
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input:
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bytes: [ 0xb1, 0x58, 0x00, 0x00 ]
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arch: "CS_ARCH_SPARC"
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options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
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expected:
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insns:
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-
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asm_text: "rd %tbr, %i0"
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details:
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sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_REG
|
|
reg: tbr
|
|
access: CS_AC_READ
|
|
-
|
|
type: SPARC_OP_REG
|
|
reg: i0
|
|
access: CS_AC_WRITE
|
|
-
|
|
input:
|
|
bytes: [ 0x9f, 0xc2, 0x60, 0x08 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "call %o1+8"
|
|
is_alias: 1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_MEM
|
|
mem_base: o1
|
|
mem_disp: 8
|
|
-
|
|
input:
|
|
bytes: [ 0x10, 0xbf, 0xff, 0xe0 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
|
|
address: 0x0001bcf0
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "ba 0x1bc70"
|
|
is_alias: 1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_IMM
|
|
imm: 0x1bc70
|
|
access: CS_AC_READ
|
|
cc: SPARC_CC_ICC_A
|
|
groups: [ jump ]
|
|
-
|
|
input:
|
|
bytes: [ 0x10, 0xbf, 0xff, 0xe0 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
|
|
address: 0x0001bcf0
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "ba 0x1bc70"
|
|
is_alias: 1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_IMM
|
|
imm: 0x1bc70
|
|
access: CS_AC_READ
|
|
cc: SPARC_CC_ICC_A
|
|
groups: [ jump ]
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x20, 0x68, 0x04, 0x00 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x0
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "bn,a %xcc, 0x1000"
|
|
is_alias: -1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_IMM
|
|
access: CS_AC_READ
|
|
imm: 0x1000
|
|
cc: SPARC_CC_ICC_N
|
|
cc_field: SPARC_CC_FIELD_XCC
|
|
groups: [ jump, SPARC_FEATURE_IS64BIT ]
|
|
-
|
|
input:
|
|
bytes: [ 0x0e, 0x80, 0x04, 0x00 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x4
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "bvs 0x1004"
|
|
is_alias: 1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_IMM
|
|
access: CS_AC_READ
|
|
imm: 0x1004
|
|
cc: SPARC_CC_ICC_VS
|
|
cc_field: SPARC_CC_FIELD_ICC
|
|
groups: [ jump ]
|
|
-
|
|
input:
|
|
bytes: [ 0x85, 0xa8, 0x0a, 0xe4 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x8
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "fcmpeq %fcc2, %f0, %f4"
|
|
is_alias: -1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: f0
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: f4
|
|
cc_field: SPARC_CC_FIELD_FCC2
|
|
-
|
|
input:
|
|
bytes: [ 0x30, 0x68, 0x04, 0x00 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0xc
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "ba,a %xcc, 0x100c"
|
|
is_alias: -1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_IMM
|
|
access: CS_AC_READ
|
|
imm: 0x100c
|
|
cc: SPARC_CC_ICC_A
|
|
cc_field: SPARC_CC_FIELD_XCC
|
|
hint: SPARC_HINT_A_PT
|
|
groups: [ jump, SPARC_FEATURE_IS64BIT ]
|
|
-
|
|
input:
|
|
bytes: [ 0x1e, 0x48, 0x04, 0x00 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "bvc %icc, 0x1010"
|
|
is_alias: -1
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_IMM
|
|
access: CS_AC_READ
|
|
imm: 0x1010
|
|
cc: SPARC_CC_ICC_VC
|
|
cc_field: SPARC_CC_FIELD_ICC
|
|
groups: [ jump, HasV9 ]
|
|
-
|
|
input:
|
|
bytes: [ 0xd4, 0xee, 0x00, 0x96 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "ldstuba [%i0+%l6] 4, %o2"
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_MEM
|
|
access: CS_AC_READ_WRITE
|
|
mem_base: i0
|
|
mem_index: l6
|
|
-
|
|
type: SPARC_OP_ASI
|
|
access: CS_AC_READ
|
|
asi: SPARC_ASITAG_ASI_N
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_WRITE
|
|
reg: o2
|
|
-
|
|
input:
|
|
bytes: [ 0x83, 0x64, 0x80, 0x00 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movle %icc, %g0, %g1"
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: g0
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_WRITE
|
|
reg: g1
|
|
cc: SPARC_CC_ICC_LE
|
|
cc_field: SPARC_CC_FIELD_ICC
|
|
groups: [ HasV9 ]
|
|
-
|
|
input:
|
|
bytes: [ 0x83, 0x65, 0xf0, 0x50 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movvs %xcc, 0x50, %g1"
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_IMM
|
|
access: CS_AC_READ
|
|
imm: 0x50
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_WRITE
|
|
reg: g1
|
|
cc: SPARC_CC_ICC_VS
|
|
cc_field: SPARC_CC_FIELD_XCC
|
|
# groups: [ HasV9 ] - Bug: llvm-project/#142388
|
|
-
|
|
input:
|
|
bytes: [ 0x83, 0x7c, 0x04, 0x05 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movrz %l0, %g5, %g1"
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: l0
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: g5
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_WRITE
|
|
reg: g1
|
|
cc: SPARC_CC_REG_Z
|
|
# groups: [ HasV9 ] - Bug: llvm-project/#142388
|
|
-
|
|
input:
|
|
bytes: [ 0x83, 0x7c, 0x3c, 0x10 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "movrgez %l0, 16, %g1"
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: l0
|
|
-
|
|
type: SPARC_OP_IMM
|
|
access: CS_AC_READ
|
|
imm: 16
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_WRITE
|
|
reg: g1
|
|
cc: SPARC_CC_REG_GEZ
|
|
# groups: [ HasV9 ] - Bug: llvm-project/#142388
|
|
|
|
-
|
|
input:
|
|
bytes: [ 0x83, 0xd4, 0x00, 0x00 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "te %icc, %l0 + %g0"
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: l0
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: g0
|
|
cc: SPARC_CC_ICC_E
|
|
cc_field: SPARC_CC_FIELD_ICC
|
|
# groups: [ HasV9 ] - Bug: llvm-project/#142388
|
|
-
|
|
input:
|
|
bytes: [ 0x8f, 0xd4, 0x10, 0x00 ]
|
|
arch: "CS_ARCH_SPARC"
|
|
options: [ CS_OPT_DETAIL, CS_MODE_BIG_ENDIAN, CS_MODE_V9 ]
|
|
address: 0x10
|
|
expected:
|
|
insns:
|
|
-
|
|
asm_text: "tvs %xcc, %l0 + %g0"
|
|
details:
|
|
sparc:
|
|
operands:
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: l0
|
|
-
|
|
type: SPARC_OP_REG
|
|
access: CS_AC_READ
|
|
reg: g0
|
|
cc: SPARC_CC_ICC_VS
|
|
cc_field: SPARC_CC_FIELD_XCC
|
|
# groups: [ HasV9 ] - Bug: llvm-project/#142388
|