136 lines
4.0 KiB
C++
136 lines
4.0 KiB
C++
#include <core/RSP.hpp>
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#include <log.hpp>
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#include <core/Mem.hpp>
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#include <core/registers/Registers.hpp>
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namespace n64 {
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RSP::RSP() {
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Reset();
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}
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void RSP::Reset() {
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lastSuccessfulSPAddr.raw = 0;
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lastSuccessfulDRAMAddr.raw = 0;
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spStatus.raw = 0;
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spStatus.halt = true;
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oldPC = 0;
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pc = 0;
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nextPC = 4;
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spDMASPAddr.raw = 0;
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spDMADRAMAddr.raw = 0;
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spDMALen.raw = 0;
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memset(dmem, 0, DMEM_SIZE);
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memset(imem, 0, IMEM_SIZE);
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memset(vpr, 0, 32 * sizeof(VPR));
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memset(gpr, 0, 32 * sizeof(u32));
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memset(&vce, 0, sizeof(VPR));
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memset(&acc, 0, 3 * sizeof(VPR));
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memset(&vcc, 0, 2 * sizeof(VPR));
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memset(&vco, 0, 2 * sizeof(VPR));
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semaphore = false;
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divIn = 0;
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divOut = 0;
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divInLoaded = false;
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}
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/*
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FORCE_INLINE void logRSP(const RSP& rsp, const u32 instr) {
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Util::debug("{:04X} {:08X} ", rsp.oldPC, instr);
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for (auto gpr : rsp.gpr) {
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Util::debug("{:08X} ", gpr);
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}
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for (auto vpr : rsp.vpr) {
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for (int i = 0; i < 8; i++) {
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Util::debug("{:04X}", vpr.element[i]);
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}
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Util::debug(" ");
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}
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for (int i = 0; i < 8; i++) {
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Util::debug("{:04X}", rsp.acc.h.element[i]);
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}
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Util::debug(" ");
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for (int i = 0; i < 8; i++) {
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Util::debug("{:04X}", rsp.acc.m.element[i]);
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}
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Util::debug(" ");
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for (int i = 0; i < 8; i++) {
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Util::debug("{:04X}", rsp.acc.l.element[i]);
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}
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Util::debug(" {:04X} {:04X} {:02X}", rsp.GetVCC(), rsp.GetVCO(), rsp.GetVCE());
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Util::debug("DMEM: {:02X}{:02X}", rsp.dmem[0x3c4], rsp.dmem[0x3c5]);
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}
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*/
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auto RSP::Read(u32 addr) -> u32{
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switch (addr) {
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case 0x04040000: return lastSuccessfulSPAddr.raw & 0x1FF8;
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case 0x04040004: return lastSuccessfulDRAMAddr.raw & 0xFFFFF8;
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case 0x04040008:
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case 0x0404000C: return spDMALen.raw;
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case 0x04040010: return spStatus.raw;
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case 0x04040014: return spStatus.dmaFull;
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case 0x04040018: return 0;
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case 0x0404001C:
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return AcquireSemaphore();
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case 0x04080000: return pc & 0xFFC;
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default:
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Util::panic("Unimplemented SP register read {:08X}", addr);
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}
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}
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void RSP::WriteStatus(MI& mi, Registers& regs, u32 value) {
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auto write = SPStatusWrite{.raw = value};
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if(write.clearHalt && !write.setHalt) {
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spStatus.halt = false;
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}
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if(write.setHalt && !write.clearHalt) {
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regs.steps = 0;
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spStatus.halt = true;
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}
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if(write.clearBroke) spStatus.broke = false;
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if(write.clearIntr && !write.setIntr)
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InterruptLower(mi, regs, Interrupt::SP);
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if(write.setIntr && !write.clearIntr)
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InterruptRaise(mi, regs, Interrupt::SP);
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CLEAR_SET(spStatus.singleStep, write.clearSstep, write.setSstep);
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CLEAR_SET(spStatus.interruptOnBreak, write.clearIntrOnBreak, write.setIntrOnBreak);
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CLEAR_SET(spStatus.signal0, write.clearSignal0, write.setSignal0);
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CLEAR_SET(spStatus.signal1, write.clearSignal1, write.setSignal1);
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CLEAR_SET(spStatus.signal2, write.clearSignal2, write.setSignal2);
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CLEAR_SET(spStatus.signal3, write.clearSignal3, write.setSignal3);
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CLEAR_SET(spStatus.signal4, write.clearSignal4, write.setSignal4);
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CLEAR_SET(spStatus.signal5, write.clearSignal5, write.setSignal5);
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CLEAR_SET(spStatus.signal6, write.clearSignal6, write.setSignal6);
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CLEAR_SET(spStatus.signal7, write.clearSignal7, write.setSignal7);
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}
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void RSP::Write(Mem& mem, Registers& regs, u32 addr, u32 value) {
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MI& mi = mem.mmio.mi;
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switch (addr) {
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case 0x04040000: spDMASPAddr.raw = value & 0x1FF8; break;
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case 0x04040004: spDMADRAMAddr.raw = value & 0xFFFFF8; break;
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case 0x04040008: {
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spDMALen.raw = value;
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DMA<false>(spDMALen, mem.GetRDRAM(), *this, spDMASPAddr.bank);
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} break;
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case 0x0404000C: {
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spDMALen.raw = value;
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DMA<true>(spDMALen, mem.GetRDRAM(), *this, spDMASPAddr.bank);
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} break;
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case 0x04040010: WriteStatus(mi, regs, value); break;
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case 0x0404001C: ReleaseSemaphore(); break;
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case 0x04080000:
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if(spStatus.halt) {
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SetPC(value);
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} break;
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default:
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Util::panic("Unimplemented SP register write {:08X}, val: {:08X}", addr, value);
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}
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}
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}
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