583 lines
16 KiB
C++
583 lines
16 KiB
C++
#include <File.hpp>
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#include <Mem.hpp>
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#include <backend/RomHelpers.hpp>
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#include <cassert>
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#include <core/Interpreter.hpp>
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#include <core/registers/Registers.hpp>
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#include <unarr.h>
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namespace n64 {
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Mem::Mem(Registers ®s, ParallelRDP ¶llel) : mmio(*this, regs, parallel), flash(saveData) {
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rom.cart.resize(CART_SIZE);
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std::ranges::fill(rom.cart, 0);
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}
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void Mem::Reset() {
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std::ranges::fill(rom.cart, 0);
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flash.Reset();
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if (saveData.is_mapped()) {
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std::error_code error;
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saveData.sync(error);
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if (error) {
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Util::panic("Could not sync save data");
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}
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saveData.unmap();
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}
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mmio.Reset();
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}
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void Mem::LoadSRAM(SaveType save_type, fs::path path) {
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if (save_type == SAVE_SRAM_256k) {
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std::error_code error;
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if (!savePath.empty()) {
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path = savePath / path.filename();
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}
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sramPath = path.replace_extension(".sram").string();
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if (saveData.is_mapped()) {
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saveData.sync(error);
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if (error) {
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Util::panic("Could not sync {}", sramPath);
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}
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saveData.unmap();
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}
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auto sramVec = Util::ReadFileBinary(sramPath);
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if (sramVec.empty()) {
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Util::WriteFileBinary(std::array<u8, SRAM_SIZE>{}, sramPath);
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sramVec = Util::ReadFileBinary(sramPath);
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}
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if (sramVec.size() != SRAM_SIZE) {
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Util::panic("Corrupt SRAM!");
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}
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saveData = mio::make_mmap_sink(sramPath, 0, mio::map_entire_file, error);
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if (error) {
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Util::panic("Could not mmap {}", sramPath);
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}
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}
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}
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FORCE_INLINE void SetROMCIC(u32 checksum, ROM &rom) {
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switch (checksum) {
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case 0xEC8B1325:
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rom.cicType = CIC_NUS_7102;
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break; // 7102
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case 0x1DEB51A9:
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rom.cicType = CIC_NUS_6101;
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break; // 6101
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case 0xC08E5BD6:
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rom.cicType = CIC_NUS_6102_7101;
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break;
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case 0x03B8376A:
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rom.cicType = CIC_NUS_6103_7103;
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break;
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case 0xCF7F41DC:
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rom.cicType = CIC_NUS_6105_7105;
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break;
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case 0xD1059C6A:
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rom.cicType = CIC_NUS_6106_7106;
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break;
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default:
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Util::warn("Could not determine CIC TYPE! Checksum: 0x{:08X} is unknown!", checksum);
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rom.cicType = UNKNOWN_CIC_TYPE;
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break;
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}
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}
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std::vector<u8> Mem::OpenArchive(const std::string &path, size_t &sizeAdjusted) {
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const auto stream = ar_open_file(fs::path(path).string().c_str());
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if (!stream) {
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Util::panic("Could not open archive! Are you sure it's an archive?");
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}
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ar_archive *archive = ar_open_zip_archive(stream, false);
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if (!archive)
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archive = ar_open_rar_archive(stream);
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if (!archive)
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archive = ar_open_7z_archive(stream);
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if (!archive)
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archive = ar_open_tar_archive(stream);
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if (!archive) {
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ar_close(stream);
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Util::panic("Could not open archive! Are you sure it's a supported archive? (7z, zip, rar and tar are supported)");
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}
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std::vector<u8> buf{};
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std::vector<std::string> rom_exts{".n64", ".z64", ".v64", ".N64", ".Z64", ".V64"};
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while (ar_parse_entry(archive)) {
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auto filename = ar_entry_get_name(archive);
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auto extension = fs::path(filename).extension();
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if (std::ranges::any_of(rom_exts, [&](const auto &x) { return extension == x; })) {
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const auto size = ar_entry_get_size(archive);
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sizeAdjusted = Util::NextPow2(size);
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buf.resize(sizeAdjusted);
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ar_entry_uncompress(archive, buf.data(), size);
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break;
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}
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ar_close_archive(archive);
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ar_close(stream);
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Util::panic("Could not find any rom image in the archive!");
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}
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ar_close_archive(archive);
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ar_close(stream);
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return buf;
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}
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std::vector<u8> Mem::OpenROM(const std::string &filename, size_t &sizeAdjusted) {
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auto buf = Util::ReadFileBinary(filename);
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sizeAdjusted = Util::NextPow2(buf.size());
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return buf;
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}
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void Mem::LoadROM(const bool isArchive, const std::string &filename) {
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u32 endianness;
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{
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size_t sizeAdjusted;
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std::vector<u8> buf{};
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if (isArchive) {
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buf = OpenArchive(filename, sizeAdjusted);
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} else {
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buf = OpenROM(filename, sizeAdjusted);
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}
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endianness = bswap(*reinterpret_cast<u32 *>(buf.data()));
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Util::SwapN64Rom<true>(buf, endianness);
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std::ranges::copy(buf, rom.cart.begin());
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rom.mask = sizeAdjusted - 1;
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memcpy(&rom.header, buf.data(), sizeof(ROMHeader));
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}
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memcpy(rom.gameNameCart, rom.header.imageName, sizeof(rom.header.imageName));
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rom.header.clockRate = bswap(rom.header.clockRate);
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rom.header.programCounter = bswap(rom.header.programCounter);
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rom.header.release = bswap(rom.header.release);
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rom.header.crc1 = bswap(rom.header.crc1);
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rom.header.crc2 = bswap(rom.header.crc2);
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rom.header.unknown = bswap(rom.header.unknown);
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rom.header.unknown2 = bswap(rom.header.unknown2);
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rom.header.manufacturerId = bswap(rom.header.manufacturerId);
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rom.header.cartridgeId = bswap(rom.header.cartridgeId);
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rom.code[0] = rom.header.manufacturerId & 0xFF;
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rom.code[1] = (rom.header.cartridgeId >> 8) & 0xFF;
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rom.code[2] = rom.header.cartridgeId & 0xFF;
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rom.code[3] = '\0';
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for (int i = sizeof(rom.header.imageName) - 1; rom.gameNameCart[i] == ' '; i--) {
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rom.gameNameCart[i] = '\0';
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}
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const u32 checksum = Util::crc32(0, &rom.cart[0x40], 0x9c0);
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SetROMCIC(checksum, rom);
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endianness = bswap(*reinterpret_cast<u32 *>(rom.cart.data()));
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Util::SwapN64Rom(rom.cart, endianness);
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rom.pal = IsROMPAL();
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}
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template <>
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u8 Mem::Read(Registers ®s, const u32 paddr) {
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const SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u8>(paddr);
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case RSP_MEM_REGION:
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{
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const auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return src[BYTE_ADDRESS(paddr & 0xfff)];
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}
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case REGION_CART:
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return mmio.pi.BusRead<u8, false>(paddr);
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case 0x04040000 ... 0x040FFFFF:
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case 0x04100000 ... 0x041FFFFF:
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case 0x04600000 ... 0x048FFFFF:
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case 0x04300000 ... 0x044FFFFF:
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Util::panic("MMIO Read<u8>!\n");
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case AI_REGION:
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{
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const u32 w = mmio.ai.Read(paddr & ~3);
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const int offs = 3 - (paddr & 3);
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return w >> offs * 8 & 0xff;
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}
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case PIF_ROM_REGION:
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return si.pif.bootrom[BYTE_ADDRESS(paddr) - PIF_ROM_REGION_START];
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case PIF_RAM_REGION:
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return si.pif.ram[paddr - PIF_RAM_REGION_START];
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case 0x00800000 ... 0x03EFFFFF: // unused
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case 0x04200000 ... 0x042FFFFF: // unused
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case 0x04900000 ... 0x04FFFFFF: // unused
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case 0x1FC00800 ... 0xFFFFFFFF: // unused
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return 0;
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default:
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Util::panic("Unimplemented 8-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
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return 0;
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}
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}
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template <>
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u16 Mem::Read(Registers ®s, const u32 paddr) {
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const SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u16>(paddr);
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case RSP_MEM_REGION:
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{
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const auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u16>(src, HALF_ADDRESS(paddr & 0xfff));
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u16, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u16>(si.pif.bootrom, HALF_ADDRESS(paddr) - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return bswap(Util::ReadAccess<u16>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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Util::panic("Unimplemented 16-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
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return 0;
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}
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}
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template <>
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u32 Mem::Read(Registers ®s, const u32 paddr) {
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const SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u32>(paddr);
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case RSP_MEM_REGION:
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{
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const auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u32>(src, paddr & 0xfff);
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u32, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u32>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return bswap(Util::ReadAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03FFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
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return 0;
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}
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}
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template <>
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u64 Mem::Read(Registers ®s, const u32 paddr) {
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const SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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return mmio.rdp.ReadRDRAM<u64>(paddr);
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case RSP_MEM_REGION:
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{
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const auto &src = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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return Util::ReadAccess<u64>(src, paddr & 0xfff);
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}
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case MMIO_REGION:
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return mmio.Read(paddr);
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case REGION_CART:
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return mmio.pi.BusRead<u64, false>(paddr);
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case PIF_ROM_REGION:
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return Util::ReadAccess<u64>(si.pif.bootrom, paddr - PIF_ROM_REGION_START);
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case PIF_RAM_REGION:
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return bswap(Util::ReadAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START));
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case 0x1FC00800 ... 0xFFFFFFFF:
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return 0;
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default:
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Util::panic("Unimplemented 32-bit read at address {:08X} (PC = {:016X})", paddr, (u64)regs.pc);
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return 0;
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}
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}
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template <>
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void Mem::Write<u8>(Registers ®s, u32 paddr, u32 val) {
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SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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mmio.rdp.WriteRDRAM<u8>(paddr, val);
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break;
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case RSP_MEM_REGION:
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{
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val = val << (8 * (3 - (paddr & 3)));
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auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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paddr = (paddr & 0xFFF) & ~3;
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Util::WriteAccess<u32>(dest, paddr, val);
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}
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break;
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case REGION_CART:
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Util::trace("BusWrite<u8> @ {:08X} = {:02X}", paddr, val);
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mmio.pi.BusWrite<u8, false>(paddr, val);
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break;
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case MMIO_REGION:
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Util::panic("MMIO Write<u8>!");
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case PIF_RAM_REGION:
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val = val << (8 * (3 - (paddr & 3)));
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paddr = (paddr - PIF_RAM_REGION_START) & ~3;
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Util::WriteAccess<u32>(si.pif.ram, paddr, bswap(val));
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si.pif.ProcessCommands(*this);
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break;
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case PIF_ROM_REGION:
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case 0x1FC00800 ... 0x7FFFFFFF:
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case 0x80000000 ... 0xFFFFFFFF:
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break;
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default:
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Util::panic("Unimplemented 8-bit write at address {:08X} with value {:02X} (PC = {:016X})", paddr, val,
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(u64)regs.pc);
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}
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}
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template <>
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void Mem::Write<u16>(Registers ®s, u32 paddr, u32 val) {
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SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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mmio.rdp.WriteRDRAM<u16>(paddr, val);
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break;
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case RSP_MEM_REGION:
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{
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val = val << (16 * !(paddr & 2));
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auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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paddr = (paddr & 0xFFF) & ~3;
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Util::WriteAccess<u32>(dest, paddr, val);
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}
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break;
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case REGION_CART:
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Util::trace("BusWrite<u8> @ {:08X} = {:04X}", paddr, val);
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mmio.pi.BusWrite<u16, false>(paddr, val);
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break;
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case MMIO_REGION:
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Util::panic("MMIO Write<u16>!");
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case PIF_RAM_REGION:
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val = val << (16 * !(paddr & 2));
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paddr &= ~3;
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Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, bswap(val));
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si.pif.ProcessCommands(*this);
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break;
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case PIF_ROM_REGION:
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case 0x1FC00800 ... 0x7FFFFFFF:
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case 0x80000000 ... 0xFFFFFFFF:
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break;
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default:
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Util::panic("Unimplemented 16-bit write at address {:08X} with value {:04X} (PC = {:016X})", paddr, val,
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(u64)regs.pc);
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}
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}
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template <>
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void Mem::Write<u32>(Registers ®s, const u32 paddr, const u32 val) {
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SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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mmio.rdp.WriteRDRAM<u32>(paddr, val);
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break;
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case RSP_MEM_REGION:
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{
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auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
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}
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break;
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case REGION_CART:
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Util::trace("BusWrite<u8> @ {:08X} = {:08X}", paddr, val);
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mmio.pi.BusWrite<u32, false>(paddr, val);
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break;
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case MMIO_REGION:
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mmio.Write(paddr, val);
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break;
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case PIF_RAM_REGION:
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Util::WriteAccess<u32>(si.pif.ram, paddr - PIF_RAM_REGION_START, bswap(val));
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si.pif.ProcessCommands(*this);
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break;
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case 0x00800000 ... 0x03EFFFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x04FFFFFF:
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case PIF_ROM_REGION:
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case 0x1FC00800 ... 0x7FFFFFFF:
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case 0x80000000 ... 0xFFFFFFFF:
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break;
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default:
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Util::panic("Unimplemented 32-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
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(u64)regs.pc);
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}
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}
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void Mem::Write(const Registers ®s, const u32 paddr, u64 val) {
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SI &si = mmio.si;
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switch (paddr) {
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case RDRAM_REGION:
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mmio.rdp.WriteRDRAM<u64>(paddr, val);
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break;
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case RSP_MEM_REGION:
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{
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auto &dest = paddr & 0x1000 ? mmio.rsp.imem : mmio.rsp.dmem;
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val >>= 32;
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Util::WriteAccess<u32>(dest, paddr & 0xfff, val);
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}
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break;
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case REGION_CART:
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Util::trace("BusWrite<u8> @ {:08X} = {:016X}", paddr, val);
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mmio.pi.BusWrite<false>(paddr, val);
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break;
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|
case MMIO_REGION:
|
|
Util::panic("MMIO Write!");
|
|
case PIF_RAM_REGION:
|
|
Util::WriteAccess<u64>(si.pif.ram, paddr - PIF_RAM_REGION_START, bswap(val));
|
|
si.pif.ProcessCommands(*this);
|
|
break;
|
|
case 0x00800000 ... 0x03EFFFFF:
|
|
case 0x04200000 ... 0x042FFFFF:
|
|
case 0x04900000 ... 0x04FFFFFF:
|
|
case 0x1FC00000 ... 0x1FC007BF:
|
|
case 0x1FC00800 ... 0x7FFFFFFF:
|
|
case 0x80000000 ... 0xFFFFFFFF:
|
|
break;
|
|
default:
|
|
Util::panic("Unimplemented 64-bit write at address {:08X} with value {:0X} (PC = {:016X})", paddr, val,
|
|
(u64)regs.pc);
|
|
}
|
|
}
|
|
|
|
template <>
|
|
u32 Mem::BackupRead<u32>(const u32 addr) {
|
|
switch (saveType) {
|
|
case SAVE_NONE:
|
|
return 0;
|
|
case SAVE_EEPROM_4k:
|
|
case SAVE_EEPROM_16k:
|
|
Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
|
|
return 0;
|
|
case SAVE_FLASH_1m:
|
|
return flash.Read<u32>(addr);
|
|
case SAVE_SRAM_256k:
|
|
return 0xFFFFFFFF;
|
|
default:
|
|
Util::panic("Backup read word with unknown save type");
|
|
}
|
|
}
|
|
|
|
template <>
|
|
u8 Mem::BackupRead<u8>(const u32 addr) {
|
|
switch (saveType) {
|
|
case SAVE_NONE:
|
|
return 0;
|
|
case SAVE_EEPROM_4k:
|
|
case SAVE_EEPROM_16k:
|
|
Util::warn("Accessing cartridge backup type SAVE_EEPROM, returning 0 for word read");
|
|
return 0;
|
|
case SAVE_FLASH_1m:
|
|
return flash.Read<u8>(addr);
|
|
case SAVE_SRAM_256k:
|
|
if (saveData.is_mapped()) {
|
|
assert(addr < saveData.size());
|
|
return saveData[addr];
|
|
} else {
|
|
Util::panic("Invalid backup Read<u8> if save data is not initialized");
|
|
}
|
|
default:
|
|
Util::panic("Backup read word with unknown save type");
|
|
}
|
|
}
|
|
|
|
template <>
|
|
void Mem::BackupWrite<u32>(const u32 addr, const u32 val) {
|
|
switch (saveType) {
|
|
case SAVE_NONE:
|
|
Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
|
|
break;
|
|
case SAVE_EEPROM_4k:
|
|
case SAVE_EEPROM_16k:
|
|
Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
|
|
case SAVE_FLASH_1m:
|
|
flash.Write<u32>(addr, val);
|
|
break;
|
|
case SAVE_SRAM_256k:
|
|
break;
|
|
default:
|
|
Util::panic("Backup read word with unknown save type");
|
|
}
|
|
}
|
|
|
|
template <>
|
|
void Mem::BackupWrite<u8>(const u32 addr, const u8 val) {
|
|
switch (saveType) {
|
|
case SAVE_NONE:
|
|
Util::warn("Accessing cartridge with save type SAVE_NONE in write word");
|
|
break;
|
|
case SAVE_EEPROM_4k:
|
|
case SAVE_EEPROM_16k:
|
|
Util::panic("Accessing cartridge with save type SAVE_EEPROM in write word");
|
|
case SAVE_FLASH_1m:
|
|
flash.Write<u8>(addr, val);
|
|
break;
|
|
case SAVE_SRAM_256k:
|
|
if (saveData.is_mapped()) {
|
|
assert(addr < saveData.size());
|
|
saveData[addr] = val;
|
|
} else {
|
|
Util::panic("Invalid backup Write<u8> if save data is not initialized");
|
|
}
|
|
break;
|
|
default:
|
|
Util::panic("Backup read word with unknown save type");
|
|
}
|
|
}
|
|
|
|
std::vector<u8> Mem::Serialize() {
|
|
std::vector<u8> res{};
|
|
|
|
auto sMMIO = mmio.Serialize();
|
|
auto sFLASH = flash.Serialize();
|
|
mmioSize = sMMIO.size();
|
|
flashSize = sFLASH.size();
|
|
|
|
res.insert(res.begin(), sMMIO.begin(), sMMIO.end());
|
|
res.insert(res.end(), sFLASH.begin(), sFLASH.end());
|
|
res.insert(res.end(), saveData.begin(), saveData.end());
|
|
|
|
return res;
|
|
}
|
|
|
|
void Mem::Deserialize(const std::vector<u8> &data) {
|
|
mmio.Deserialize(std::vector(data.begin(), data.begin() + mmioSize));
|
|
flash.Deserialize(std::vector(data.begin() + mmioSize, data.begin() + mmioSize + flashSize));
|
|
memcpy(saveData.data(), data.data() + mmioSize + flashSize, saveData.size());
|
|
}
|
|
} // namespace n64
|