229 lines
9.7 KiB
C++
229 lines
9.7 KiB
C++
#include <Mem.hpp>
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#include <fstream>
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#include <util.hpp>
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#include <n64/core/cpu/Registers.hpp>
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#include <n64/core/cpu/registers/Cop0.hpp>
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#include <n64/core/Cpu.hpp>
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namespace n64 {
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Mem::Mem() {
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Reset();
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}
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void Mem::Reset() {
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sram.resize(SRAM_SIZE);
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std::fill(sram.begin(), sram.end(), 0);
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romMask = 0;
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mmio.Reset();
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}
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void Mem::LoadROM(const std::string& filename) {
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std::ifstream file(filename, std::ios::binary);
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file.unsetf(std::ios::skipws);
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if(!file.is_open()) {
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util::panic("Unable to open {}!", filename);
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}
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file.seekg(0, std::ios::end);
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auto size = file.tellg();
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auto sizeAdjusted = util::NextPow2(size);
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romMask = sizeAdjusted - 1;
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file.seekg(0, std::ios::beg);
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std::fill(cart.begin(), cart.end(), 0);
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cart.resize(sizeAdjusted);
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cart.insert(cart.begin(), std::istream_iterator<u8>(file), std::istream_iterator<u8>());
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file.close();
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util::SwapN64Rom(sizeAdjusted, cart.data());
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memcpy(mmio.rsp.dmem, cart.data(), 0x1000);
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}
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template <bool tlb>
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inline bool MapVAddr(Registers& regs, TLBAccessType accessType, u32 vaddr, u32& paddr) {
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paddr = vaddr & 0x1FFFFFFF;
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if constexpr(!tlb) return true;
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switch(vaddr >> 29) {
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case 0 ... 3: case 7:
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return ProbeTLB(regs, accessType, s64(s32(vaddr)), paddr, nullptr);
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case 4 ... 5: return true;
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case 6: util::panic("Unimplemented virtual mapping in KSSEG! ({:08X})\n", vaddr);
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default:
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util::panic("Should never end up in default case in map_vaddr! ({:08X})\n", vaddr);
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}
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return false;
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}
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template <class T, bool tlb>
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T Mem::Read(Registers& regs, u32 vaddr, s64 pc) {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, LOAD, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, pc);
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}
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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if constexpr (sizeof(T) == 1) {
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return util::ReadAccess<T>(mmio.rdp.dram.data(), BYTE_ADDRESS(paddr) & RDRAM_DSIZE);
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} else if constexpr (sizeof(T) == 2) {
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return util::ReadAccess<T>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr) & RDRAM_DSIZE);
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} else {
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return util::ReadAccess<T>(mmio.rdp.dram.data(), paddr & RDRAM_DSIZE);
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}
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case 0x04000000 ... 0x04000FFF:
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if constexpr (sizeof(T) == 1) {
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return util::ReadAccess<T>(mmio.rsp.dmem, BYTE_ADDRESS(paddr) & DMEM_DSIZE);
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} else if constexpr (sizeof(T) == 2) {
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return util::ReadAccess<T>(mmio.rsp.dmem, HALF_ADDRESS(paddr) & DMEM_DSIZE);
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} else {
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return util::ReadAccess<T>(mmio.rsp.dmem, paddr & DMEM_DSIZE);
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}
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case 0x04001000 ... 0x04001FFF:
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if constexpr (sizeof(T) == 1) {
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return util::ReadAccess<T>(mmio.rsp.imem, BYTE_ADDRESS(paddr) & IMEM_DSIZE);
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} else if constexpr (sizeof(T) == 2) {
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return util::ReadAccess<T>(mmio.rsp.imem, HALF_ADDRESS(paddr) & IMEM_DSIZE);
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} else {
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return util::ReadAccess<T>(mmio.rsp.imem, paddr & IMEM_DSIZE);
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}
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: return mmio.Read(paddr);
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case 0x10000000 ... 0x1FBFFFFF:
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if constexpr (sizeof(T) == 1) {
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return util::ReadAccess<T>(cart.data(), BYTE_ADDRESS(paddr) & romMask);
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} else if constexpr (sizeof(T) == 2) {
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return util::ReadAccess<T>(cart.data(), HALF_ADDRESS(paddr) & romMask);
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} else {
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return util::ReadAccess<T>(cart.data(), paddr & romMask);
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}
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case 0x1FC00000 ... 0x1FC007BF:
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if constexpr (sizeof(T) == 1) {
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return util::ReadAccess<T>(pifBootrom, BYTE_ADDRESS(paddr) & PIF_BOOTROM_DSIZE);
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} else if constexpr (sizeof(T) == 2) {
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return util::ReadAccess<T>(pifBootrom, HALF_ADDRESS(paddr) & PIF_BOOTROM_DSIZE);
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} else {
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return util::ReadAccess<T>(pifBootrom, paddr & PIF_BOOTROM_DSIZE);
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}
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case 0x1FC007C0 ... 0x1FC007FF:
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if constexpr (sizeof(T) == 1) {
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return util::ReadAccess<T>(pifRam, BYTE_ADDRESS(paddr) & PIF_RAM_DSIZE);
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} else if constexpr (sizeof(T) == 2) {
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return util::ReadAccess<T>(pifRam, HALF_ADDRESS(paddr) & PIF_RAM_DSIZE);
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} else {
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return util::ReadAccess<T>(pifRam, paddr & PIF_RAM_DSIZE);
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}
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case 0x00800000 ... 0x03FFFFFF: case 0x04002000 ... 0x0403FFFF:
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case 0x04200000 ... 0x042FFFFF:
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case 0x04900000 ... 0x07FFFFFF: case 0x08000000 ... 0x0FFFFFFF:
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case 0x80000000 ... 0xFFFFFFFF: case 0x1FC00800 ... 0x7FFFFFFF: return 0;
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default: util::panic("Unimplemented {}-bit read at address {:08X} (PC = {:016X})\n", sizeof(T) * 8, paddr, regs.pc);
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}
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return 0;
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}
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template u8 Mem::Read<u8>(Registers& regs, u32 vaddr, s64 pc);
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template u16 Mem::Read<u16>(Registers& regs, u32 vaddr, s64 pc);
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template u32 Mem::Read<u32>(Registers& regs, u32 vaddr, s64 pc);
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template u64 Mem::Read<u64>(Registers& regs, u32 vaddr, s64 pc);
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template u8 Mem::Read<u8, false>(Registers& regs, u32 vaddr, s64 pc);
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template u16 Mem::Read<u16, false>(Registers& regs, u32 vaddr, s64 pc);
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template u32 Mem::Read<u32, false>(Registers& regs, u32 vaddr, s64 pc);
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template u64 Mem::Read<u64, false>(Registers& regs, u32 vaddr, s64 pc);
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template s8 Mem::Read<s8>(Registers& regs, u32 vaddr, s64 pc);
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template s16 Mem::Read<s16>(Registers& regs, u32 vaddr, s64 pc);
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template s32 Mem::Read<s32>(Registers& regs, u32 vaddr, s64 pc);
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template s64 Mem::Read<s64>(Registers& regs, u32 vaddr, s64 pc);
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template s8 Mem::Read<s8, false>(Registers& regs, u32 vaddr, s64 pc);
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template s16 Mem::Read<s16, false>(Registers& regs, u32 vaddr, s64 pc);
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template s32 Mem::Read<s32, false>(Registers& regs, u32 vaddr, s64 pc);
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template s64 Mem::Read<s64, false>(Registers& regs, u32 vaddr, s64 pc);
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template <class T, bool tlb>
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void Mem::Write(Registers& regs, u32 vaddr, T val, s64 pc) {
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u32 paddr = vaddr;
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if(!MapVAddr<tlb>(regs, STORE, vaddr, paddr)) {
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HandleTLBException(regs, vaddr);
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FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, pc);
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}
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switch(paddr) {
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case 0x00000000 ... 0x007FFFFF:
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if constexpr (sizeof(T) == 1) {
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util::WriteAccess<T>(mmio.rdp.dram.data(), BYTE_ADDRESS(paddr) & RDRAM_DSIZE, val);
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} else if constexpr (sizeof(T) == 2) {
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util::WriteAccess<T>(mmio.rdp.dram.data(), HALF_ADDRESS(paddr) & RDRAM_DSIZE, val);
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} else {
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util::WriteAccess<T>(mmio.rdp.dram.data(), paddr & RDRAM_DSIZE, val);
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}
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break;
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case 0x04000000 ... 0x04000FFF:
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if constexpr (sizeof(T) == 1) {
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util::WriteAccess<T>(mmio.rsp.dmem, BYTE_ADDRESS(paddr) & DMEM_DSIZE, val);
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} else if constexpr (sizeof(T) == 2) {
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util::WriteAccess<T>(mmio.rsp.dmem, HALF_ADDRESS(paddr) & DMEM_DSIZE, val);
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} else {
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util::WriteAccess<T>(mmio.rsp.dmem, paddr & DMEM_DSIZE, val);
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}
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break;
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case 0x04001000 ... 0x04001FFF:
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if constexpr (sizeof(T) == 1) {
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util::WriteAccess<T>(mmio.rsp.imem, BYTE_ADDRESS(paddr) & IMEM_DSIZE, val);
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} else if constexpr (sizeof(T) == 2) {
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util::WriteAccess<T>(mmio.rsp.imem, HALF_ADDRESS(paddr) & IMEM_DSIZE, val);
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} else {
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util::WriteAccess<T>(mmio.rsp.imem, paddr & IMEM_DSIZE, val);
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}
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break;
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case 0x04040000 ... 0x040FFFFF: case 0x04100000 ... 0x041FFFFF:
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case 0x04300000 ... 0x044FFFFF: case 0x04500000 ... 0x048FFFFF: mmio.Write(*this, regs, paddr, val); break;
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case 0x10000000 ... 0x13FF0013: break;
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case 0x13FF0014: {
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if(val < ISVIEWER_SIZE) {
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char* message = (char*)calloc(val + 1, 1);
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memcpy(message, isviewer, val);
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printf("%s", message);
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free(message);
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}
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} break;
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case 0x13FF0020 ... 0x13FFFFFF:
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util::WriteAccess<T>(isviewer, paddr & ISVIEWER_DSIZE, be32toh(val));
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break;
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case 0x1FC007C0 ... 0x1FC007FF:
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if constexpr (sizeof(T) == 1) {
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util::WriteAccess<T>(pifRam, BYTE_ADDRESS(paddr) & PIF_RAM_DSIZE, val);
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} else if constexpr (sizeof(T) == 2) {
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util::WriteAccess<T>(pifRam, HALF_ADDRESS(paddr) & PIF_RAM_DSIZE, val);
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} else {
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util::WriteAccess<T>(pifRam, paddr & PIF_RAM_DSIZE, val);
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}
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ProcessPIFCommands(pifRam, mmio.si.controller, *this);
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break;
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case 0x00800000 ... 0x03FFFFFF: case 0x04002000 ... 0x0403FFFF:
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case 0x04200000 ... 0x042FFFFF: case 0x04900000 ... 0x07FFFFFF:
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case 0x08000000 ... 0x0FFFFFFF:
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case 0x1FC00800 ... 0x7FFFFFFF: case 0x80000000 ... 0xFFFFFFFF: break;
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default: util::panic("Unimplemented {}-bit write at address {:08X} with value {:0X} (PC = {:016X})\n", sizeof(T) * 8, paddr, val, regs.pc);
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}
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}
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template void Mem::Write<u8>(Registers& regs, u32 vaddr, u8 val, s64 pc);
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template void Mem::Write<u16>(Registers& regs, u32 vaddr, u16 val, s64 pc);
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template void Mem::Write<u32>(Registers& regs, u32 vaddr, u32 val, s64 pc);
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template void Mem::Write<u64>(Registers& regs, u32 vaddr, u64 val, s64 pc);
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template void Mem::Write<u8, false>(Registers& regs, u32 vaddr, u8 val, s64 pc);
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template void Mem::Write<u16, false>(Registers& regs, u32 vaddr, u16 val, s64 pc);
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template void Mem::Write<u32, false>(Registers& regs, u32 vaddr, u32 val, s64 pc);
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template void Mem::Write<u64, false>(Registers& regs, u32 vaddr, u64 val, s64 pc);
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template void Mem::Write<s8>(Registers& regs, u32 vaddr, s8 val, s64 pc);
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template void Mem::Write<s16>(Registers& regs, u32 vaddr, s16 val, s64 pc);
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template void Mem::Write<s32>(Registers& regs, u32 vaddr, s32 val, s64 pc);
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template void Mem::Write<s64>(Registers& regs, u32 vaddr, s64 val, s64 pc);
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template void Mem::Write<s8, false>(Registers& regs, u32 vaddr, s8 val, s64 pc);
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template void Mem::Write<s16, false>(Registers& regs, u32 vaddr, s16 val, s64 pc);
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template void Mem::Write<s32, false>(Registers& regs, u32 vaddr, s32 val, s64 pc);
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template void Mem::Write<s64, false>(Registers& regs, u32 vaddr, s64 val, s64 pc);
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} |