497 lines
18 KiB
C++
497 lines
18 KiB
C++
#include <core/mmio/PI.hpp>
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#include <log.hpp>
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#include <Core.hpp>
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#include <Scheduler.hpp>
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namespace n64 {
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PI::PI(Mem& mem, Registers& regs) : mem(mem), regs(regs) {
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Reset();
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}
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void PI::Reset() {
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dmaBusy = false;
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ioBusy = false;
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latch = 0;
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dramAddr = 0;
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cartAddr = 0;
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rdLen = 0;
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wrLen = 0;
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piBsdDom1Lat = 0;
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piBsdDom2Lat = 0;
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piBsdDom1Pwd = 0;
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piBsdDom2Pwd = 0;
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piBsdDom1Pgs = 0;
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piBsdDom2Pgs = 0;
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piBsdDom1Rls = 0;
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piBsdDom2Rls = 0;
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}
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bool PI::WriteLatch(u32 value) {
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if (ioBusy) {
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return false;
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} else {
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ioBusy = true;
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latch = value;
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scheduler.EnqueueRelative(100, PI_BUS_WRITE_COMPLETE);
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return true;
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}
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}
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bool PI::ReadLatch() {
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if (ioBusy) [[unlikely]] {
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ioBusy = false;
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regs.CpuStall(scheduler.Remove(PI_BUS_WRITE_COMPLETE));
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return false;
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}
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return true;
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}
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template<> auto PI::BusRead<u8, true>(u32 addr) -> u8 {
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, returning FF because it is not emulated", addr);
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case REGION_PI_64DD_REG:
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Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, returning FF because it is not emulated", addr);
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case REGION_PI_64DD_ROM:
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Util::warn("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, returning FF because it is not emulated", addr);
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return 0xFF;
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case REGION_PI_SRAM:
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return mem.BackupRead<u8>(addr - SREGION_PI_SRAM);
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case REGION_PI_ROM: {
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// round to nearest 4 byte boundary, keeping old LSB
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u32 index = BYTE_ADDRESS(addr) - SREGION_PI_ROM;
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if (index >= mem.rom.cart.size()) {
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Util::warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM! ({}/0x{:016X})", addr, index, index, mem.rom.cart.size(), mem.rom.cart.size());
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return 0xFF;
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}
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return mem.rom.cart[index];
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}
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template<> auto PI::BusRead<u8, false>(u32 addr) -> u8 {
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if (!ReadLatch()) [[unlikely]] {
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return latch >> 24;
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}
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, returning FF because it is not emulated", addr);
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case REGION_PI_64DD_REG:
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Util::panic("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, returning FF because it is not emulated", addr);
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case REGION_PI_64DD_ROM:
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Util::warn("Reading byte from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, returning FF because it is not emulated", addr);
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return 0xFF;
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case REGION_PI_SRAM:
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return mem.BackupRead<u8>(addr - SREGION_PI_SRAM);
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case REGION_PI_ROM: {
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addr = (addr + 2) & ~2;
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// round to nearest 4 byte boundary, keeping old LSB
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u32 index = BYTE_ADDRESS(addr) - SREGION_PI_ROM;
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if (index >= mem.rom.cart.size()) {
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Util::warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM! ({}/0x{:016X})", addr, index, index, mem.rom.cart.size(), mem.rom.cart.size());
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return 0xFF;
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}
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return mem.rom.cart[index];
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}
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template<> void PI::BusWrite<u8, true>(u32 addr, u32 val) {
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::panic("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
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case REGION_PI_64DD_REG:
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if (addr == 0x05000020) {
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fprintf(stderr, "%c", val);
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} else {
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Util::warn("Writing byte 0x{:02X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!", val, addr);
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}
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break;
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case REGION_PI_64DD_ROM:
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Util::panic("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
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case REGION_PI_SRAM:
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mem.BackupWrite<u8>(addr - SREGION_PI_SRAM, val);
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break;
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case REGION_PI_ROM:
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Util::warn("Writing byte 0x{:02X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
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break;
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template<> void PI::BusWrite<u8, false>(u32 addr, u32 val) {
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u8 latch_shift = 24 - (addr & 1) * 8;
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if (!WriteLatch(val << latch_shift) && addr != 0x05000020) [[unlikely]] {
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return;
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}
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BusWrite<u8, true>(addr, val);
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}
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template <> auto PI::BusRead<u16, false>(u32 addr) -> u16 {
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if (!ReadLatch()) [[unlikely]] {
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return latch >> 16;
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}
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, returning FF because it is not emulated", addr);
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case REGION_PI_64DD_REG:
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Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, returning FF because it is not emulated", addr);
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case REGION_PI_64DD_ROM:
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Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, returning FF because it is not emulated", addr);
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case REGION_PI_SRAM:
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Util::panic("Reading half from address 0x{:08X} in unsupported region: REGION_PI_SRAM", addr);
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case REGION_PI_ROM: {
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addr = (addr + 2) & ~3;
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u32 index = HALF_ADDRESS(addr) - SREGION_PI_ROM;
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if (index > mem.rom.cart.size() - 1) {
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Util::panic("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
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}
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return Util::ReadAccess<u16>(mem.rom.cart, index);
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}
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template <> auto PI::BusRead<u16, true>(u32 addr) -> u16 {
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return BusRead<u16, false>(addr);
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}
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template <> void PI::BusWrite<u16, false>(u32 addr, u32 val) {
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if (!WriteLatch(val << 16)) [[unlikely]] {
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return;
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}
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
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case REGION_PI_64DD_REG:
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Util::panic("Writing half 0x{:04X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!", val, addr);
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case REGION_PI_64DD_ROM:
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Util::panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
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case REGION_PI_SRAM:
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Util::panic("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_SRAM", val, addr);
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case REGION_PI_ROM:
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Util::warn("Writing half 0x{:04X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
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break;
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template <> void PI::BusWrite<u16, true>(u32 addr, u32 val) {
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BusWrite<u16, false>(addr, val);
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}
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template <> auto PI::BusRead<u32, false>(u32 addr) -> u32 {
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if (!ReadLatch()) [[unlikely]] {
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return latch;
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}
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN - This is the N64DD, returning FF because it is not emulated", addr);
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return 0xFF;
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case REGION_PI_64DD_REG:
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Util::warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG - This is the N64DD, returning FF because it is not emulated", addr);
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return 0xFF;
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case REGION_PI_64DD_ROM:
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Util::warn("Reading word from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM - This is the N64DD, returning FF because it is not emulated", addr);
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return 0xFF;
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case REGION_PI_SRAM:
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return mem.BackupRead<u32>(addr);
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case REGION_PI_ROM: {
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u32 index = addr - SREGION_PI_ROM;
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if (index > mem.rom.cart.size() - 3) { // -3 because we're reading an entire word
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switch (addr) {
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case REGION_CART_ISVIEWER_BUFFER:
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return htobe32(Util::ReadAccess<u32>(mem.isviewer, addr - SREGION_CART_ISVIEWER_BUFFER));
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case CART_ISVIEWER_FLUSH:
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Util::panic("Read from ISViewer flush!");
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default: break;
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}
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Util::warn("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
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return 0;
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} else {
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return Util::ReadAccess<u32>(mem.rom.cart, index);
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}
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}
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template <> auto PI::BusRead<u32, true>(u32 addr) -> u32 {
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return BusRead<u32, false>(addr);
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}
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template <> void PI::BusWrite<u32, false>(u32 addr, u32 val) {
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switch (addr) {
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case REGION_PI_UNKNOWN:
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if (!WriteLatch(val)) [[unlikely]] {
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return;
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}
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Util::warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
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return;
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case REGION_PI_64DD_REG:
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if (!WriteLatch(val)) [[unlikely]] {
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return;
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}
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Util::warn("Writing word 0x{:08X} to address 0x{:08X} in region: REGION_PI_64DD_ROM, this is the 64DD, ignoring!", val, addr);
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return;
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case REGION_PI_64DD_ROM:
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if (!WriteLatch(val)) [[unlikely]] {
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return;
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}
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Util::warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
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return;
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case REGION_PI_SRAM:
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if (!WriteLatch(val)) [[unlikely]] {
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return;
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}
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mem.BackupWrite<u32>(addr - SREGION_PI_SRAM, val);
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return;
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case REGION_PI_ROM:
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switch (addr) {
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case REGION_CART_ISVIEWER_BUFFER:
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Util::WriteAccess<u32>(mem.isviewer, addr - SREGION_CART_ISVIEWER_BUFFER, be32toh(val));
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break;
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case CART_ISVIEWER_FLUSH: {
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if (val < CART_ISVIEWER_SIZE) {
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std::string message(val + 1, 0);
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std::copy(mem.isviewer.begin(), mem.isviewer.begin() + val, message.begin());
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Util::print<Util::Always>("{}", message);
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} else {
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Util::panic("ISViewer buffer size is emulated at {} bytes, but received a flush command for {} bytes!", CART_ISVIEWER_SIZE, val);
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}
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break;
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}
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default:
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if (!WriteLatch(val)) [[unlikely]] {
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Util::warn("Couldn't latch PI bus, ignoring write to REGION_PI_ROM");
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return;
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}
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Util::warn("Writing word 0x{:08X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
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}
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return;
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template <>
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void PI::BusWrite<u32, true>(u32 addr, u32 val) {
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BusWrite<u32, false>(addr, val);
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}
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template <> auto PI::BusRead<u64, false>(u32 addr) -> u64 {
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if (!ReadLatch()) [[unlikely]] {
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return (u64)latch << 32;
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}
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", addr);
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case REGION_PI_64DD_REG:
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Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_64DD_REG", addr);
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case REGION_PI_64DD_ROM:
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Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", addr);
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case REGION_PI_SRAM:
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Util::panic("Reading dword from address 0x{:08X} in unsupported region: REGION_PI_SRAM", addr);
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case REGION_PI_ROM: {
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u32 index = addr - SREGION_PI_ROM;
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if (index > mem.rom.cart.size() - 7) { // -7 because we're reading an entire dword
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Util::panic("Address 0x{:08X} accessed an index {}/0x{:X} outside the bounds of the ROM!", addr, index, index);
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}
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return Util::ReadAccess<u64>(mem.rom.cart, index);
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}
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default:
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Util::panic("Should never end up here! Access to address {:08X} which did not match any PI bus regions!", addr);
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}
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}
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template <> auto PI::BusRead<u64, true>(u32 addr) -> u64 {
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return BusRead<u64, false>(addr);
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}
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template <> void PI::BusWrite<false>(u32 addr, u64 val) {
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if (!WriteLatch(val >> 32)) [[unlikely]] {
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return;
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}
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switch (addr) {
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case REGION_PI_UNKNOWN:
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Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_UNKNOWN", val, addr);
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case REGION_PI_64DD_REG:
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Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_REG", val, addr);
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case REGION_PI_64DD_ROM:
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Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_64DD_ROM", val, addr);
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case REGION_PI_SRAM:
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Util::panic("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_SRAM", val, addr);
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case REGION_PI_ROM:
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Util::warn("Writing dword 0x{:016X} to address 0x{:08X} in unsupported region: REGION_PI_ROM", val, addr);
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break;
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default:
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Util::panic("Should never end up here! Access to address %08X which did not match any PI bus regions!", addr);
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}
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}
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template <> void PI::BusWrite<true>(u32 addr, u64 val) {
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BusWrite<false>(addr, val);
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}
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auto PI::Read(u32 addr) const -> u32 {
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switch(addr) {
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case 0x04600000: return dramAddr & 0x00FFFFFE;
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case 0x04600004: return cartAddr & 0xFFFFFFFE;
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case 0x04600008: return rdLen;
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case 0x0460000C: return wrLen;
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case 0x04600010: {
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u32 value = 0;
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value |= (dmaBusy << 0); // Is PI DMA active? No, because it's instant
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value |= (ioBusy << 1); // Is PI IO busy? No, because it's instant
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value |= (0 << 2); // PI IO error?
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value |= (mem.mmio.mi.miIntr.pi << 3); // PI interrupt?
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return value;
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}
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case 0x04600014: return piBsdDom1Lat;
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case 0x04600018: return piBsdDom1Pwd;
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case 0x0460001C: return piBsdDom1Pgs;
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case 0x04600020: return piBsdDom1Rls;
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case 0x04600024: return piBsdDom2Lat;
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case 0x04600028: return piBsdDom2Pwd;
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case 0x0460002C: return piBsdDom2Pgs;
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case 0x04600030: return piBsdDom2Rls;
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default:
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Util::panic("Unhandled PI[{:08X}] read", addr);
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}
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}
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u8 PI::GetDomain(u32 address) {
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switch (address) {
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case REGION_PI_UNKNOWN:
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case REGION_PI_64DD_ROM:
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case REGION_PI_ROM:
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return 1;
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case REGION_PI_64DD_REG:
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case REGION_PI_SRAM:
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return 2;
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default:
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Util::panic("Unknown PI domain for address {:08X}!", address);
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}
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}
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u32 PI::AccessTiming(u8 domain, u32 length) const {
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uint32_t cycles = 0;
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uint32_t latency = 0;
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uint32_t pulse_width = 0;
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uint32_t release = 0;
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uint32_t page_size = 0;
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uint32_t pages;
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switch (domain) {
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case 1:
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latency = piBsdDom1Lat + 1;
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pulse_width = piBsdDom1Pwd + 1;
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release = piBsdDom1Rls + 1;
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page_size = std::pow(2, (piBsdDom1Pgs + 2));
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break;
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case 2:
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latency = piBsdDom2Lat + 1;
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pulse_width = piBsdDom2Pwd + 1;
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release = piBsdDom2Rls + 1;
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page_size = std::pow(2, (piBsdDom2Pgs + 2));
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break;
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default:
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Util::panic("Unknown PI domain: {}\n", domain);
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}
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pages = ceil((double)length / page_size);
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cycles += (14 + latency) * pages;
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cycles += (pulse_width + release) * (length / 2);
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cycles += 5 * pages;
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return cycles * 1.5; // Converting RCP clock speed to CPU clock speed
|
|
}
|
|
|
|
// rdram -> cart
|
|
template <> void PI::DMA<false>() {
|
|
s32 len = rdLen + 1;
|
|
Util::trace("PI DMA from RDRAM to CARTRIDGE (size: {} B, {:08X} to {:08X})", len, dramAddr, cartAddr);
|
|
|
|
if(mem.saveType == SAVE_FLASH_1m && cartAddr >= SREGION_PI_SRAM && cartAddr < 0x08010000) {
|
|
cartAddr = SREGION_PI_SRAM | ((cartAddr & 0xFFFFF) << 1);
|
|
}
|
|
|
|
for (int i = 0; i < len; i++) {
|
|
BusWrite<u8, true>(cartAddr + i, mem.mmio.rdp.ReadRDRAM<u8>(dramAddr + i));
|
|
}
|
|
dramAddr += len;
|
|
dramAddr = (dramAddr + 7) & ~7;
|
|
cartAddr += len;
|
|
if(cartAddr & 1) cartAddr += 1;
|
|
|
|
dmaBusy = true;
|
|
scheduler.EnqueueRelative(AccessTiming(GetDomain(cartAddr), rdLen), PI_DMA_COMPLETE);
|
|
}
|
|
|
|
// cart -> rdram
|
|
template <> void PI::DMA<true>() {
|
|
s32 len = wrLen + 1;
|
|
Util::trace("PI DMA from CARTRIDGE to RDRAM (size: {} B, {:08X} to {:08X})", len, cartAddr, dramAddr);
|
|
|
|
if(mem.saveType == SAVE_FLASH_1m && cartAddr >= SREGION_PI_SRAM && cartAddr < 0x08010000) {
|
|
cartAddr = SREGION_PI_SRAM | ((cartAddr & 0xFFFFF) << 1);
|
|
}
|
|
|
|
for(u32 i = 0; i < len; i++) {
|
|
mem.mmio.rdp.WriteRDRAM<u8>(dramAddr + i, BusRead<u8, true>(cartAddr + i));
|
|
}
|
|
dramAddr += len;
|
|
dramAddr = (dramAddr + 7) & ~7;
|
|
cartAddr += len;
|
|
if(cartAddr & 1) cartAddr += 1;
|
|
|
|
dmaBusy = true;
|
|
scheduler.EnqueueRelative(AccessTiming(GetDomain(cartAddr), len), PI_DMA_COMPLETE);
|
|
}
|
|
|
|
void PI::Write(u32 addr, u32 val) {
|
|
MI& mi = mem.mmio.mi;
|
|
switch(addr) {
|
|
case 0x04600000: dramAddr = val & 0x00FFFFFE; break;
|
|
case 0x04600004: cartAddr = val & 0xFFFFFFFE; break;
|
|
case 0x04600008: {
|
|
rdLen = val & 0x00FFFFFF;
|
|
DMA<false>();
|
|
} break;
|
|
case 0x0460000C: {
|
|
wrLen = val & 0x00FFFFFF;
|
|
DMA<true>();
|
|
} break;
|
|
case 0x04600010:
|
|
if(val & 2) {
|
|
mi.InterruptLower(MI::Interrupt::PI);
|
|
} break;
|
|
case 0x04600014: piBsdDom1Lat = val & 0xff; break;
|
|
case 0x04600018: piBsdDom1Pwd = val & 0xff; break;
|
|
case 0x0460001C: piBsdDom1Pgs = val & 0xff; break;
|
|
case 0x04600020: piBsdDom1Rls = val & 0xff; break;
|
|
case 0x04600024: piBsdDom2Lat = val & 0xff; break;
|
|
case 0x04600028: piBsdDom2Pwd = val & 0xff; break;
|
|
case 0x0460002C: piBsdDom2Pgs = val & 0xff; break;
|
|
case 0x04600030: piBsdDom2Rls = val & 0xff; break;
|
|
default:
|
|
Util::panic("Unhandled PI[{:08X}] write ({:08X})", val, addr);
|
|
}
|
|
}
|
|
} |