1059 lines
29 KiB
C++
1059 lines
29 KiB
C++
#include <core/registers/Cop1.hpp>
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#include <core/registers/Registers.hpp>
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#include <core/Interpreter.hpp>
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#include <core/JIT.hpp>
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#include <core/Mem.hpp>
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#include <cmath>
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#include <cfenv>
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namespace n64 {
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template<> auto Cop1::FGR<s32>(Cop0Status& status, u32 index) -> s32& {
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if (status.fr) {
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return fgr[index].int32;
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} else {
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if (index & 1) {
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return fgr[index & ~1].int32h;
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} else {
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return fgr[index].int32;
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}
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}
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}
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template<> auto Cop1::FGR<u32>(Cop0Status& status, u32 index) -> u32& {
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return (u32&)FGR<s32>(status, index);
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}
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template<> auto Cop1::FGR<float>(Cop0Status& status, u32 index) -> float& {
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if (status.fr) {
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return fgr[index].float32;
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} else {
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if (index & 1) {
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return fgr[index & ~1].float32h;
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} else {
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return fgr[index].float32;
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}
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}
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}
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template<> auto Cop1::FGR<s64>(Cop0Status& status, u32 index) -> s64& {
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if (status.fr) {
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return fgr[index].int64;
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} else {
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return fgr[index & ~1].int64;
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}
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}
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template<> auto Cop1::FGR<u64>(Cop0Status& status, u32 index) -> u64& {
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return (u64&)FGR<s64>(status, index);
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}
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template<> auto Cop1::FGR<double>(Cop0Status& status, u32 index) -> double& {
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if (status.fr) {
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return fgr[index].float64;
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} else {
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return fgr[index & ~1].float64;
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}
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}
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FORCE_INLINE bool FireFPUException(Registers& regs) {
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FCR31& fcr31 = regs.cop1.fcr31;
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u32 enable = fcr31.enable | (1 << 5);
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if(fcr31.cause & enable) {
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FireException(regs, ExceptionCode::FloatingPointError, 0, regs.oldPC);
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return true;
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}
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return false;
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}
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#define CheckFPUException() do { if(FireFPUException(regs)) { return; } } while(0)
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FORCE_INLINE int PushRoundingMode(const FCR31& fcr31) {
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int og = fegetround();
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switch (fcr31.rounding_mode) {
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case 0: fesetround(FE_TONEAREST); break;
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case 1: fesetround(FE_TOWARDZERO); break;
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case 2: fesetround(FE_UPWARD); break;
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case 3: fesetround(FE_DOWNWARD); break;
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}
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return og;
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}
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void Cop1::SetCauseUnimplemented() {
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fcr31.cause_unimplemented_operation = true;
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}
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void Cop1::SetCauseUnderflow() {
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fcr31.cause_underflow = true;
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if(!fcr31.enable_underflow) {
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fcr31.flag_underflow = true;
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}
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}
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void Cop1::SetCauseInexact() {
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fcr31.cause_inexact_operation = true;
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if(!fcr31.enable_inexact_operation) {
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fcr31.flag_inexact_operation = true;
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}
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}
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void Cop1::SetCauseDivisionByZero() {
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fcr31.cause_division_by_zero = true;
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if(!fcr31.enable_division_by_zero) {
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fcr31.flag_division_by_zero = true;
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}
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}
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void Cop1::SetCauseOverflow() {
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fcr31.cause_overflow = true;
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if(!fcr31.enable_overflow) {
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fcr31.flag_overflow = true;
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}
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}
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void Cop1::SetCauseInvalid() {
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fcr31.cause_invalid_operation = true;
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if(!fcr31.enable_invalid_operation) {
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fcr31.flag_invalid_operation = true;
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}
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}
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#define PUSHROUNDING int orig_round = PushRoundingMode(fcr31)
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#define POPROUNDING fesetround(orig_round)
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#define OP_CheckExcept(op) do { feclearexcept(FE_ALL_EXCEPT); PUSHROUNDING; op; SetFPUCauseRaised(regs, fetestexcept(FE_ALL_EXCEPT)); POPROUNDING; } while(0)
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#define CVT_OP_CheckExcept(op) do { feclearexcept(FE_ALL_EXCEPT); op; SetFPUCauseCVTRaised(regs, fetestexcept(FE_ALL_EXCEPT)); CheckFPUException(); } while(0)
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#define OP(T, op) do { \
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CheckFPUUsable(); \
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auto fs = FGR<T>(regs.cop0.status, FS(instr)); \
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auto ft = FGR<T>(regs.cop0.status, FT(instr)); \
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CheckArg(fs); \
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CheckArg(ft); \
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T result; \
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OP_CheckExcept({result = (op);}); \
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CheckResult(result); \
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FGR<T>(regs.cop0.status, FD(instr)) = result; \
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} while(0)
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template <typename T>
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FORCE_INLINE void SetCauseByArgWCVT(Registers& regs, T f) {
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switch (std::fpclassify(f)) {
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case FP_NAN:
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case FP_INFINITE:
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case FP_SUBNORMAL:
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regs.cop1.SetCauseUnimplemented();
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CheckFPUException();
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break;
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case FP_NORMAL:
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// Check overflow
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if (f >= 2147483648.0f || f < -2147483648.0f) {
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regs.cop1.SetCauseUnimplemented();
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CheckFPUException();
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}
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break;
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case FP_ZERO:
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break; // Fine
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}
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}
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template <typename T>
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FORCE_INLINE void SetCauseByArgLCVT(Registers& regs, T f) {
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switch (std::fpclassify(f)) {
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case FP_NAN:
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case FP_INFINITE:
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case FP_SUBNORMAL:
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regs.cop1.SetCauseUnimplemented();
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CheckFPUException();
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break;
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case FP_NORMAL:
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// Check overflow
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if (f >= 9007199254740992.000000 || f <= -9007199254740992.000000) {
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regs.cop1.SetCauseUnimplemented();
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CheckFPUException();
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}
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break;
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case FP_ZERO:
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break; // Fine
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}
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}
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#define CheckWCVTArg(f) do { SetCauseByArgWCVT(regs, f); CheckFPUException(); } while(0)
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#define CheckLCVTArg(f) do { SetCauseByArgLCVT(regs, f); CheckFPUException(); } while(0)
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FORCE_INLINE void SetFPUCauseRaised(Registers& regs, int raised) {
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if (raised == 0) {
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return;
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}
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if (raised & FE_UNDERFLOW) {
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if (!regs.cop1.fcr31.fs || regs.cop1.fcr31.enable_underflow || regs.cop1.fcr31.enable_inexact_operation) {
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regs.cop1.SetCauseUnimplemented();
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return;
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} else {
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regs.cop1.SetCauseUnderflow();
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}
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}
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if (raised & FE_INEXACT) {
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regs.cop1.SetCauseInexact();
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}
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if (raised & FE_DIVBYZERO) {
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regs.cop1.SetCauseDivisionByZero();
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}
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if (raised & FE_OVERFLOW) {
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regs.cop1.SetCauseOverflow();
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}
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if (raised & FE_INVALID) {
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regs.cop1.SetCauseInvalid();
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}
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}
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FORCE_INLINE void SetFPUCauseCVTRaised(Registers& regs, int raised) {
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if(raised & FE_INVALID) {
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regs.cop1.SetCauseUnimplemented();
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return;
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}
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SetFPUCauseRaised(regs, raised);
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}
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#define F_TO_U32(f) (*((u32*)(&(f))))
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#define D_TO_U64(d) (*((u64*)(&(d))))
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#define U64_TO_D(d) (*((double*)(&(d))))
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#define U32_TO_F(f) (*((float*)(&(f))))
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template <typename T>
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FORCE_INLINE bool isqnan(T f) {
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if constexpr(std::is_same_v<T, float>) {
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u32 v = F_TO_U32(f);
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return (v & 0x7FC00000) == 0x7FC00000;
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} else if constexpr(std::is_same_v<T, double>) {
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u64 v = D_TO_U64(f);
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return (v & 0x7FF8000000000000) == 0x7FF8000000000000;
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} else {
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Util::panic("Invalid float type in isqnan");
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}
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}
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template <typename T>
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FORCE_INLINE void SetCauseByArg(Registers& regs, T f) {
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auto fp_class = std::fpclassify(f);
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switch(fp_class) {
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case FP_NAN:
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if(isqnan(f)) {
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regs.cop1.SetCauseInvalid();
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CheckFPUException();
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} else {
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regs.cop1.SetCauseUnimplemented();
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CheckFPUException();
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}
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break;
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case FP_SUBNORMAL:
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regs.cop1.SetCauseUnimplemented();
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CheckFPUException();
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break;
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case FP_INFINITE:
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case FP_ZERO:
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case FP_NORMAL:
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break; // No-op, these are fine.
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default:
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Util::panic("Unknown floating point classification: {}", fp_class);
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}
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}
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#define CheckArg(f) do { SetCauseByArg(regs, f); CheckFPUException(); } while(0)
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template <typename T>
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FORCE_INLINE void SetCauseOnResult(Registers& regs, T& d) {
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Cop1& cop1 = regs.cop1;
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auto fp_class = std::fpclassify(d);
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T magic, min;
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if constexpr(std::is_same_v<T, float>) {
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u32 c = 0x7FBFFFFF;
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magic = U32_TO_F(c);
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min = FLT_MIN;
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} else if constexpr(std::is_same_v<T, double>) {
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u64 c = 0x7FF7FFFFFFFFFFFF;
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magic = U64_TO_D(c);
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min = DBL_MIN;
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}
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switch (fp_class) {
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case FP_NAN:
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d = magic; // set result to sNAN
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break;
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case FP_SUBNORMAL:
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if (!cop1.fcr31.fs || cop1.fcr31.enable_underflow || cop1.fcr31.enable_inexact_operation) {
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regs.cop1.SetCauseUnimplemented();
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CheckFPUException();
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} else {
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// Since the if statement checks for the corresponding enable bits, it's safe to turn these cause bits on here.
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regs.cop1.SetCauseUnderflow();
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regs.cop1.SetCauseInexact();
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switch (cop1.fcr31.rounding_mode) {
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case 0:
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case 1:
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d = std::copysign(0, d);
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break;
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case 2:
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if (std::signbit(d)) {
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d = -(T)0;
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} else {
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d = min;
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}
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break;
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case 3:
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if (std::signbit(d)) {
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d = -min;
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} else {
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d = 0;
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}
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break;
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}
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}
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break;
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case FP_INFINITE:
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case FP_ZERO:
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case FP_NORMAL:
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break; // No-op, these are fine.
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default:
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Util::panic("Unknown FP classification: {}", fp_class);
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}
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}
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#define CheckResult(f) do { SetCauseOnResult(regs, (f)); CheckFPUException(); } while(0)
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#define any_unordered(fs, ft) (std::isnan(fs) || std::isnan(ft))
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#define CheckRound(a, b) do { if ((a) != (b)) { SetCauseInexact(); } CheckFPUException(); } while(0)
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template <typename T>
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FORCE_INLINE bool is_nan(T f) {
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if constexpr(std::is_same_v<T, float>) {
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u32 v = F_TO_U32(f);
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return ((v & 0x7F800000) == 0x7F800000) && ((v & 0x7FFFFF) != 0);
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} else if constexpr(std::is_same_v<T, double>) {
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u64 v = D_TO_U64(f);
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return ((v & 0x7FF0000000000000) == 0x7FF0000000000000) && ((v & 0xFFFFFFFFFFFFF) != 0);
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} else {
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Util::panic("Invalid float type in is_nan");
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}
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}
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#define checknanregs(fs, ft) do { \
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if(is_nan(fs) || is_nan(ft)) { \
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regs.cop1.SetCauseInvalid(); \
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CheckFPUException(); \
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} \
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} while(0)
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#define checkqnanregs(fs, ft) do { \
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if(isqnan(fs) || isqnan(ft)) { \
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regs.cop1.SetCauseInvalid(); \
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CheckFPUException(); \
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} \
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} while(0)
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void Cop1::absd(Registers& regs, u32 instr) {
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OP(double, std::fabs(fs));
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}
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void Cop1::abss(Registers& regs, u32 instr) {
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OP(float, std::fabs(fs));
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}
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void Cop1::adds(Registers& regs, u32 instr) {
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OP(float, fs + ft);
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}
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void Cop1::addd(Registers& regs, u32 instr) {
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OP(double, fs + ft);
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}
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void Cop1::ceills(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<float>(regs.cop0.status, FS(instr));
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CheckLCVTArg(fs);
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s64 result;
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CVT_OP_CheckExcept({ result = std::ceil(fs); });
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CheckRound(fs, result);
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FGR<s64>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::ceilws(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<float>(regs.cop0.status, FS(instr));
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CheckWCVTArg(fs);
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s32 result;
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CVT_OP_CheckExcept({ result = std::ceil(fs); });
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CheckRound(fs, result);
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FGR<s32>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::ceilld(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<double>(regs.cop0.status, FS(instr));
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CheckLCVTArg(fs);
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s64 result;
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CVT_OP_CheckExcept({ result = std::ceil(fs); });
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CheckRound(fs, result);
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FGR<s64>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::ceilwd(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<double>(regs.cop0.status, FS(instr));
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CheckWCVTArg(fs);
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s32 result;
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CVT_OP_CheckExcept({ result = std::ceil(fs); });
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CheckRound(fs, result);
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FGR<s32>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::cfc1(Registers& regs, u32 instr) const {
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CheckFPUUsable_PreserveCause();
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u8 fd = RD(instr);
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s32 val = 0;
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switch(fd) {
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case 0: val = fcr0; break;
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case 31:
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val = fcr31.read();
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break;
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default: Util::panic("Undefined CFC1 with rd != 0 or 31");
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}
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regs.gpr[RT(instr)] = val;
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}
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void Cop1::ctc1(Registers& regs, u32 instr) {
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CheckFPUUsable_PreserveCause();
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u8 fs = RD(instr);
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u32 val = regs.gpr[RT(instr)];
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switch(fs) {
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case 0: break;
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case 31: {
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u32 prevRound = fcr31.rounding_mode;
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fcr31.write(val);
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if (prevRound != fcr31.rounding_mode) {
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switch (fcr31.rounding_mode) {
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case 0: fesetround(FE_TONEAREST); break;
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case 1: fesetround(FE_TOWARDZERO); break;
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case 2: fesetround(FE_UPWARD); break;
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case 3: fesetround(FE_DOWNWARD); break;
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}
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}
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CheckFPUException();
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} break;
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default: Util::panic("Undefined CTC1 with rd != 0 or 31");
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}
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}
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void Cop1::cvtds(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<float>(regs.cop0.status, FS(instr));
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CheckArg(fs);
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double result;
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OP_CheckExcept({ result = double(fs); });
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CheckResult(result);
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FGR<double>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::cvtsd(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<double>(regs.cop0.status, FS(instr));
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CheckArg(fs);
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float result;
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OP_CheckExcept({ result = float(fs); });
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CheckResult(result);
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FGR<float>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::cvtsw(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<s32>(regs.cop0.status, FS(instr));
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float result;
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OP_CheckExcept({ result = float(fs); });
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CheckResult(result);
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FGR<float>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::cvtsl(Registers& regs, u32 instr) {
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CheckFPUUsable();
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auto fs = FGR<s64>(regs.cop0.status, FS(instr));
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if (fs >= s64(0x0080000000000000) || fs < s64(0xff80000000000000)) {
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SetCauseUnimplemented();
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CheckFPUException();
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}
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float result;
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OP_CheckExcept({ result = float(fs); });
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CheckResult(result);
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FGR<float>(regs.cop0.status, FD(instr)) = result;
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}
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void Cop1::cvtwd(Registers& regs, u32 instr) {
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CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
PUSHROUNDING;
|
|
CVT_OP_CheckExcept({ result = std::rint(fs); });
|
|
POPROUNDING;
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::cvtws(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
PUSHROUNDING;
|
|
CVT_OP_CheckExcept({ result = std::rint(fs); });
|
|
POPROUNDING;
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::cvtls(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
PUSHROUNDING;
|
|
CVT_OP_CheckExcept({ result = std::rint(fs); });
|
|
POPROUNDING;
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::cvtdw(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<s32>(regs.cop0.status, FS(instr));
|
|
double result;
|
|
OP_CheckExcept({ result = double(fs); });
|
|
CheckResult(result);
|
|
FGR<double>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::cvtdl(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<s64>(regs.cop0.status, FS(instr));
|
|
|
|
if (fs >= s64(0x0080000000000000) || fs < s64(0xff80000000000000)) {
|
|
SetCauseUnimplemented();
|
|
CheckFPUException();
|
|
}
|
|
double result;
|
|
OP_CheckExcept({ result = double(fs); });
|
|
CheckResult(result);
|
|
FGR<double>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::cvtld(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
PUSHROUNDING;
|
|
CVT_OP_CheckExcept({ result = std::rint(fs); });
|
|
POPROUNDING;
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cf(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = false;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cun(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = any_unordered(fs, ft);
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::ceq(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = fs == ft;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cueq(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = fs == ft || any_unordered(fs, ft);
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::colt(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = fs < ft;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cult(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = fs < ft || any_unordered(fs, ft);
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cole(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = fs <= ft;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cule(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checkqnanregs(fs, ft);
|
|
fcr31.compare = fs <= ft || any_unordered(fs, ft);
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::csf(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = false;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cngle(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = any_unordered(fs, ft);
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cseq(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = fs == ft;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cngl(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = fs == ft || any_unordered(fs, ft);
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::clt(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = fs < ft;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cnge(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = fs < ft || any_unordered(fs, ft);
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cle(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = fs <= ft;
|
|
}
|
|
|
|
template <typename T>
|
|
void Cop1::cngt(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
T fs = FGR<T>(regs.cop0.status, FS(instr));
|
|
T ft = FGR<T>(regs.cop0.status, FT(instr));
|
|
checknanregs(fs, ft);
|
|
fcr31.compare = fs <= ft || any_unordered(fs, ft);
|
|
}
|
|
|
|
template void Cop1::cf<float>(Registers&, u32 instr);
|
|
template void Cop1::cun<float>(Registers&, u32 instr);
|
|
template void Cop1::ceq<float>(Registers&, u32 instr);
|
|
template void Cop1::cueq<float>(Registers&, u32 instr);
|
|
template void Cop1::colt<float>(Registers&, u32 instr);
|
|
template void Cop1::cult<float>(Registers&, u32 instr);
|
|
template void Cop1::cole<float>(Registers&, u32 instr);
|
|
template void Cop1::cule<float>(Registers&, u32 instr);
|
|
template void Cop1::csf<float>(Registers&, u32 instr);
|
|
template void Cop1::cngle<float>(Registers&, u32 instr);
|
|
template void Cop1::cseq<float>(Registers&, u32 instr);
|
|
template void Cop1::cngl<float>(Registers&, u32 instr);
|
|
template void Cop1::clt<float>(Registers&, u32 instr);
|
|
template void Cop1::cnge<float>(Registers&, u32 instr);
|
|
template void Cop1::cle<float>(Registers&, u32 instr);
|
|
template void Cop1::cngt<float>(Registers&, u32 instr);
|
|
template void Cop1::cf<double>(Registers&, u32 instr);
|
|
template void Cop1::cun<double>(Registers&, u32 instr);
|
|
template void Cop1::ceq<double>(Registers&, u32 instr);
|
|
template void Cop1::cueq<double>(Registers&, u32 instr);
|
|
template void Cop1::colt<double>(Registers&, u32 instr);
|
|
template void Cop1::cult<double>(Registers&, u32 instr);
|
|
template void Cop1::cole<double>(Registers&, u32 instr);
|
|
template void Cop1::cule<double>(Registers&, u32 instr);
|
|
template void Cop1::csf<double>(Registers&, u32 instr);
|
|
template void Cop1::cngle<double>(Registers&, u32 instr);
|
|
template void Cop1::cseq<double>(Registers&, u32 instr);
|
|
template void Cop1::cngl<double>(Registers&, u32 instr);
|
|
template void Cop1::clt<double>(Registers&, u32 instr);
|
|
template void Cop1::cnge<double>(Registers&, u32 instr);
|
|
template void Cop1::cle<double>(Registers&, u32 instr);
|
|
template void Cop1::cngt<double>(Registers&, u32 instr);
|
|
|
|
void Cop1::divs(Registers ®s, u32 instr) {
|
|
OP(float, fs / ft);
|
|
}
|
|
|
|
void Cop1::divd(Registers ®s, u32 instr) {
|
|
OP(double, fs / ft);
|
|
}
|
|
|
|
void Cop1::muls(Registers ®s, u32 instr) {
|
|
OP(float, fs * ft);
|
|
}
|
|
|
|
void Cop1::muld(Registers& regs, u32 instr) {
|
|
OP(double, fs * ft);
|
|
}
|
|
|
|
void Cop1::subs(Registers ®s, u32 instr) {
|
|
OP(float, fs - ft);
|
|
}
|
|
|
|
void Cop1::subd(Registers ®s, u32 instr) {
|
|
OP(double, fs - ft);
|
|
}
|
|
|
|
void Cop1::movs(Registers& regs, u32 instr) {
|
|
CheckFPUUsable_PreserveCause();
|
|
auto val = FGR<u64>(regs.cop0.status, FS(instr));
|
|
FGR<u64>(regs.cop0.status, FD(instr)) = val;
|
|
}
|
|
|
|
void Cop1::movd(Registers& regs, u32 instr) {
|
|
CheckFPUUsable_PreserveCause();
|
|
auto val = FGR<double>(regs.cop0.status, FS(instr));
|
|
FGR<double>(regs.cop0.status, FD(instr)) = val;
|
|
}
|
|
|
|
void Cop1::negs(Registers ®s, u32 instr) {
|
|
OP(float, -fs);
|
|
}
|
|
|
|
void Cop1::negd(Registers ®s, u32 instr) {
|
|
OP(double, -fs);
|
|
}
|
|
|
|
void Cop1::sqrts(Registers ®s, u32 instr) {
|
|
OP(float, std::sqrt(fs));
|
|
}
|
|
|
|
void Cop1::sqrtd(Registers ®s, u32 instr) {
|
|
OP(double, std::sqrt(fs));
|
|
}
|
|
|
|
void Cop1::roundls(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
CVT_OP_CheckExcept({ result = std::nearbyint(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::roundld(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
CVT_OP_CheckExcept({ result = std::nearbyint(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::roundws(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
CVT_OP_CheckExcept({ result = std::nearbyint(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::roundwd(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
CVT_OP_CheckExcept({ result = std::nearbyint(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::floorls(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
CVT_OP_CheckExcept({ result = std::floor(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::floorld(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
CVT_OP_CheckExcept({ result = std::floor(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::floorws(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
CVT_OP_CheckExcept({ result = std::floor(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::floorwd(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
CVT_OP_CheckExcept({ result = std::floor(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::truncws(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
CVT_OP_CheckExcept({ result = std::trunc(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::truncwd(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckWCVTArg(fs);
|
|
s32 result;
|
|
CVT_OP_CheckExcept({ result = std::trunc(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s32>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::truncls(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<float>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
CVT_OP_CheckExcept({ result = std::trunc(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
void Cop1::truncld(Registers& regs, u32 instr) {
|
|
CheckFPUUsable();
|
|
auto fs = FGR<double>(regs.cop0.status, FS(instr));
|
|
CheckLCVTArg(fs);
|
|
s64 result;
|
|
CVT_OP_CheckExcept({ result = std::trunc(fs); });
|
|
CheckRound(fs, result);
|
|
FGR<s64>(regs.cop0.status, FD(instr)) = result;
|
|
}
|
|
|
|
template<class T>
|
|
void Cop1::lwc1(T &cpu, Mem &mem, u32 instr) {
|
|
if constexpr(std::is_same_v<decltype(cpu), Interpreter&>) {
|
|
Registers& regs = cpu.regs;
|
|
CheckFPUUsable_PreserveCause();
|
|
lwc1Interp(cpu.regs, mem, instr);
|
|
} else if constexpr (std::is_same_v<decltype(cpu), JIT&>) {
|
|
lwc1JIT(cpu, mem, instr);
|
|
} else {
|
|
Util::panic("What the fuck did you just give me?!!");
|
|
}
|
|
}
|
|
|
|
template void Cop1::lwc1<Interpreter>(Interpreter&, Mem&, u32);
|
|
template void Cop1::lwc1<JIT>(JIT&, Mem&, u32);
|
|
|
|
template<class T>
|
|
void Cop1::swc1(T &cpu, Mem &mem, u32 instr) {
|
|
if constexpr(std::is_same_v<decltype(cpu), Interpreter&>) {
|
|
Registers& regs = cpu.regs;
|
|
CheckFPUUsable_PreserveCause();
|
|
swc1Interp(cpu.regs, mem, instr);
|
|
} else if constexpr (std::is_same_v<decltype(cpu), JIT&>) {
|
|
swc1JIT(cpu, mem, instr);
|
|
} else {
|
|
Util::panic("What the fuck did you just give me?!!");
|
|
}
|
|
}
|
|
|
|
template void Cop1::swc1<Interpreter>(Interpreter&, Mem&, u32);
|
|
template void Cop1::swc1<JIT>(JIT&, Mem&, u32);
|
|
|
|
template<class T>
|
|
void Cop1::ldc1(T &cpu, Mem &mem, u32 instr) {
|
|
if constexpr(std::is_same_v<decltype(cpu), Interpreter&>) {
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|
Registers& regs = cpu.regs;
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|
CheckFPUUsable_PreserveCause();
|
|
ldc1Interp(cpu.regs, mem, instr);
|
|
} else if constexpr (std::is_same_v<decltype(cpu), JIT&>) {
|
|
ldc1JIT(cpu, mem, instr);
|
|
} else {
|
|
Util::panic("What the fuck did you just give me?!!");
|
|
}
|
|
}
|
|
|
|
template void Cop1::ldc1<Interpreter>(Interpreter&, Mem&, u32);
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template void Cop1::ldc1<JIT>(JIT&, Mem&, u32);
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|
|
|
template<class T>
|
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void Cop1::sdc1(T &cpu, Mem &mem, u32 instr) {
|
|
if constexpr(std::is_same_v<decltype(cpu), Interpreter&>) {
|
|
Registers& regs = cpu.regs;
|
|
CheckFPUUsable_PreserveCause();
|
|
sdc1Interp(cpu.regs, mem, instr);
|
|
} else if constexpr (std::is_same_v<decltype(cpu), JIT&>) {
|
|
sdc1JIT(cpu, mem, instr);
|
|
} else {
|
|
Util::panic("What the fuck did you just give me?!!");
|
|
}
|
|
}
|
|
|
|
template void Cop1::sdc1<Interpreter>(Interpreter&, Mem&, u32);
|
|
template void Cop1::sdc1<JIT>(JIT&, Mem&, u32);
|
|
|
|
void Cop1::lwc1Interp(Registers& regs, Mem& mem, u32 instr) {
|
|
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
|
|
|
|
u32 physical;
|
|
if(!MapVAddr(regs, LOAD, addr, physical)) {
|
|
HandleTLBException(regs, addr);
|
|
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
|
} else {
|
|
u32 data = mem.Read<u32>(regs, physical);
|
|
FGR<u32>(regs.cop0.status, FT(instr)) = data;
|
|
}
|
|
}
|
|
|
|
void Cop1::swc1Interp(Registers& regs, Mem& mem, u32 instr) {
|
|
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
|
|
|
|
u32 physical;
|
|
if(!MapVAddr(regs, STORE, addr, physical)) {
|
|
HandleTLBException(regs, addr);
|
|
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
} else {
|
|
mem.Write<u32>(regs, physical, FGR<u32>(regs.cop0.status, FT(instr)));
|
|
}
|
|
}
|
|
|
|
void Cop1::unimplemented(Registers& regs) {
|
|
CheckFPUUsable();
|
|
fcr31.cause_unimplemented_operation = true;
|
|
FireFPUException(regs);
|
|
}
|
|
|
|
void Cop1::ldc1Interp(Registers& regs, Mem& mem, u32 instr) {
|
|
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
|
|
|
|
u32 physical;
|
|
if(!MapVAddr(regs, LOAD, addr, physical)) {
|
|
HandleTLBException(regs, addr);
|
|
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, LOAD), 0, regs.oldPC);
|
|
} else {
|
|
u64 data = mem.Read<u64>(regs, physical);
|
|
FGR<u64>(regs.cop0.status, FT(instr)) = data;
|
|
}
|
|
}
|
|
|
|
void Cop1::sdc1Interp(Registers& regs, Mem& mem, u32 instr) {
|
|
u64 addr = (s64)(s16)instr + regs.gpr[BASE(instr)];
|
|
|
|
u32 physical;
|
|
if(!MapVAddr(regs, STORE, addr, physical)) {
|
|
HandleTLBException(regs, addr);
|
|
FireException(regs, GetTLBExceptionCode(regs.cop0.tlbError, STORE), 0, regs.oldPC);
|
|
} else {
|
|
mem.Write(regs, physical, FGR<u64>(regs.cop0.status, FT(instr)));
|
|
}
|
|
}
|
|
|
|
void Cop1::mfc1(Registers& regs, u32 instr) {
|
|
CheckFPUUsable_PreserveCause();
|
|
regs.gpr[RT(instr)] = FGR<s32>(regs.cop0.status, FS(instr));
|
|
}
|
|
|
|
void Cop1::dmfc1(Registers& regs, u32 instr) {
|
|
CheckFPUUsable_PreserveCause();
|
|
regs.gpr[RT(instr)] = FGR<s64>(regs.cop0.status, FS(instr));
|
|
}
|
|
|
|
void Cop1::mtc1(Registers& regs, u32 instr) {
|
|
CheckFPUUsable_PreserveCause();
|
|
FGR<u32>(regs.cop0.status, FS(instr)) = regs.gpr[RT(instr)];
|
|
}
|
|
|
|
void Cop1::dmtc1(Registers& regs, u32 instr) {
|
|
CheckFPUUsable_PreserveCause();
|
|
FGR<u64>(regs.cop0.status, FS(instr)) = regs.gpr[RT(instr)];
|
|
}
|
|
|
|
}
|