297 lines
5.8 KiB
C
297 lines
5.8 KiB
C
#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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enum {
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ARC_NoRegister,
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ARC_BLINK = 1,
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ARC_FP = 2,
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ARC_GP = 3,
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ARC_ILINK = 4,
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ARC_SP = 5,
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ARC_R0 = 6,
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ARC_R1 = 7,
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ARC_R2 = 8,
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ARC_R3 = 9,
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ARC_R4 = 10,
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ARC_R5 = 11,
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ARC_R6 = 12,
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ARC_R7 = 13,
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ARC_R8 = 14,
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ARC_R9 = 15,
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ARC_R10 = 16,
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ARC_R11 = 17,
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ARC_R12 = 18,
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ARC_R13 = 19,
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ARC_R14 = 20,
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ARC_R15 = 21,
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ARC_R16 = 22,
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ARC_R17 = 23,
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ARC_R18 = 24,
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ARC_R19 = 25,
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ARC_R20 = 26,
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ARC_R21 = 27,
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ARC_R22 = 28,
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ARC_R23 = 29,
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ARC_R24 = 30,
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ARC_R25 = 31,
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ARC_R30 = 32,
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ARC_R32 = 33,
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ARC_R33 = 34,
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ARC_R34 = 35,
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ARC_R35 = 36,
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ARC_R36 = 37,
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ARC_R37 = 38,
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ARC_R38 = 39,
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ARC_R39 = 40,
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ARC_R40 = 41,
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ARC_R41 = 42,
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ARC_R42 = 43,
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ARC_R43 = 44,
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ARC_R44 = 45,
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ARC_R45 = 46,
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ARC_R46 = 47,
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ARC_R47 = 48,
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ARC_R48 = 49,
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ARC_R49 = 50,
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ARC_R50 = 51,
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ARC_R51 = 52,
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ARC_R52 = 53,
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ARC_R53 = 54,
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ARC_R54 = 55,
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ARC_R55 = 56,
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ARC_R56 = 57,
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ARC_R57 = 58,
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ARC_R58 = 59,
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ARC_R59 = 60,
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ARC_R60 = 61,
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ARC_R61 = 62,
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ARC_R62 = 63,
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ARC_R63 = 64,
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ARC_STATUS32 = 65,
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NUM_TARGET_REGS // 66
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};
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// Register classes
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enum {
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ARC_SREGRegClassID = 0,
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ARC_GPR_SRegClassID = 1,
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ARC_GPR32RegClassID = 2,
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ARC_GPR32_and_GPR_SRegClassID = 3,
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};
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#endif // GET_REGINFO_ENUM
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/* Capstone Disassembly Engine, https://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2024 */
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/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Do not edit. */
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/* Capstone's LLVM TableGen Backends: */
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/* https://github.com/capstone-engine/llvm-capstone */
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#ifdef GET_REGINFO_MC_DESC
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#undef GET_REGINFO_MC_DESC
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static const MCPhysReg ARCRegDiffLists[] = {
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/* 0 */ 0,
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};
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static const uint16_t ARCSubRegIdxLists[] = {
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/* 0 */ 0,
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};
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static const MCRegisterDesc ARCRegDesc[] = { // Descriptors
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{ 3, 0, 0, 0, 0, 0 },
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{ 235, 0, 0, 0, 0, 0 },
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{ 247, 0, 0, 0, 1, 0 },
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{ 250, 0, 0, 0, 2, 0 },
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{ 241, 0, 0, 0, 3, 0 },
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{ 253, 0, 0, 0, 4, 0 },
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{ 24, 0, 0, 0, 5, 0 },
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{ 47, 0, 0, 0, 6, 0 },
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{ 83, 0, 0, 0, 7, 0 },
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{ 110, 0, 0, 0, 8, 0 },
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{ 133, 0, 0, 0, 9, 0 },
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{ 156, 0, 0, 0, 10, 0 },
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{ 175, 0, 0, 0, 11, 0 },
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{ 194, 0, 0, 0, 12, 0 },
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{ 213, 0, 0, 0, 13, 0 },
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{ 232, 0, 0, 0, 14, 0 },
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{ 0, 0, 0, 0, 15, 0 },
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{ 27, 0, 0, 0, 16, 0 },
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{ 50, 0, 0, 0, 17, 0 },
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{ 86, 0, 0, 0, 18, 0 },
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{ 113, 0, 0, 0, 19, 0 },
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{ 136, 0, 0, 0, 20, 0 },
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{ 159, 0, 0, 0, 21, 0 },
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{ 178, 0, 0, 0, 22, 0 },
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{ 197, 0, 0, 0, 23, 0 },
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{ 216, 0, 0, 0, 24, 0 },
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{ 4, 0, 0, 0, 25, 0 },
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{ 31, 0, 0, 0, 26, 0 },
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{ 54, 0, 0, 0, 27, 0 },
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{ 90, 0, 0, 0, 28, 0 },
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{ 117, 0, 0, 0, 29, 0 },
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{ 140, 0, 0, 0, 30, 0 },
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{ 8, 0, 0, 0, 31, 0 },
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{ 58, 0, 0, 0, 32, 0 },
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{ 94, 0, 0, 0, 33, 0 },
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{ 121, 0, 0, 0, 34, 0 },
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{ 144, 0, 0, 0, 35, 0 },
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{ 163, 0, 0, 0, 36, 0 },
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{ 182, 0, 0, 0, 37, 0 },
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{ 201, 0, 0, 0, 38, 0 },
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{ 220, 0, 0, 0, 39, 0 },
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{ 12, 0, 0, 0, 40, 0 },
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{ 35, 0, 0, 0, 41, 0 },
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{ 71, 0, 0, 0, 42, 0 },
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{ 98, 0, 0, 0, 43, 0 },
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{ 125, 0, 0, 0, 44, 0 },
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{ 148, 0, 0, 0, 45, 0 },
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{ 167, 0, 0, 0, 46, 0 },
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{ 186, 0, 0, 0, 47, 0 },
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{ 205, 0, 0, 0, 48, 0 },
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{ 224, 0, 0, 0, 49, 0 },
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{ 16, 0, 0, 0, 50, 0 },
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{ 39, 0, 0, 0, 51, 0 },
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{ 75, 0, 0, 0, 52, 0 },
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{ 102, 0, 0, 0, 53, 0 },
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{ 129, 0, 0, 0, 54, 0 },
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{ 152, 0, 0, 0, 55, 0 },
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{ 171, 0, 0, 0, 56, 0 },
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{ 190, 0, 0, 0, 57, 0 },
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{ 209, 0, 0, 0, 58, 0 },
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{ 228, 0, 0, 0, 59, 0 },
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{ 20, 0, 0, 0, 60, 0 },
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{ 43, 0, 0, 0, 61, 0 },
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{ 79, 0, 0, 0, 62, 0 },
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{ 106, 0, 0, 0, 63, 0 },
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{ 62, 0, 0, 0, 64, 0 },
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};
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// SREG Register Class...
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static const MCPhysReg SREG[] = {
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ARC_STATUS32,
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};
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// SREG Bit set.
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static const uint8_t SREGBits[] = {
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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
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};
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// GPR_S Register Class...
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static const MCPhysReg GPR_S[] = {
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ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
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};
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// GPR_S Bit set.
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static const uint8_t GPR_SBits[] = {
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0xc0, 0x03, 0x3c,
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};
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// GPR32 Register Class...
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static const MCPhysReg GPR32[] = {
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ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R4, ARC_R5, ARC_R6, ARC_R7, ARC_R8, ARC_R9, ARC_R10, ARC_R11, ARC_R12, ARC_R13, ARC_R14, ARC_R15, ARC_R16, ARC_R17, ARC_R18, ARC_R19, ARC_R20, ARC_R21, ARC_R22, ARC_R23, ARC_R24, ARC_R25, ARC_GP, ARC_FP, ARC_SP, ARC_ILINK, ARC_R30, ARC_BLINK, ARC_R32, ARC_R33, ARC_R34, ARC_R35, ARC_R36, ARC_R37, ARC_R38, ARC_R39, ARC_R40, ARC_R41, ARC_R42, ARC_R43, ARC_R44, ARC_R45, ARC_R46, ARC_R47, ARC_R48, ARC_R49, ARC_R50, ARC_R51, ARC_R52, ARC_R53, ARC_R54, ARC_R55, ARC_R56, ARC_R57, ARC_R58, ARC_R59, ARC_R60, ARC_R61, ARC_R62, ARC_R63,
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};
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// GPR32 Bit set.
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static const uint8_t GPR32Bits[] = {
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0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x01,
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};
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// GPR32_and_GPR_S Register Class...
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static const MCPhysReg GPR32_and_GPR_S[] = {
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ARC_R0, ARC_R1, ARC_R2, ARC_R3, ARC_R12, ARC_R13, ARC_R14, ARC_R15,
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};
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// GPR32_and_GPR_S Bit set.
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static const uint8_t GPR32_and_GPR_SBits[] = {
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0xc0, 0x03, 0x3c,
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};
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static const MCRegisterClass ARCMCRegisterClasses[] = {
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{ SREG, SREGBits, sizeof(SREGBits) },
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{ GPR_S, GPR_SBits, sizeof(GPR_SBits) },
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{ GPR32, GPR32Bits, sizeof(GPR32Bits) },
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{ GPR32_and_GPR_S, GPR32_and_GPR_SBits, sizeof(GPR32_and_GPR_SBits) },
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};
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static const uint16_t ARCRegEncodingTable[] = {
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0,
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31,
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27,
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26,
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29,
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28,
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0,
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1,
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2,
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3,
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4,
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5,
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6,
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7,
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8,
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9,
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10,
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11,
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12,
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13,
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14,
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15,
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16,
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17,
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18,
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19,
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20,
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21,
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22,
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23,
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24,
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25,
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30,
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32,
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33,
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34,
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35,
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36,
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37,
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38,
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39,
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40,
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41,
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42,
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43,
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44,
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45,
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46,
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47,
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48,
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49,
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50,
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51,
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52,
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53,
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54,
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55,
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56,
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57,
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58,
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59,
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60,
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61,
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62,
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63,
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10,
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};
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#endif // GET_REGINFO_MC_DESC
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