2989 lines
123 KiB
C
2989 lines
123 KiB
C
#ifdef GET_REGINFO_ENUM
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#undef GET_REGINFO_ENUM
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enum {
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ARM_NoRegister,
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ARM_APSR = 1,
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ARM_APSR_NZCV = 2,
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ARM_CPSR = 3,
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ARM_FPCXTNS = 4,
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ARM_FPCXTS = 5,
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ARM_FPEXC = 6,
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ARM_FPINST = 7,
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ARM_FPSCR = 8,
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ARM_FPSCR_NZCV = 9,
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ARM_FPSCR_NZCVQC = 10,
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ARM_FPSID = 11,
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ARM_ITSTATE = 12,
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ARM_LR = 13,
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ARM_PC = 14,
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ARM_RA_AUTH_CODE = 15,
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ARM_SP = 16,
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ARM_SPSR = 17,
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ARM_VPR = 18,
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ARM_ZR = 19,
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ARM_D0 = 20,
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ARM_D1 = 21,
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ARM_D2 = 22,
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ARM_D3 = 23,
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ARM_D4 = 24,
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ARM_D5 = 25,
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ARM_D6 = 26,
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ARM_D7 = 27,
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ARM_D8 = 28,
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ARM_D9 = 29,
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ARM_D10 = 30,
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ARM_D11 = 31,
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ARM_D12 = 32,
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ARM_D13 = 33,
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ARM_D14 = 34,
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ARM_D15 = 35,
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ARM_D16 = 36,
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ARM_D17 = 37,
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ARM_D18 = 38,
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ARM_D19 = 39,
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ARM_D20 = 40,
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ARM_D21 = 41,
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ARM_D22 = 42,
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ARM_D23 = 43,
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ARM_D24 = 44,
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ARM_D25 = 45,
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ARM_D26 = 46,
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ARM_D27 = 47,
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ARM_D28 = 48,
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ARM_D29 = 49,
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ARM_D30 = 50,
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ARM_D31 = 51,
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ARM_FPINST2 = 52,
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ARM_MVFR0 = 53,
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ARM_MVFR1 = 54,
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ARM_MVFR2 = 55,
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ARM_P0 = 56,
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ARM_Q0 = 57,
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ARM_Q1 = 58,
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ARM_Q2 = 59,
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ARM_Q3 = 60,
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ARM_Q4 = 61,
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ARM_Q5 = 62,
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ARM_Q6 = 63,
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ARM_Q7 = 64,
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ARM_Q8 = 65,
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ARM_Q9 = 66,
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ARM_Q10 = 67,
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ARM_Q11 = 68,
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ARM_Q12 = 69,
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ARM_Q13 = 70,
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ARM_Q14 = 71,
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ARM_Q15 = 72,
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ARM_R0 = 73,
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ARM_R1 = 74,
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ARM_R2 = 75,
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ARM_R3 = 76,
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ARM_R4 = 77,
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ARM_R5 = 78,
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ARM_R6 = 79,
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ARM_R7 = 80,
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ARM_R8 = 81,
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ARM_R9 = 82,
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ARM_R10 = 83,
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ARM_R11 = 84,
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ARM_R12 = 85,
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ARM_S0 = 86,
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ARM_S1 = 87,
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ARM_S2 = 88,
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ARM_S3 = 89,
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ARM_S4 = 90,
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ARM_S5 = 91,
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ARM_S6 = 92,
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ARM_S7 = 93,
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ARM_S8 = 94,
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ARM_S9 = 95,
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ARM_S10 = 96,
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ARM_S11 = 97,
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ARM_S12 = 98,
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ARM_S13 = 99,
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ARM_S14 = 100,
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ARM_S15 = 101,
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ARM_S16 = 102,
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ARM_S17 = 103,
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ARM_S18 = 104,
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ARM_S19 = 105,
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ARM_S20 = 106,
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ARM_S21 = 107,
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ARM_S22 = 108,
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ARM_S23 = 109,
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ARM_S24 = 110,
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ARM_S25 = 111,
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ARM_S26 = 112,
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ARM_S27 = 113,
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ARM_S28 = 114,
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ARM_S29 = 115,
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ARM_S30 = 116,
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ARM_S31 = 117,
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ARM_D0_D2 = 118,
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ARM_D1_D3 = 119,
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ARM_D2_D4 = 120,
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ARM_D3_D5 = 121,
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ARM_D4_D6 = 122,
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ARM_D5_D7 = 123,
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ARM_D6_D8 = 124,
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ARM_D7_D9 = 125,
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ARM_D8_D10 = 126,
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ARM_D9_D11 = 127,
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ARM_D10_D12 = 128,
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ARM_D11_D13 = 129,
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ARM_D12_D14 = 130,
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ARM_D13_D15 = 131,
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ARM_D14_D16 = 132,
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ARM_D15_D17 = 133,
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ARM_D16_D18 = 134,
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ARM_D17_D19 = 135,
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ARM_D18_D20 = 136,
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ARM_D19_D21 = 137,
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ARM_D20_D22 = 138,
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ARM_D21_D23 = 139,
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ARM_D22_D24 = 140,
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ARM_D23_D25 = 141,
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ARM_D24_D26 = 142,
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ARM_D25_D27 = 143,
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ARM_D26_D28 = 144,
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ARM_D27_D29 = 145,
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ARM_D28_D30 = 146,
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ARM_D29_D31 = 147,
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ARM_Q0_Q1 = 148,
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ARM_Q1_Q2 = 149,
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ARM_Q2_Q3 = 150,
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ARM_Q3_Q4 = 151,
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ARM_Q4_Q5 = 152,
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ARM_Q5_Q6 = 153,
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ARM_Q6_Q7 = 154,
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ARM_Q7_Q8 = 155,
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ARM_Q8_Q9 = 156,
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ARM_Q9_Q10 = 157,
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ARM_Q10_Q11 = 158,
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ARM_Q11_Q12 = 159,
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ARM_Q12_Q13 = 160,
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ARM_Q13_Q14 = 161,
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ARM_Q14_Q15 = 162,
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ARM_Q0_Q1_Q2_Q3 = 163,
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ARM_Q1_Q2_Q3_Q4 = 164,
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ARM_Q2_Q3_Q4_Q5 = 165,
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ARM_Q3_Q4_Q5_Q6 = 166,
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ARM_Q4_Q5_Q6_Q7 = 167,
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ARM_Q5_Q6_Q7_Q8 = 168,
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ARM_Q6_Q7_Q8_Q9 = 169,
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ARM_Q7_Q8_Q9_Q10 = 170,
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ARM_Q8_Q9_Q10_Q11 = 171,
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ARM_Q9_Q10_Q11_Q12 = 172,
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ARM_Q10_Q11_Q12_Q13 = 173,
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ARM_Q11_Q12_Q13_Q14 = 174,
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ARM_Q12_Q13_Q14_Q15 = 175,
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ARM_R0_R1 = 176,
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ARM_R2_R3 = 177,
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ARM_R4_R5 = 178,
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ARM_R6_R7 = 179,
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ARM_R8_R9 = 180,
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ARM_R10_R11 = 181,
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ARM_R12_SP = 182,
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ARM_D0_D1_D2 = 183,
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ARM_D1_D2_D3 = 184,
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ARM_D2_D3_D4 = 185,
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ARM_D3_D4_D5 = 186,
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ARM_D4_D5_D6 = 187,
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ARM_D5_D6_D7 = 188,
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ARM_D6_D7_D8 = 189,
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ARM_D7_D8_D9 = 190,
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ARM_D8_D9_D10 = 191,
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ARM_D9_D10_D11 = 192,
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ARM_D10_D11_D12 = 193,
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ARM_D11_D12_D13 = 194,
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ARM_D12_D13_D14 = 195,
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ARM_D13_D14_D15 = 196,
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ARM_D14_D15_D16 = 197,
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ARM_D15_D16_D17 = 198,
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ARM_D16_D17_D18 = 199,
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ARM_D17_D18_D19 = 200,
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ARM_D18_D19_D20 = 201,
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ARM_D19_D20_D21 = 202,
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ARM_D20_D21_D22 = 203,
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ARM_D21_D22_D23 = 204,
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ARM_D22_D23_D24 = 205,
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ARM_D23_D24_D25 = 206,
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ARM_D24_D25_D26 = 207,
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ARM_D25_D26_D27 = 208,
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ARM_D26_D27_D28 = 209,
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ARM_D27_D28_D29 = 210,
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ARM_D28_D29_D30 = 211,
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ARM_D29_D30_D31 = 212,
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ARM_D0_D2_D4 = 213,
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ARM_D1_D3_D5 = 214,
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ARM_D2_D4_D6 = 215,
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ARM_D3_D5_D7 = 216,
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ARM_D4_D6_D8 = 217,
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ARM_D5_D7_D9 = 218,
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ARM_D6_D8_D10 = 219,
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ARM_D7_D9_D11 = 220,
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ARM_D8_D10_D12 = 221,
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ARM_D9_D11_D13 = 222,
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ARM_D10_D12_D14 = 223,
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ARM_D11_D13_D15 = 224,
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ARM_D12_D14_D16 = 225,
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ARM_D13_D15_D17 = 226,
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ARM_D14_D16_D18 = 227,
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ARM_D15_D17_D19 = 228,
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ARM_D16_D18_D20 = 229,
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ARM_D17_D19_D21 = 230,
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ARM_D18_D20_D22 = 231,
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ARM_D19_D21_D23 = 232,
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ARM_D20_D22_D24 = 233,
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ARM_D21_D23_D25 = 234,
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ARM_D22_D24_D26 = 235,
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ARM_D23_D25_D27 = 236,
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ARM_D24_D26_D28 = 237,
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ARM_D25_D27_D29 = 238,
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ARM_D26_D28_D30 = 239,
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ARM_D27_D29_D31 = 240,
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ARM_D0_D2_D4_D6 = 241,
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ARM_D1_D3_D5_D7 = 242,
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ARM_D2_D4_D6_D8 = 243,
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ARM_D3_D5_D7_D9 = 244,
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ARM_D4_D6_D8_D10 = 245,
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ARM_D5_D7_D9_D11 = 246,
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ARM_D6_D8_D10_D12 = 247,
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ARM_D7_D9_D11_D13 = 248,
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ARM_D8_D10_D12_D14 = 249,
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ARM_D9_D11_D13_D15 = 250,
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ARM_D10_D12_D14_D16 = 251,
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ARM_D11_D13_D15_D17 = 252,
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ARM_D12_D14_D16_D18 = 253,
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ARM_D13_D15_D17_D19 = 254,
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ARM_D14_D16_D18_D20 = 255,
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ARM_D15_D17_D19_D21 = 256,
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ARM_D16_D18_D20_D22 = 257,
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ARM_D17_D19_D21_D23 = 258,
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ARM_D18_D20_D22_D24 = 259,
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ARM_D19_D21_D23_D25 = 260,
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ARM_D20_D22_D24_D26 = 261,
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ARM_D21_D23_D25_D27 = 262,
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ARM_D22_D24_D26_D28 = 263,
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ARM_D23_D25_D27_D29 = 264,
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ARM_D24_D26_D28_D30 = 265,
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ARM_D25_D27_D29_D31 = 266,
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ARM_D1_D2 = 267,
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ARM_D3_D4 = 268,
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ARM_D5_D6 = 269,
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ARM_D7_D8 = 270,
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ARM_D9_D10 = 271,
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ARM_D11_D12 = 272,
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ARM_D13_D14 = 273,
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ARM_D15_D16 = 274,
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ARM_D17_D18 = 275,
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ARM_D19_D20 = 276,
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ARM_D21_D22 = 277,
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ARM_D23_D24 = 278,
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ARM_D25_D26 = 279,
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ARM_D27_D28 = 280,
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ARM_D29_D30 = 281,
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ARM_D1_D2_D3_D4 = 282,
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ARM_D3_D4_D5_D6 = 283,
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ARM_D5_D6_D7_D8 = 284,
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ARM_D7_D8_D9_D10 = 285,
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ARM_D9_D10_D11_D12 = 286,
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ARM_D11_D12_D13_D14 = 287,
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ARM_D13_D14_D15_D16 = 288,
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ARM_D15_D16_D17_D18 = 289,
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ARM_D17_D18_D19_D20 = 290,
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ARM_D19_D20_D21_D22 = 291,
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ARM_D21_D22_D23_D24 = 292,
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ARM_D23_D24_D25_D26 = 293,
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ARM_D25_D26_D27_D28 = 294,
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ARM_D27_D28_D29_D30 = 295,
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NUM_TARGET_REGS // 296
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};
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// Register classes
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enum {
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ARM_HPRRegClassID = 0,
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ARM_FPWithVPRRegClassID = 1,
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ARM_SPRRegClassID = 2,
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ARM_FPWithVPR_with_ssub_0RegClassID = 3,
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ARM_GPRRegClassID = 4,
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ARM_GPRwithAPSRRegClassID = 5,
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ARM_GPRwithZRRegClassID = 6,
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ARM_SPR_8RegClassID = 7,
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ARM_GPRnopcRegClassID = 8,
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ARM_GPRnospRegClassID = 9,
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ARM_GPRwithAPSR_NZCVnospRegClassID = 10,
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ARM_GPRwithAPSRnospRegClassID = 11,
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ARM_GPRwithZRnospRegClassID = 12,
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ARM_GPRnoipRegClassID = 13,
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ARM_rGPRRegClassID = 14,
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ARM_GPRnoip_and_GPRnopcRegClassID = 15,
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ARM_GPRnoip_and_GPRnospRegClassID = 16,
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ARM_GPRnoip_and_GPRwithAPSR_NZCVnospRegClassID = 17,
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ARM_tGPRwithpcRegClassID = 18,
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ARM_FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClassID = 19,
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ARM_hGPRRegClassID = 20,
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ARM_tGPRRegClassID = 21,
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ARM_tGPREvenRegClassID = 22,
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ARM_GPRnopc_and_hGPRRegClassID = 23,
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ARM_GPRnosp_and_hGPRRegClassID = 24,
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ARM_GPRnoip_and_hGPRRegClassID = 25,
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ARM_GPRnoip_and_tGPREvenRegClassID = 26,
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ARM_GPRnosp_and_GPRnopc_and_hGPRRegClassID = 27,
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ARM_tGPROddRegClassID = 28,
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ARM_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 29,
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ARM_GPRnosp_and_GPRnoip_and_hGPRRegClassID = 30,
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ARM_tcGPRRegClassID = 31,
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ARM_GPRnoip_and_tcGPRRegClassID = 32,
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ARM_GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRRegClassID = 33,
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ARM_hGPR_and_tGPREvenRegClassID = 34,
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ARM_tGPR_and_tGPREvenRegClassID = 35,
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ARM_tGPR_and_tGPROddRegClassID = 36,
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ARM_tGPREven_and_tcGPRRegClassID = 37,
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ARM_hGPR_and_GPRnoip_and_tGPREvenRegClassID = 38,
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ARM_hGPR_and_tGPROddRegClassID = 39,
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ARM_tGPREven_and_GPRnoip_and_tcGPRRegClassID = 40,
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ARM_tGPROdd_and_tcGPRRegClassID = 41,
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ARM_CCRRegClassID = 42,
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ARM_FPCXTRegsRegClassID = 43,
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ARM_GPRlrRegClassID = 44,
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ARM_GPRspRegClassID = 45,
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ARM_VCCRRegClassID = 46,
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ARM_cl_FPSCR_NZCVRegClassID = 47,
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ARM_hGPR_and_tGPRwithpcRegClassID = 48,
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ARM_hGPR_and_tcGPRRegClassID = 49,
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ARM_DPRRegClassID = 50,
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ARM_DPR_VFP2RegClassID = 51,
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ARM_DPR_8RegClassID = 52,
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ARM_GPRPairRegClassID = 53,
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ARM_GPRPairnospRegClassID = 54,
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ARM_GPRPair_with_gsub_0_in_tGPRRegClassID = 55,
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ARM_GPRPair_with_gsub_0_in_hGPRRegClassID = 56,
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ARM_GPRPair_with_gsub_0_in_tcGPRRegClassID = 57,
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ARM_GPRPair_with_gsub_1_in_tcGPRRegClassID = 58,
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ARM_GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClassID = 59,
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ARM_GPRPair_with_gsub_1_in_GPRspRegClassID = 60,
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ARM_DPairSpcRegClassID = 61,
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ARM_DPairSpc_with_ssub_0RegClassID = 62,
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ARM_DPairSpc_with_ssub_4RegClassID = 63,
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ARM_DPairSpc_with_dsub_0_in_DPR_8RegClassID = 64,
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ARM_DPairSpc_with_dsub_2_in_DPR_8RegClassID = 65,
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ARM_DPairRegClassID = 66,
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ARM_DPair_with_ssub_0RegClassID = 67,
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ARM_QPRRegClassID = 68,
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ARM_DPair_with_ssub_2RegClassID = 69,
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ARM_DPair_with_dsub_0_in_DPR_8RegClassID = 70,
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ARM_MQPRRegClassID = 71,
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ARM_QPR_VFP2RegClassID = 72,
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ARM_DPair_with_dsub_1_in_DPR_8RegClassID = 73,
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ARM_QPR_8RegClassID = 74,
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ARM_DTripleRegClassID = 75,
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ARM_DTripleSpcRegClassID = 76,
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ARM_DTripleSpc_with_ssub_0RegClassID = 77,
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ARM_DTriple_with_ssub_0RegClassID = 78,
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ARM_DTriple_with_qsub_0_in_QPRRegClassID = 79,
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ARM_DTriple_with_ssub_2RegClassID = 80,
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ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 81,
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ARM_DTripleSpc_with_ssub_4RegClassID = 82,
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ARM_DTriple_with_ssub_4RegClassID = 83,
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ARM_DTripleSpc_with_ssub_8RegClassID = 84,
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ARM_DTripleSpc_with_dsub_0_in_DPR_8RegClassID = 85,
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ARM_DTriple_with_dsub_0_in_DPR_8RegClassID = 86,
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ARM_DTriple_with_qsub_0_in_MQPRRegClassID = 87,
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ARM_DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 88,
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ARM_DTriple_with_dsub_1_in_DPR_8RegClassID = 89,
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ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 90,
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ARM_DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClassID = 91,
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ARM_DTripleSpc_with_dsub_2_in_DPR_8RegClassID = 92,
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ARM_DTriple_with_dsub_2_in_DPR_8RegClassID = 93,
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ARM_DTripleSpc_with_dsub_4_in_DPR_8RegClassID = 94,
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ARM_DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 95,
|
|
ARM_DTriple_with_qsub_0_in_QPR_8RegClassID = 96,
|
|
ARM_DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClassID = 97,
|
|
ARM_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 98,
|
|
ARM_DQuadSpcRegClassID = 99,
|
|
ARM_DQuadSpc_with_ssub_0RegClassID = 100,
|
|
ARM_DQuadSpc_with_ssub_4RegClassID = 101,
|
|
ARM_DQuadSpc_with_ssub_8RegClassID = 102,
|
|
ARM_DQuadSpc_with_dsub_0_in_DPR_8RegClassID = 103,
|
|
ARM_DQuadSpc_with_dsub_2_in_DPR_8RegClassID = 104,
|
|
ARM_DQuadSpc_with_dsub_4_in_DPR_8RegClassID = 105,
|
|
ARM_DQuadRegClassID = 106,
|
|
ARM_DQuad_with_ssub_0RegClassID = 107,
|
|
ARM_DQuad_with_ssub_2RegClassID = 108,
|
|
ARM_QQPRRegClassID = 109,
|
|
ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 110,
|
|
ARM_DQuad_with_ssub_4RegClassID = 111,
|
|
ARM_DQuad_with_ssub_6RegClassID = 112,
|
|
ARM_DQuad_with_dsub_0_in_DPR_8RegClassID = 113,
|
|
ARM_DQuad_with_qsub_0_in_MQPRRegClassID = 114,
|
|
ARM_DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClassID = 115,
|
|
ARM_DQuad_with_dsub_1_in_DPR_8RegClassID = 116,
|
|
ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 117,
|
|
ARM_MQQPRRegClassID = 118,
|
|
ARM_DQuad_with_dsub_2_in_DPR_8RegClassID = 119,
|
|
ARM_DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 120,
|
|
ARM_DQuad_with_dsub_3_in_DPR_8RegClassID = 121,
|
|
ARM_DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 122,
|
|
ARM_DQuad_with_qsub_0_in_QPR_8RegClassID = 123,
|
|
ARM_DQuad_with_qsub_1_in_QPR_8RegClassID = 124,
|
|
ARM_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClassID = 125,
|
|
ARM_DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClassID = 126,
|
|
ARM_QQQQPRRegClassID = 127,
|
|
ARM_QQQQPR_with_ssub_0RegClassID = 128,
|
|
ARM_QQQQPR_with_ssub_4RegClassID = 129,
|
|
ARM_QQQQPR_with_ssub_8RegClassID = 130,
|
|
ARM_MQQQQPRRegClassID = 131,
|
|
ARM_MQQQQPR_with_dsub_0_in_DPR_8RegClassID = 132,
|
|
ARM_MQQQQPR_with_dsub_2_in_DPR_8RegClassID = 133,
|
|
ARM_MQQQQPR_with_dsub_4_in_DPR_8RegClassID = 134,
|
|
ARM_MQQQQPR_with_dsub_6_in_DPR_8RegClassID = 135,
|
|
|
|
};
|
|
|
|
// Register alternate name indices
|
|
|
|
enum {
|
|
ARM_NoRegAltName, // 0
|
|
ARM_RegNamesRaw, // 1
|
|
NUM_TARGET_REG_ALT_NAMES = 2
|
|
};
|
|
|
|
// Subregister indices
|
|
|
|
enum {
|
|
ARM_NoSubRegister,
|
|
ARM_dsub_0, // 1
|
|
ARM_dsub_1, // 2
|
|
ARM_dsub_2, // 3
|
|
ARM_dsub_3, // 4
|
|
ARM_dsub_4, // 5
|
|
ARM_dsub_5, // 6
|
|
ARM_dsub_6, // 7
|
|
ARM_dsub_7, // 8
|
|
ARM_gsub_0, // 9
|
|
ARM_gsub_1, // 10
|
|
ARM_qqsub_0, // 11
|
|
ARM_qqsub_1, // 12
|
|
ARM_qsub_0, // 13
|
|
ARM_qsub_1, // 14
|
|
ARM_qsub_2, // 15
|
|
ARM_qsub_3, // 16
|
|
ARM_ssub_0, // 17
|
|
ARM_ssub_1, // 18
|
|
ARM_ssub_2, // 19
|
|
ARM_ssub_3, // 20
|
|
ARM_ssub_4, // 21
|
|
ARM_ssub_5, // 22
|
|
ARM_ssub_6, // 23
|
|
ARM_ssub_7, // 24
|
|
ARM_ssub_8, // 25
|
|
ARM_ssub_9, // 26
|
|
ARM_ssub_10, // 27
|
|
ARM_ssub_11, // 28
|
|
ARM_ssub_12, // 29
|
|
ARM_ssub_13, // 30
|
|
ARM_ssub_14, // 31
|
|
ARM_ssub_15, // 32
|
|
ARM_ssub_0_ssub_1_ssub_4_ssub_5, // 33
|
|
ARM_ssub_0_ssub_1_ssub_2_ssub_3_ssub_4_ssub_5, // 34
|
|
ARM_ssub_2_ssub_3_ssub_6_ssub_7, // 35
|
|
ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7, // 36
|
|
ARM_ssub_2_ssub_3_ssub_4_ssub_5, // 37
|
|
ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9, // 38
|
|
ARM_ssub_0_ssub_1_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 39
|
|
ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5, // 40
|
|
ARM_ssub_2_ssub_3_ssub_6_ssub_7_dsub_5_dsub_7, // 41
|
|
ARM_ssub_2_ssub_3_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 42
|
|
ARM_ssub_4_ssub_5_ssub_8_ssub_9, // 43
|
|
ARM_ssub_4_ssub_5_ssub_6_ssub_7_ssub_8_ssub_9, // 44
|
|
ARM_ssub_4_ssub_5_ssub_8_ssub_9_ssub_12_ssub_13, // 45
|
|
ARM_ssub_6_ssub_7_dsub_5, // 46
|
|
ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5, // 47
|
|
ARM_ssub_6_ssub_7_dsub_5_dsub_7, // 48
|
|
ARM_ssub_6_ssub_7_ssub_8_ssub_9, // 49
|
|
ARM_ssub_6_ssub_7_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 50
|
|
ARM_ssub_8_ssub_9_ssub_12_ssub_13, // 51
|
|
ARM_ssub_8_ssub_9_dsub_5_ssub_12_ssub_13, // 52
|
|
ARM_dsub_5_dsub_7, // 53
|
|
ARM_dsub_5_ssub_12_ssub_13_dsub_7, // 54
|
|
ARM_dsub_5_ssub_12_ssub_13, // 55
|
|
ARM_ssub_4_ssub_5_ssub_6_ssub_7_qsub_2, // 56
|
|
ARM_NUM_TARGET_SUBREGS
|
|
};
|
|
#endif // GET_REGINFO_ENUM
|
|
|
|
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
|
|
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
|
|
/* Rot127 <unisono@quyllur.org> 2022-2024 */
|
|
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
|
|
|
|
/* LLVM-commit: <commit> */
|
|
/* LLVM-tag: <tag> */
|
|
|
|
/* Do not edit. */
|
|
|
|
/* Capstone's LLVM TableGen Backends: */
|
|
/* https://github.com/capstone-engine/llvm-capstone */
|
|
|
|
#ifdef GET_REGINFO_MC_DESC
|
|
#undef GET_REGINFO_MC_DESC
|
|
|
|
static const MCPhysReg ARMRegDiffLists[] = {
|
|
/* 0 */ -248, 1, 1, 1, 230, 1, -136, 65, -64, 65, -140, 0,
|
|
/* 12 */ -249, 1, 1, 1, 231, 1, -137, 65, -64, 65, -139, 0,
|
|
/* 24 */ -250, 1, 1, 1, 232, 1, -138, 65, -64, 65, -138, 0,
|
|
/* 36 */ -251, 1, 1, 1, 233, 1, -139, 65, -64, 65, -137, 0,
|
|
/* 48 */ -252, 1, 1, 1, 234, 1, -140, 65, -64, 65, -136, 0,
|
|
/* 60 */ -253, 1, 1, 1, 235, 1, -141, 65, -64, 65, -135, 0,
|
|
/* 72 */ -15, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -117, -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, -44, 28, -27, 28, 28, -150, 65, 30, -94, 65, 30, 40, 15, -134, 0,
|
|
/* 111 */ -15, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -117, -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, -45, 28, -27, 28, 29, -151, 65, 30, -94, 65, 30, 41, 15, -134, 0,
|
|
/* 150 */ -15, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -117, -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, -46, 28, -27, 28, 30, -152, 65, 30, -94, 65, 30, 42, 15, -134, 0,
|
|
/* 189 */ -15, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -117, -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, -47, 28, -27, 28, 31, -153, 65, 30, -94, 65, 30, 43, 15, -134, 0,
|
|
/* 228 */ -15, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -117, -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, -48, 28, -27, 28, 32, -154, 65, 30, -94, 65, 30, 44, 15, -134, 0,
|
|
/* 267 */ -15, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -117, -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, -49, 28, -27, 28, 33, -155, 65, 30, -94, 65, 30, 45, 15, -134, 0,
|
|
/* 310 */ -15, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -117, -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, -50, 28, -27, 28, 34, -156, 65, 30, -94, 65, 30, 46, 15, -134, 0,
|
|
/* 357 */ -15, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -117, -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, -51, 28, -27, 28, 35, -157, 65, 30, -94, 65, 30, 47, 15, -134, 0,
|
|
/* 408 */ -15, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -117, -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, -52, 28, -27, 28, 36, -158, 65, 30, -94, 65, 30, 48, 15, -134, 0,
|
|
/* 463 */ -15, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -117, -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, -53, 28, -27, 28, 37, -159, 65, 30, -94, 65, 30, 49, 15, -134, 0,
|
|
/* 518 */ -15, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -117, -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, -54, 28, -27, 28, 38, -160, 65, 30, -94, 65, 30, 50, 15, -134, 0,
|
|
/* 573 */ -15, -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, -117, -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, -55, 28, -27, 28, 39, -161, 65, 30, -94, 65, 30, 51, 15, -134, 0,
|
|
/* 628 */ -15, -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, -117, -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, -56, 28, -27, 28, 40, -162, 65, 30, -94, 65, 30, 52, 15, -134, 0,
|
|
/* 683 */ -254, 81, 1, -81, 1, 1, 236, 1, -142, 65, -64, 65, -134, 0,
|
|
/* 697 */ -255, 79, 1, -79, 80, 1, -80, 81, 1, -81, 237, 1, -143, 65, -64, 65, -133, 0,
|
|
/* 715 */ -256, 77, 1, -77, 78, 1, -78, 79, 1, -79, 80, 1, 157, 1, -144, 65, -64, 65, -132, 0,
|
|
/* 735 */ -257, 75, 1, -75, 76, 1, -76, 77, 1, -77, 78, 1, 160, 1, -145, 65, -64, 65, -131, 0,
|
|
/* 755 */ -258, 73, 1, -73, 74, 1, -74, 75, 1, -75, 76, 1, 163, 1, -146, 65, -64, 65, -130, 0,
|
|
/* 775 */ -259, 71, 1, -71, 72, 1, -72, 73, 1, -73, 74, 1, 166, 1, -147, 65, -64, 65, -129, 0,
|
|
/* 795 */ -260, 69, 1, -69, 70, 1, -70, 71, 1, -71, 72, 1, 169, 1, -148, 65, -64, 65, -128, 0,
|
|
/* 815 */ -261, 67, 1, -67, 68, 1, -68, 69, 1, -69, 70, 1, 172, 1, -149, 65, -64, 65, -127, 0,
|
|
/* 835 */ 23, 73, 2, 63, -48, 120, -71, 1, -49, 75, 26, -89, 65, 26, 30, -120, 66, 26, 29, -120, 0,
|
|
/* 856 */ 22, 74, 2, 63, -49, 120, -70, 1, -50, 76, 26, -90, 66, 26, 29, -120, 0,
|
|
/* 873 */ 65, -49, 77, 26, -90, 66, 26, 29, -120, 0,
|
|
/* 883 */ 23, 73, 2, 134, -71, 1, -49, 50, -49, 75, 26, 31, -120, 65, 26, 30, -120, 0,
|
|
/* 901 */ 22, 74, 135, -70, 1, -50, 77, 26, 30, -120, 0,
|
|
/* 912 */ 65, -49, 77, 26, 30, -120, 0,
|
|
/* 919 */ -71, 1, -49, 133, -120, 121, -120, 0,
|
|
/* 927 */ 139, -49, 50, -49, 12, 121, -120, 0,
|
|
/* 935 */ -49, 13, 121, -120, 0,
|
|
/* 940 */ -70, 1, -50, 133, -120, 0,
|
|
/* 946 */ -49, 133, -120, 0,
|
|
/* 950 */ -68, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
|
|
/* 962 */ -67, 36, 62, 148, -84, 1, -36, 66, 28, 40, -119, 0,
|
|
/* 974 */ 65, -36, 66, 28, 40, -119, 0,
|
|
/* 981 */ -84, 1, -36, 134, -119, 0,
|
|
/* 987 */ -221, 75, 1, -74, 77, 1, -76, 79, 1, -78, 81, 1, 10, 95, -93, 95, -93, 0,
|
|
/* 1005 */ -221, 74, 1, -73, 76, 1, -75, 78, 1, -77, 80, 1, 11, 95, -93, 95, -93, 0,
|
|
/* 1023 */ -221, 73, 1, -72, 75, 1, -74, 77, 1, -76, 79, 1, 12, 95, -93, 95, -93, 0,
|
|
/* 1041 */ -221, 72, 1, -71, 74, 1, -73, 76, 1, -75, 78, 1, 13, 95, -93, 95, -93, 0,
|
|
/* 1059 */ -221, 71, 1, -70, 73, 1, -72, 75, 1, -74, 77, 1, 14, 95, -93, 95, -93, 0,
|
|
/* 1077 */ -221, 70, 1, -69, 72, 1, -71, 74, 1, -73, 76, 1, 15, 95, -93, 95, -93, 0,
|
|
/* 1095 */ -221, 69, 1, -68, 71, 1, -70, 73, 1, -72, 75, 1, 16, 95, -93, 95, -93, 0,
|
|
/* 1113 */ -221, 68, 1, -67, 70, 1, -69, 72, 1, -71, 74, 1, 17, 95, -93, 95, -93, 0,
|
|
/* 1131 */ -221, 67, 1, -66, 69, 1, -68, 71, 1, -70, 73, 1, 18, 95, -93, 95, -93, 0,
|
|
/* 1149 */ -221, 66, 1, -65, 68, 1, -67, 70, 1, -69, 72, 1, 19, 95, -93, 95, -93, 0,
|
|
/* 1167 */ -221, 77, 1, -76, 79, 1, -78, 81, 1, -80, 92, 95, -93, 95, -93, 0,
|
|
/* 1183 */ -221, 76, 1, -75, 78, 1, -77, 80, 1, -79, 92, 95, -93, 95, -93, 0,
|
|
/* 1199 */ -221, 79, 1, -78, 81, 1, -80, 2, 92, 95, -93, 95, -93, 0,
|
|
/* 1213 */ -221, 78, 1, -77, 80, 1, -79, 2, 92, 95, -93, 95, -93, 0,
|
|
/* 1227 */ -221, 81, 1, -80, 2, 2, 92, 95, -93, 95, -93, 0,
|
|
/* 1239 */ -221, 80, 1, -79, 2, 2, 92, 95, -93, 95, -93, 0,
|
|
/* 1251 */ -221, 2, 2, 2, 92, 95, -93, 95, -93, 0,
|
|
/* 1261 */ 21, 75, 65, -50, 78, 26, -91, 0,
|
|
/* 1269 */ 24, 72, 2, 63, -47, 120, -72, 1, -48, 74, 26, -88, 64, 26, 31, -120, 65, 26, 30, -120, 92, -91, 0,
|
|
/* 1292 */ 65, -48, 76, 26, -89, 65, 26, 30, -120, 92, -91, 0,
|
|
/* 1304 */ 26, -90, 92, -91, 0,
|
|
/* 1309 */ 24, 72, 2, 135, -72, 1, -48, 49, -48, 74, 26, 32, -120, 64, 26, 31, -120, 65, 26, -90, 0,
|
|
/* 1330 */ 65, -48, 76, 26, 31, -120, 65, 26, -90, 0,
|
|
/* 1340 */ 25, 71, 2, 63, -46, 120, -73, 1, -47, 73, 26, -87, 63, 26, 32, -120, 64, 26, 31, -120, 91, -90, 0,
|
|
/* 1363 */ 65, -47, 75, 26, -88, 64, 26, 31, -120, 91, -90, 0,
|
|
/* 1375 */ 25, 71, 2, 136, -73, 1, -47, 48, -47, 73, 26, 33, -120, 63, 26, 32, -120, 64, 26, -89, 91, -90, 0,
|
|
/* 1398 */ 65, -47, 75, 26, 32, -120, 64, 26, -89, 91, -90, 0,
|
|
/* 1410 */ 26, 70, 2, 63, -45, 120, -74, 1, -46, 72, 26, -86, 62, 26, 33, -120, 63, 26, 32, -120, 90, -89, 0,
|
|
/* 1433 */ 65, -46, 74, 26, -87, 63, 26, 32, -120, 90, -89, 0,
|
|
/* 1445 */ 26, 70, 2, 137, -74, 1, -46, 47, -46, 72, 26, 34, -120, 62, 26, 33, -120, 63, 26, -88, 90, -89, 0,
|
|
/* 1468 */ 65, -46, 74, 26, 33, -120, 63, 26, -88, 90, -89, 0,
|
|
/* 1480 */ 27, 69, 2, 63, -44, 120, -75, 1, -45, 71, 26, -85, 61, 26, 34, -120, 62, 26, 33, -120, 89, -88, 0,
|
|
/* 1503 */ 65, -45, 73, 26, -86, 62, 26, 33, -120, 89, -88, 0,
|
|
/* 1515 */ 27, 69, 2, 138, -75, 1, -45, 46, -45, 71, 26, 35, -120, 61, 26, 34, -120, 62, 26, -87, 89, -88, 0,
|
|
/* 1538 */ 65, -45, 73, 26, 34, -120, 62, 26, -87, 89, -88, 0,
|
|
/* 1550 */ 28, 68, 2, 63, -43, 120, -76, 1, -44, 70, 26, -84, 60, 26, 35, -120, 61, 26, 34, -120, 88, -87, 0,
|
|
/* 1573 */ 65, -44, 72, 26, -85, 61, 26, 34, -120, 88, -87, 0,
|
|
/* 1585 */ 28, 68, 2, 139, -76, 1, -44, 45, -44, 70, 26, 36, -120, 60, 26, 35, -120, 61, 26, -86, 88, -87, 0,
|
|
/* 1608 */ 65, -44, 72, 26, 35, -120, 61, 26, -86, 88, -87, 0,
|
|
/* 1620 */ -82, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
|
|
/* 1644 */ -81, 29, 67, 2, 63, -42, 120, -77, 1, -43, 69, 26, -83, 59, 26, 36, -120, 60, 26, 35, -120, 87, -86, 0,
|
|
/* 1668 */ 65, -43, 71, 26, -84, 60, 26, 35, -120, 87, -86, 0,
|
|
/* 1680 */ 29, 67, 2, 140, -77, 1, -43, 44, -43, 69, 26, 37, -120, 59, 26, 36, -120, 60, 26, -85, 87, -86, 0,
|
|
/* 1703 */ 65, -43, 71, 26, 36, -120, 60, 26, -85, 87, -86, 0,
|
|
/* 1715 */ -80, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
|
|
/* 1739 */ -79, 30, 66, 2, 63, -41, 120, -78, 1, -42, 68, 26, -82, 58, 26, 37, -120, 59, 26, 36, -120, 86, -85, 0,
|
|
/* 1763 */ 65, -42, 70, 26, -83, 59, 26, 36, -120, 86, -85, 0,
|
|
/* 1775 */ -81, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
|
|
/* 1799 */ -80, 30, 66, 2, 141, -78, 1, -42, 43, -42, 68, 26, 38, -120, 58, 26, 37, -120, 59, 26, -84, 86, -85, 0,
|
|
/* 1823 */ 65, -42, 70, 26, 37, -120, 59, 26, -84, 86, -85, 0,
|
|
/* 1835 */ -78, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
|
|
/* 1859 */ -77, 31, 65, 2, 63, -40, 120, -79, 1, -41, 67, 26, -81, 57, 26, 38, -120, 58, 26, 37, -120, 85, -84, 0,
|
|
/* 1883 */ 65, -41, 69, 26, -82, 58, 26, 37, -120, 85, -84, 0,
|
|
/* 1895 */ -79, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
|
|
/* 1919 */ -78, 31, 65, 2, 142, -79, 1, -41, 42, -41, 67, 26, 39, -120, 57, 26, 38, -120, 58, 26, -83, 85, -84, 0,
|
|
/* 1943 */ 65, -41, 69, 26, 38, -120, 58, 26, -83, 85, -84, 0,
|
|
/* 1955 */ -76, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
|
|
/* 1979 */ -75, 32, 64, 2, 63, -39, 120, -80, 1, -40, 66, 26, -80, 56, 26, 39, -120, 57, 26, 38, -120, 84, -83, 0,
|
|
/* 2003 */ 65, -40, 68, 26, -81, 57, 26, 38, -120, 84, -83, 0,
|
|
/* 2015 */ -77, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
|
|
/* 2039 */ -76, 32, 64, 2, 143, -80, 1, -40, 41, -40, 66, 26, 40, -120, 56, 26, 39, -120, 57, 26, -82, 84, -83, 0,
|
|
/* 2063 */ 65, -40, 68, 26, 39, -120, 57, 26, -82, 84, -83, 0,
|
|
/* 2075 */ -74, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
|
|
/* 2099 */ -73, 33, 63, 2, 63, -38, 120, -81, 1, -39, 65, 26, -79, 55, 26, 40, -120, 56, 26, 39, -120, 83, -82, 0,
|
|
/* 2123 */ 65, -39, 67, 26, -80, 56, 26, 39, -120, 83, -82, 0,
|
|
/* 2135 */ -75, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
|
|
/* 2159 */ -74, 33, 63, 2, 144, -81, 1, -39, 40, -39, 65, 26, 41, -120, 55, 26, 40, -120, 56, 26, -81, 83, -82, 0,
|
|
/* 2183 */ 65, -39, 67, 26, 40, -120, 56, 26, -81, 83, -82, 0,
|
|
/* 2195 */ -239, 81, 1, -81, 0,
|
|
/* 2200 */ -72, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
|
|
/* 2222 */ -71, 34, 62, 2, 63, -37, 120, -82, 1, -38, 64, 2, 26, 41, -120, 55, 26, 40, -120, 82, -81, 0,
|
|
/* 2244 */ 65, -38, 66, 26, -79, 55, 26, 40, -120, 82, -81, 0,
|
|
/* 2256 */ -73, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
|
|
/* 2280 */ -72, 34, 62, 2, 145, -82, 1, -38, 39, -38, 64, 26, 42, -120, 54, 26, 41, -120, 55, 26, -80, 82, -81, 0,
|
|
/* 2304 */ 65, -38, 66, 26, 41, -120, 55, 26, -80, 82, -81, 0,
|
|
/* 2316 */ -98, 81, 1, -80, 0,
|
|
/* 2321 */ -70, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
|
|
/* 2340 */ -69, 35, 61, 2, 63, -36, 120, -83, 1, -37, 65, 2, 26, 40, 1, -120, 81, -80, 0,
|
|
/* 2359 */ 65, -37, 65, 2, 26, 41, -120, 81, -80, 0,
|
|
/* 2369 */ -71, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
|
|
/* 2391 */ -70, 35, 61, 2, 146, -83, 1, -37, 38, -37, 63, 2, 26, 41, 1, -120, 54, 26, -79, 81, -80, 0,
|
|
/* 2413 */ 65, -37, 65, 26, 42, -120, 54, 26, -79, 81, -80, 0,
|
|
/* 2425 */ -98, 80, 1, -79, 0,
|
|
/* 2430 */ 28, -79, 0,
|
|
/* 2433 */ -69, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
|
|
/* 2451 */ -68, 36, 60, 2, 147, -84, 1, -36, 37, -36, 64, 2, 26, 41, -119, 80, -79, 0,
|
|
/* 2469 */ 65, -36, 64, 2, 26, 41, -119, 80, -79, 0,
|
|
/* 2479 */ 26, -78, 80, -79, 0,
|
|
/* 2484 */ -67, 37, 61, 65, -35, 65, 28, -78, 0,
|
|
/* 2493 */ -66, 37, 61, 65, -35, 65, 28, -78, 0,
|
|
/* 2502 */ -163, 1, 1, 230, -134, -75, 0,
|
|
/* 2509 */ -163, 1, 1, 231, -135, -74, 0,
|
|
/* 2516 */ -163, 1, 1, 232, -136, -73, 0,
|
|
/* 2523 */ -163, 1, 1, 233, -137, -72, 0,
|
|
/* 2530 */ -163, 1, 1, 234, -138, -71, 0,
|
|
/* 2537 */ -163, 1, 1, 235, -139, -70, 0,
|
|
/* 2544 */ -163, 1, 1, 236, -140, -69, 0,
|
|
/* 2551 */ -97, -69, 0,
|
|
/* 2554 */ -163, 81, 1, -81, 1, 237, -141, -68, 0,
|
|
/* 2563 */ -163, 79, 1, -79, 80, 1, -80, 81, 1, 156, -142, -67, 0,
|
|
/* 2576 */ -163, 77, 1, -77, 78, 1, -78, 79, 1, 159, -143, -66, 0,
|
|
/* 2589 */ -163, 75, 1, -75, 76, 1, -76, 77, 1, 162, -144, -65, 0,
|
|
/* 2602 */ -163, 73, 1, -73, 74, 1, -74, 75, 1, 165, -145, -64, 0,
|
|
/* 2615 */ -163, 71, 1, -71, 72, 1, -72, 73, 1, 168, -146, -63, 0,
|
|
/* 2628 */ -163, 69, 1, -69, 70, 1, -70, 71, 1, 171, -147, -62, 0,
|
|
/* 2641 */ -163, 67, 1, -67, 68, 1, -68, 69, 1, 174, -148, -61, 0,
|
|
/* 2654 */ -238, 1, 0,
|
|
/* 2657 */ -237, 1, 0,
|
|
/* 2660 */ -236, 1, 0,
|
|
/* 2663 */ -235, 1, 0,
|
|
/* 2666 */ -234, 1, 0,
|
|
/* 2669 */ -233, 1, 0,
|
|
/* 2672 */ -232, 1, 0,
|
|
/* 2675 */ -83, 1, -37, 133, 1, -120, 1, 0,
|
|
/* 2683 */ -72, 1, -48, 133, -120, 121, -120, 1, 0,
|
|
/* 2692 */ -73, 1, -47, 133, -120, 121, -120, 1, 0,
|
|
/* 2701 */ -74, 1, -46, 133, -120, 121, -120, 1, 0,
|
|
/* 2710 */ -75, 1, -45, 133, -120, 121, -120, 1, 0,
|
|
/* 2719 */ -76, 1, -44, 133, -120, 121, -120, 1, 0,
|
|
/* 2728 */ -77, 1, -43, 133, -120, 121, -120, 1, 0,
|
|
/* 2737 */ -78, 1, -42, 133, -120, 121, -120, 1, 0,
|
|
/* 2746 */ -79, 1, -41, 133, -120, 121, -120, 1, 0,
|
|
/* 2755 */ -80, 1, -40, 133, -120, 121, -120, 1, 0,
|
|
/* 2764 */ -81, 1, -39, 133, -120, 121, -120, 1, 0,
|
|
/* 2773 */ -82, 1, -38, 133, -120, 121, -120, 1, 0,
|
|
/* 2782 */ 138, -48, 49, -48, 12, 121, -120, 1, 0,
|
|
/* 2791 */ -48, 13, 121, -120, 1, 0,
|
|
/* 2797 */ -47, 13, 121, -120, 1, 0,
|
|
/* 2803 */ -46, 13, 121, -120, 1, 0,
|
|
/* 2809 */ -45, 13, 121, -120, 1, 0,
|
|
/* 2815 */ -44, 13, 121, -120, 1, 0,
|
|
/* 2821 */ -43, 13, 121, -120, 1, 0,
|
|
/* 2827 */ -42, 13, 121, -120, 1, 0,
|
|
/* 2833 */ -41, 13, 121, -120, 1, 0,
|
|
/* 2839 */ -40, 13, 121, -120, 1, 0,
|
|
/* 2845 */ -39, 13, 121, -120, 1, 0,
|
|
/* 2851 */ -38, 13, 121, -120, 1, 0,
|
|
/* 2857 */ -48, 133, -120, 1, 0,
|
|
/* 2862 */ -37, 134, -120, 1, 0,
|
|
/* 2867 */ 126, -36, 37, -36, 133, -119, 1, 0,
|
|
/* 2875 */ -103, 1, 0,
|
|
/* 2878 */ -102, 1, 0,
|
|
/* 2881 */ -101, 1, 0,
|
|
/* 2884 */ -100, 1, 0,
|
|
/* 2887 */ -99, 1, 0,
|
|
/* 2890 */ -98, 1, 0,
|
|
/* 2893 */ -29, 1, 0,
|
|
/* 2896 */ -28, 1, 0,
|
|
/* 2899 */ -27, 1, 0,
|
|
/* 2902 */ -26, 1, 0,
|
|
/* 2905 */ -25, 1, 0,
|
|
/* 2908 */ -24, 1, 0,
|
|
/* 2911 */ -23, 1, 0,
|
|
/* 2914 */ -22, 1, 0,
|
|
/* 2917 */ 137, -47, 48, -47, 12, 121, -120, 1, 1, 0,
|
|
/* 2927 */ 136, -46, 47, -46, 12, 121, -120, 1, 1, 0,
|
|
/* 2937 */ 135, -45, 46, -45, 12, 121, -120, 1, 1, 0,
|
|
/* 2947 */ 134, -44, 45, -44, 12, 121, -120, 1, 1, 0,
|
|
/* 2957 */ 133, -43, 44, -43, 12, 121, -120, 1, 1, 0,
|
|
/* 2967 */ 132, -42, 43, -42, 12, 121, -120, 1, 1, 0,
|
|
/* 2977 */ 131, -41, 42, -41, 12, 121, -120, 1, 1, 0,
|
|
/* 2987 */ 130, -40, 41, -40, 12, 121, -120, 1, 1, 0,
|
|
/* 2997 */ 129, -39, 40, -39, 12, 121, -120, 1, 1, 0,
|
|
/* 3007 */ 128, -38, 39, -38, 12, 121, -120, 1, 1, 0,
|
|
/* 3017 */ -47, 133, -120, 1, 1, 0,
|
|
/* 3023 */ -46, 133, -120, 1, 1, 0,
|
|
/* 3029 */ -45, 133, -120, 1, 1, 0,
|
|
/* 3035 */ -44, 133, -120, 1, 1, 0,
|
|
/* 3041 */ -43, 133, -120, 1, 1, 0,
|
|
/* 3047 */ -42, 133, -120, 1, 1, 0,
|
|
/* 3053 */ -41, 133, -120, 1, 1, 0,
|
|
/* 3059 */ -40, 133, -120, 1, 1, 0,
|
|
/* 3065 */ -39, 133, -120, 1, 1, 0,
|
|
/* 3071 */ -38, 133, -120, 1, 1, 0,
|
|
/* 3077 */ 127, -37, 38, -37, 133, -120, 1, 1, 0,
|
|
/* 3086 */ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0,
|
|
/* 3102 */ 13, 1, 1, 0,
|
|
/* 3106 */ 1, 3, 1, 3, 1, 3, 1, 0,
|
|
/* 3114 */ 13, 1, 0,
|
|
/* 3117 */ 14, 1, 0,
|
|
/* 3120 */ 66, 1, 0,
|
|
/* 3123 */ -37, 66, 1, -66, 67, 1, 0,
|
|
/* 3130 */ -246, 67, 1, -67, 68, 1, 0,
|
|
/* 3137 */ -98, 66, 1, -65, 68, 1, 0,
|
|
/* 3144 */ -36, 68, 1, -68, 69, 1, 0,
|
|
/* 3151 */ -98, 67, 1, -66, 69, 1, 0,
|
|
/* 3158 */ -245, 69, 1, -69, 70, 1, 0,
|
|
/* 3165 */ -98, 68, 1, -67, 70, 1, 0,
|
|
/* 3172 */ -35, 70, 1, -70, 71, 1, 0,
|
|
/* 3179 */ -98, 69, 1, -68, 71, 1, 0,
|
|
/* 3186 */ -244, 71, 1, -71, 72, 1, 0,
|
|
/* 3193 */ -98, 70, 1, -69, 72, 1, 0,
|
|
/* 3200 */ -34, 72, 1, -72, 73, 1, 0,
|
|
/* 3207 */ -98, 71, 1, -70, 73, 1, 0,
|
|
/* 3214 */ -243, 73, 1, -73, 74, 1, 0,
|
|
/* 3221 */ -98, 72, 1, -71, 74, 1, 0,
|
|
/* 3228 */ -33, 74, 1, -74, 75, 1, 0,
|
|
/* 3235 */ -98, 73, 1, -72, 75, 1, 0,
|
|
/* 3242 */ -242, 75, 1, -75, 76, 1, 0,
|
|
/* 3249 */ -98, 74, 1, -73, 76, 1, 0,
|
|
/* 3256 */ -32, 76, 1, -76, 77, 1, 0,
|
|
/* 3263 */ -98, 75, 1, -74, 77, 1, 0,
|
|
/* 3270 */ -241, 77, 1, -77, 78, 1, 0,
|
|
/* 3277 */ -98, 76, 1, -75, 78, 1, 0,
|
|
/* 3284 */ -31, 78, 1, -78, 79, 1, 0,
|
|
/* 3291 */ -98, 77, 1, -76, 79, 1, 0,
|
|
/* 3298 */ -240, 79, 1, -79, 80, 1, 0,
|
|
/* 3305 */ -98, 78, 1, -77, 80, 1, 0,
|
|
/* 3312 */ -30, 80, 1, -80, 81, 1, 0,
|
|
/* 3319 */ -98, 79, 1, -78, 81, 1, 0,
|
|
/* 3326 */ -98, 2, 0,
|
|
/* 3329 */ 1, 3, 1, 3, 1, 2, 0,
|
|
/* 3336 */ 1, 3, 1, 2, 2, 0,
|
|
/* 3342 */ 1, 2, 2, 2, 0,
|
|
/* 3347 */ 1, 3, 2, 2, 0,
|
|
/* 3352 */ 1, 3, 1, 3, 2, 0,
|
|
/* 3358 */ -193, 77, 1, -76, 79, 1, -78, 81, 1, 12, 2, 0,
|
|
/* 3370 */ -193, 76, 1, -75, 78, 1, -77, 80, 1, 13, 2, 0,
|
|
/* 3382 */ -193, 75, 1, -74, 77, 1, -76, 79, 1, 14, 2, 0,
|
|
/* 3394 */ -193, 74, 1, -73, 76, 1, -75, 78, 1, 15, 2, 0,
|
|
/* 3406 */ -193, 73, 1, -72, 75, 1, -74, 77, 1, 16, 2, 0,
|
|
/* 3418 */ -193, 72, 1, -71, 74, 1, -73, 76, 1, 17, 2, 0,
|
|
/* 3430 */ -193, 71, 1, -70, 73, 1, -72, 75, 1, 18, 2, 0,
|
|
/* 3442 */ -193, 70, 1, -69, 72, 1, -71, 74, 1, 19, 2, 0,
|
|
/* 3454 */ -193, 69, 1, -68, 71, 1, -70, 73, 1, 20, 2, 0,
|
|
/* 3466 */ -193, 68, 1, -67, 70, 1, -69, 72, 1, 21, 2, 0,
|
|
/* 3478 */ -193, 67, 1, -66, 69, 1, -68, 71, 1, 22, 2, 0,
|
|
/* 3490 */ -193, 66, 1, -65, 68, 1, -67, 70, 1, 23, 2, 0,
|
|
/* 3502 */ -193, 79, 1, -78, 81, 1, -80, 94, 2, 0,
|
|
/* 3512 */ -193, 78, 1, -77, 80, 1, -79, 94, 2, 0,
|
|
/* 3522 */ -193, 81, 1, -80, 2, 94, 2, 0,
|
|
/* 3530 */ -193, 80, 1, -79, 2, 94, 2, 0,
|
|
/* 3538 */ -193, 2, 2, 94, 2, 0,
|
|
/* 3544 */ 1, 3, 1, 3, 1, 3, 0,
|
|
/* 3551 */ 140, -50, 13, 0,
|
|
/* 3555 */ 126, -35, 15, 0,
|
|
/* 3559 */ -91, -23, 1, 23, -22, 1, 95, 65, -64, 65, 69, 0,
|
|
/* 3571 */ -91, -24, 1, 24, -23, 1, 95, 65, -64, 65, 70, 0,
|
|
/* 3583 */ -91, -25, 1, 25, -24, 1, 95, 65, -64, 65, 71, 0,
|
|
/* 3595 */ -91, -26, 1, 26, -25, 1, 95, 65, -64, 65, 72, 0,
|
|
/* 3607 */ -91, -27, 1, 27, -26, 1, 95, 65, -64, 65, 73, 0,
|
|
/* 3619 */ -91, -28, 1, 28, -27, 1, 95, 65, -64, 65, 74, 0,
|
|
/* 3631 */ -91, -29, 1, 29, -28, 1, 95, 65, -64, 65, 75, 0,
|
|
/* 3643 */ -91, -30, 80, 1, -80, 81, 1, -52, -29, 1, 95, 65, -64, 65, 76, 0,
|
|
/* 3659 */ -91, -31, 78, 1, -78, 79, 1, -49, -30, 80, 1, -80, 81, 1, 13, 65, -64, 65, 77, 0,
|
|
/* 3679 */ -91, -32, 76, 1, -76, 77, 1, -46, -31, 78, 1, -78, 79, 1, 15, 65, -64, 65, 78, 0,
|
|
/* 3699 */ -91, -33, 74, 1, -74, 75, 1, -43, -32, 76, 1, -76, 77, 1, 17, 65, -64, 65, 79, 0,
|
|
/* 3719 */ -91, -34, 72, 1, -72, 73, 1, -40, -33, 74, 1, -74, 75, 1, 19, 65, -64, 65, 80, 0,
|
|
/* 3739 */ -91, -35, 70, 1, -70, 71, 1, -37, -34, 72, 1, -72, 73, 1, 21, 65, -64, 65, 81, 0,
|
|
/* 3759 */ -91, -36, 68, 1, -68, 69, 1, -34, -35, 70, 1, -70, 71, 1, 23, 65, -64, 65, 82, 0,
|
|
/* 3779 */ -91, -37, 66, 1, -66, 67, 1, -31, -36, 68, 1, -68, 69, 1, 25, 65, -64, 65, 83, 0,
|
|
/* 3799 */ 97, 0,
|
|
/* 3801 */ 98, 0,
|
|
/* 3803 */ 99, 0,
|
|
/* 3805 */ 100, 0,
|
|
/* 3807 */ 101, 0,
|
|
/* 3809 */ 102, 0,
|
|
/* 3811 */ 103, 0,
|
|
/* 3813 */ -163, 1, 1, 21, 75, 135, 0,
|
|
/* 3820 */ -163, 1, 1, 22, 74, 136, 0,
|
|
/* 3827 */ -163, 1, 1, 23, 73, 137, 0,
|
|
/* 3834 */ -163, 1, 1, 24, 72, 138, 0,
|
|
/* 3841 */ -163, 1, 1, 25, 71, 139, 0,
|
|
/* 3848 */ -163, 1, 1, 26, 70, 140, 0,
|
|
/* 3855 */ -163, 1, 1, 27, 69, 141, 0,
|
|
/* 3862 */ -163, 80, 1, -80, 81, 1, -81, 28, 68, 142, 0,
|
|
/* 3873 */ -163, 78, 1, -78, 79, 1, -79, 80, 1, -52, 67, 143, 0,
|
|
/* 3886 */ -163, 76, 1, -76, 77, 1, -77, 78, 1, -49, 66, 144, 0,
|
|
/* 3899 */ -163, 74, 1, -74, 75, 1, -75, 76, 1, -46, 65, 145, 0,
|
|
/* 3912 */ -163, 72, 1, -72, 73, 1, -73, 74, 1, -43, 64, 146, 0,
|
|
/* 3925 */ -163, 70, 1, -70, 71, 1, -71, 72, 1, -40, 63, 147, 0,
|
|
/* 3938 */ -163, 68, 1, -68, 69, 1, -69, 70, 1, -37, 62, 148, 0,
|
|
/* 3951 */ -163, 66, 1, -66, 67, 1, -67, 68, 1, -34, 61, 149, 0,
|
|
/* 3964 */ 166, 0,
|
|
};
|
|
|
|
static const uint16_t ARMSubRegIdxLists[] = {
|
|
/* 0 */ 1, 2, 0,
|
|
/* 3 */ 1, 17, 18, 2, 0,
|
|
/* 8 */ 1, 3, 0,
|
|
/* 11 */ 1, 17, 18, 3, 0,
|
|
/* 16 */ 9, 10, 0,
|
|
/* 19 */ 17, 18, 0,
|
|
/* 22 */ 1, 17, 18, 2, 19, 20, 0,
|
|
/* 29 */ 1, 17, 18, 3, 21, 22, 0,
|
|
/* 36 */ 1, 2, 3, 13, 33, 37, 0,
|
|
/* 43 */ 1, 17, 18, 2, 3, 13, 33, 37, 0,
|
|
/* 52 */ 1, 17, 18, 2, 19, 20, 3, 13, 33, 37, 0,
|
|
/* 63 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 13, 33, 37, 0,
|
|
/* 76 */ 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 0,
|
|
/* 88 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 0,
|
|
/* 104 */ 1, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
|
|
/* 116 */ 1, 17, 18, 2, 3, 4, 13, 14, 33, 34, 35, 36, 37, 0,
|
|
/* 130 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 13, 14, 33, 34, 35, 36, 37, 0,
|
|
/* 148 */ 1, 17, 18, 2, 19, 20, 3, 21, 22, 4, 23, 24, 13, 14, 33, 34, 35, 36, 37, 0,
|
|
/* 168 */ 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 0,
|
|
/* 188 */ 1, 3, 5, 33, 43, 0,
|
|
/* 194 */ 1, 17, 18, 3, 5, 33, 43, 0,
|
|
/* 202 */ 1, 17, 18, 3, 21, 22, 5, 33, 43, 0,
|
|
/* 212 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 33, 43, 0,
|
|
/* 224 */ 1, 3, 5, 7, 33, 38, 43, 45, 51, 0,
|
|
/* 234 */ 1, 17, 18, 3, 5, 7, 33, 38, 43, 45, 51, 0,
|
|
/* 246 */ 1, 17, 18, 3, 21, 22, 5, 7, 33, 38, 43, 45, 51, 0,
|
|
/* 260 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 33, 38, 43, 45, 51, 0,
|
|
/* 276 */ 1, 17, 18, 3, 21, 22, 5, 25, 26, 7, 29, 30, 33, 38, 43, 45, 51, 0,
|
|
/* 294 */ 11, 13, 1, 2, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
|
|
/* 333 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 4, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
|
|
/* 376 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 6, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
|
|
/* 423 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 8, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
|
|
/* 474 */ 11, 13, 1, 17, 18, 2, 19, 20, 14, 3, 21, 22, 4, 23, 24, 33, 34, 35, 36, 37, 12, 15, 5, 25, 26, 6, 27, 28, 16, 7, 29, 30, 8, 31, 32, 51, 52, 53, 54, 55, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 56, 0,
|
|
};
|
|
|
|
static const MCRegisterDesc ARMRegDesc[] = { // Descriptors
|
|
{ 12, 0, 0, 0, 0, 0 },
|
|
{ 1268, 11, 11, 2, 45056, 212 },
|
|
{ 1319, 11, 11, 2, 45057, 212 },
|
|
{ 1273, 11, 11, 2, 45058, 212 },
|
|
{ 1286, 11, 11, 2, 45059, 212 },
|
|
{ 1294, 11, 11, 2, 45060, 212 },
|
|
{ 1215, 11, 11, 2, 45061, 212 },
|
|
{ 1301, 11, 11, 2, 45062, 212 },
|
|
{ 1255, 11, 11, 2, 45063, 212 },
|
|
{ 1308, 11, 11, 2, 45063, 212 },
|
|
{ 1202, 11, 11, 2, 45064, 212 },
|
|
{ 1221, 11, 11, 2, 45065, 212 },
|
|
{ 1240, 11, 11, 2, 45066, 212 },
|
|
{ 1261, 11, 11, 2, 45067, 212 },
|
|
{ 1199, 11, 11, 2, 45068, 212 },
|
|
{ 1227, 11, 11, 2, 45069, 212 },
|
|
{ 1252, 11, 3964, 2, 45070, 212 },
|
|
{ 1278, 11, 11, 2, 45071, 212 },
|
|
{ 1264, 11, 11, 2, 45072, 212 },
|
|
{ 1283, 11, 11, 2, 45073, 212 },
|
|
{ 119, 3120, 2485, 19, 10874898, 6 },
|
|
{ 251, 3127, 951, 19, 10874900, 6 },
|
|
{ 366, 3134, 2434, 19, 10874902, 6 },
|
|
{ 482, 3148, 2322, 19, 10874904, 6 },
|
|
{ 608, 3162, 2370, 19, 10874906, 6 },
|
|
{ 726, 3176, 2201, 19, 10874908, 6 },
|
|
{ 840, 3190, 2257, 19, 10874910, 6 },
|
|
{ 946, 3204, 2076, 19, 10874912, 6 },
|
|
{ 1060, 3218, 2136, 19, 10874914, 6 },
|
|
{ 1166, 3232, 1956, 19, 10874916, 6 },
|
|
{ 9, 3246, 2016, 19, 10874918, 6 },
|
|
{ 144, 3260, 1836, 19, 10874920, 6 },
|
|
{ 285, 3274, 1896, 19, 10874922, 6 },
|
|
{ 411, 3288, 1716, 19, 10874924, 6 },
|
|
{ 526, 3302, 1776, 19, 10874926, 6 },
|
|
{ 652, 3316, 1621, 19, 10874928, 6 },
|
|
{ 771, 11, 1680, 2, 45106, 212 },
|
|
{ 885, 11, 1550, 2, 45107, 212 },
|
|
{ 991, 11, 1585, 2, 45108, 212 },
|
|
{ 1105, 11, 1480, 2, 45109, 212 },
|
|
{ 59, 11, 1515, 2, 45110, 212 },
|
|
{ 195, 11, 1410, 2, 45111, 212 },
|
|
{ 339, 11, 1445, 2, 45112, 212 },
|
|
{ 459, 11, 1340, 2, 45113, 212 },
|
|
{ 578, 11, 1375, 2, 45114, 212 },
|
|
{ 700, 11, 1269, 2, 45115, 212 },
|
|
{ 807, 11, 1309, 2, 45116, 212 },
|
|
{ 917, 11, 835, 2, 45117, 212 },
|
|
{ 1027, 11, 883, 2, 45118, 212 },
|
|
{ 1137, 11, 856, 2, 45119, 212 },
|
|
{ 95, 11, 901, 2, 45120, 212 },
|
|
{ 227, 11, 1261, 2, 45121, 212 },
|
|
{ 393, 11, 11, 2, 45122, 212 },
|
|
{ 128, 11, 11, 2, 45123, 212 },
|
|
{ 260, 11, 11, 2, 45124, 212 },
|
|
{ 384, 11, 11, 2, 45125, 212 },
|
|
{ 122, 11, 11, 2, 45126, 212 },
|
|
{ 125, 3123, 3555, 22, 12689426, 9 },
|
|
{ 257, 3144, 2867, 22, 12689430, 9 },
|
|
{ 381, 3172, 3077, 22, 12689434, 9 },
|
|
{ 503, 3200, 3007, 22, 12689438, 9 },
|
|
{ 632, 3228, 2997, 22, 12689442, 9 },
|
|
{ 747, 3256, 2987, 22, 12689446, 9 },
|
|
{ 864, 3284, 2977, 22, 12689450, 9 },
|
|
{ 967, 3312, 2967, 22, 12689454, 9 },
|
|
{ 1084, 2893, 2957, 0, 10874930, 18 },
|
|
{ 1187, 2896, 2947, 0, 10874932, 18 },
|
|
{ 35, 2899, 2937, 0, 10874934, 18 },
|
|
{ 171, 2902, 2927, 0, 10874936, 18 },
|
|
{ 315, 2905, 2917, 0, 10874938, 18 },
|
|
{ 439, 2908, 2782, 0, 10874940, 18 },
|
|
{ 558, 2911, 927, 0, 10874942, 18 },
|
|
{ 680, 2914, 3551, 0, 10874944, 18 },
|
|
{ 131, 11, 3811, 2, 45127, 212 },
|
|
{ 263, 11, 3809, 2, 45128, 212 },
|
|
{ 387, 11, 3809, 2, 45129, 212 },
|
|
{ 509, 11, 3807, 2, 45130, 212 },
|
|
{ 635, 11, 3807, 2, 45131, 212 },
|
|
{ 753, 11, 3805, 2, 45132, 212 },
|
|
{ 867, 11, 3805, 2, 45133, 212 },
|
|
{ 973, 11, 3803, 2, 45134, 212 },
|
|
{ 1087, 11, 3803, 2, 45135, 212 },
|
|
{ 1193, 11, 3801, 2, 45136, 212 },
|
|
{ 39, 11, 3801, 2, 45137, 212 },
|
|
{ 179, 11, 3799, 2, 45138, 212 },
|
|
{ 319, 11, 3799, 2, 45139, 212 },
|
|
{ 134, 11, 2493, 2, 45074, 212 },
|
|
{ 272, 11, 2484, 2, 45075, 212 },
|
|
{ 390, 11, 962, 2, 45076, 212 },
|
|
{ 512, 11, 950, 2, 45077, 212 },
|
|
{ 638, 11, 2451, 2, 45078, 212 },
|
|
{ 756, 11, 2433, 2, 45079, 212 },
|
|
{ 870, 11, 2340, 2, 45080, 212 },
|
|
{ 976, 11, 2321, 2, 45081, 212 },
|
|
{ 1090, 11, 2391, 2, 45082, 212 },
|
|
{ 1196, 11, 2369, 2, 45083, 212 },
|
|
{ 43, 11, 2222, 2, 45084, 212 },
|
|
{ 183, 11, 2200, 2, 45085, 212 },
|
|
{ 323, 11, 2280, 2, 45086, 212 },
|
|
{ 443, 11, 2256, 2, 45087, 212 },
|
|
{ 562, 11, 2099, 2, 45088, 212 },
|
|
{ 684, 11, 2075, 2, 45089, 212 },
|
|
{ 791, 11, 2159, 2, 45090, 212 },
|
|
{ 901, 11, 2135, 2, 45091, 212 },
|
|
{ 1011, 11, 1979, 2, 45092, 212 },
|
|
{ 1121, 11, 1955, 2, 45093, 212 },
|
|
{ 79, 11, 2039, 2, 45094, 212 },
|
|
{ 215, 11, 2015, 2, 45095, 212 },
|
|
{ 359, 11, 1859, 2, 45096, 212 },
|
|
{ 475, 11, 1835, 2, 45097, 212 },
|
|
{ 598, 11, 1919, 2, 45098, 212 },
|
|
{ 716, 11, 1895, 2, 45099, 212 },
|
|
{ 827, 11, 1739, 2, 45100, 212 },
|
|
{ 933, 11, 1715, 2, 45101, 212 },
|
|
{ 1047, 11, 1799, 2, 45102, 212 },
|
|
{ 1153, 11, 1775, 2, 45103, 212 },
|
|
{ 115, 11, 1644, 2, 45104, 212 },
|
|
{ 247, 11, 1620, 2, 45105, 212 },
|
|
{ 363, 3137, 2487, 29, 12738578, 21 },
|
|
{ 479, 3151, 974, 29, 12738580, 21 },
|
|
{ 605, 3165, 2469, 29, 12738582, 21 },
|
|
{ 723, 3179, 2359, 29, 12738584, 21 },
|
|
{ 837, 3193, 2413, 29, 12738586, 21 },
|
|
{ 943, 3207, 2244, 29, 12738588, 21 },
|
|
{ 1057, 3221, 2304, 29, 12738590, 21 },
|
|
{ 1163, 3235, 2123, 29, 12738592, 21 },
|
|
{ 6, 3249, 2183, 29, 12738594, 21 },
|
|
{ 154, 3263, 2003, 29, 12738596, 21 },
|
|
{ 281, 3277, 2063, 29, 12738598, 21 },
|
|
{ 407, 3291, 1883, 29, 12738600, 21 },
|
|
{ 522, 3305, 1943, 29, 12738602, 21 },
|
|
{ 648, 3319, 1763, 29, 12738604, 21 },
|
|
{ 767, 2425, 1823, 11, 14532654, 33 },
|
|
{ 881, 2316, 1668, 11, 13652016, 33 },
|
|
{ 987, 3326, 1703, 8, 13627442, 37 },
|
|
{ 1101, 3326, 1573, 8, 13627443, 37 },
|
|
{ 55, 3326, 1608, 8, 13627444, 37 },
|
|
{ 207, 3326, 1503, 8, 13627445, 37 },
|
|
{ 335, 3326, 1538, 8, 13627446, 37 },
|
|
{ 455, 3326, 1433, 8, 13627447, 37 },
|
|
{ 574, 3326, 1468, 8, 13627448, 37 },
|
|
{ 696, 3326, 1363, 8, 13627449, 37 },
|
|
{ 803, 3326, 1398, 8, 13627450, 37 },
|
|
{ 913, 3326, 1292, 8, 13627451, 37 },
|
|
{ 1023, 3326, 1330, 8, 13627452, 37 },
|
|
{ 1133, 3326, 873, 8, 13627453, 37 },
|
|
{ 91, 3326, 912, 8, 13627454, 37 },
|
|
{ 239, 3326, 1263, 8, 13627455, 37 },
|
|
{ 254, 3779, 3557, 168, 12673042, 55 },
|
|
{ 378, 3759, 3117, 168, 12673046, 55 },
|
|
{ 500, 3739, 3102, 168, 12673050, 55 },
|
|
{ 629, 3719, 3102, 168, 12673054, 55 },
|
|
{ 744, 3699, 3102, 168, 12673058, 55 },
|
|
{ 861, 3679, 3102, 168, 12673062, 55 },
|
|
{ 964, 3659, 3102, 168, 12673066, 55 },
|
|
{ 1081, 3643, 3102, 88, 12681262, 72 },
|
|
{ 1184, 3631, 3102, 76, 12689458, 85 },
|
|
{ 32, 3619, 3102, 76, 12689460, 85 },
|
|
{ 167, 3607, 3102, 76, 12689462, 85 },
|
|
{ 311, 3595, 3102, 76, 12689464, 85 },
|
|
{ 435, 3583, 3102, 76, 12689466, 85 },
|
|
{ 554, 3571, 3114, 76, 12689468, 85 },
|
|
{ 676, 3559, 3553, 76, 12689470, 85 },
|
|
{ 494, 628, 11, 474, 12640274, 147 },
|
|
{ 623, 573, 11, 474, 12640278, 147 },
|
|
{ 738, 518, 11, 474, 12640282, 147 },
|
|
{ 855, 463, 11, 474, 12640286, 147 },
|
|
{ 958, 408, 11, 474, 12640290, 147 },
|
|
{ 1075, 357, 11, 423, 12648486, 164 },
|
|
{ 1178, 310, 11, 376, 12656682, 179 },
|
|
{ 26, 267, 11, 333, 12664878, 192 },
|
|
{ 161, 228, 11, 294, 12673074, 203 },
|
|
{ 304, 189, 11, 294, 12673076, 203 },
|
|
{ 427, 150, 11, 294, 12673078, 203 },
|
|
{ 546, 111, 11, 294, 12673080, 203 },
|
|
{ 668, 72, 11, 294, 12673082, 203 },
|
|
{ 266, 2875, 11, 16, 10874951, 3 },
|
|
{ 506, 2878, 11, 16, 10874953, 3 },
|
|
{ 750, 2881, 11, 16, 10874955, 3 },
|
|
{ 970, 2884, 11, 16, 10874957, 3 },
|
|
{ 1190, 2887, 11, 16, 10874959, 3 },
|
|
{ 175, 2890, 11, 16, 10874961, 3 },
|
|
{ 1248, 2551, 11, 16, 14618638, 0 },
|
|
{ 369, 3951, 3556, 63, 12681234, 26 },
|
|
{ 485, 2641, 983, 63, 12681236, 26 },
|
|
{ 614, 3938, 2870, 63, 12681238, 26 },
|
|
{ 729, 2628, 2862, 63, 12681240, 26 },
|
|
{ 846, 3925, 3080, 63, 12681242, 26 },
|
|
{ 949, 2615, 2851, 63, 12681244, 26 },
|
|
{ 1066, 3912, 3071, 63, 12681246, 26 },
|
|
{ 1169, 2602, 2845, 63, 12681248, 26 },
|
|
{ 16, 3899, 3065, 63, 12681250, 26 },
|
|
{ 137, 2589, 2839, 63, 12681252, 26 },
|
|
{ 292, 3886, 3059, 63, 12681254, 26 },
|
|
{ 415, 2576, 2833, 63, 12681256, 26 },
|
|
{ 534, 3873, 3053, 63, 12681258, 26 },
|
|
{ 656, 2563, 2827, 63, 12681260, 26 },
|
|
{ 779, 3862, 3047, 52, 12685358, 40 },
|
|
{ 889, 2554, 2821, 43, 12689456, 46 },
|
|
{ 999, 3855, 3041, 36, 11976754, 51 },
|
|
{ 1109, 2544, 2815, 36, 11976755, 51 },
|
|
{ 67, 3848, 3035, 36, 11976756, 51 },
|
|
{ 187, 2537, 2809, 36, 11976757, 51 },
|
|
{ 347, 3841, 3029, 36, 11976758, 51 },
|
|
{ 463, 2530, 2803, 36, 11976759, 51 },
|
|
{ 586, 3834, 3023, 36, 11976760, 51 },
|
|
{ 704, 2523, 2797, 36, 11976761, 51 },
|
|
{ 815, 3827, 3017, 36, 11976762, 51 },
|
|
{ 921, 2516, 2791, 36, 11976763, 51 },
|
|
{ 1035, 3820, 2857, 36, 11976764, 51 },
|
|
{ 1141, 2509, 935, 36, 11976765, 51 },
|
|
{ 103, 3813, 946, 36, 11976766, 51 },
|
|
{ 219, 2502, 3552, 36, 11976767, 51 },
|
|
{ 602, 3490, 2490, 212, 12730386, 90 },
|
|
{ 720, 3478, 2430, 212, 12730388, 90 },
|
|
{ 834, 3466, 2479, 212, 12730390, 90 },
|
|
{ 940, 3454, 2386, 212, 12730392, 90 },
|
|
{ 1054, 3442, 2386, 212, 12730394, 90 },
|
|
{ 1160, 3430, 2275, 212, 12730396, 90 },
|
|
{ 3, 3418, 2275, 212, 12730398, 90 },
|
|
{ 151, 3406, 2154, 212, 12730400, 90 },
|
|
{ 278, 3394, 2154, 212, 12730402, 90 },
|
|
{ 404, 3382, 2034, 212, 12730404, 90 },
|
|
{ 518, 3370, 2034, 212, 12730406, 90 },
|
|
{ 644, 3358, 1914, 212, 12730408, 90 },
|
|
{ 763, 3512, 1914, 202, 14524458, 97 },
|
|
{ 877, 3502, 1794, 202, 13643820, 97 },
|
|
{ 983, 3530, 1794, 194, 13738030, 103 },
|
|
{ 1097, 3522, 1698, 194, 13672496, 103 },
|
|
{ 51, 3538, 1698, 188, 13676594, 108 },
|
|
{ 203, 3538, 1603, 188, 13676595, 108 },
|
|
{ 331, 3538, 1603, 188, 13676596, 108 },
|
|
{ 451, 3538, 1533, 188, 13676597, 108 },
|
|
{ 570, 3538, 1533, 188, 13676598, 108 },
|
|
{ 692, 3538, 1463, 188, 13676599, 108 },
|
|
{ 799, 3538, 1463, 188, 13676600, 108 },
|
|
{ 909, 3538, 1393, 188, 13676601, 108 },
|
|
{ 1019, 3538, 1393, 188, 13676602, 108 },
|
|
{ 1129, 3538, 1304, 188, 13676603, 108 },
|
|
{ 87, 3538, 1327, 188, 13676604, 108 },
|
|
{ 235, 3538, 1266, 188, 13676605, 108 },
|
|
{ 831, 1149, 2491, 276, 12722194, 112 },
|
|
{ 937, 1131, 2428, 276, 12722196, 112 },
|
|
{ 1051, 1113, 2428, 276, 12722198, 112 },
|
|
{ 1157, 1095, 2319, 276, 12722200, 112 },
|
|
{ 0, 1077, 2319, 276, 12722202, 112 },
|
|
{ 148, 1059, 2198, 276, 12722204, 112 },
|
|
{ 275, 1041, 2198, 276, 12722206, 112 },
|
|
{ 401, 1023, 2097, 276, 12722208, 112 },
|
|
{ 515, 1005, 2097, 276, 12722210, 112 },
|
|
{ 641, 987, 1977, 276, 12722212, 112 },
|
|
{ 759, 1183, 1977, 260, 14516262, 121 },
|
|
{ 873, 1167, 1857, 260, 13635624, 121 },
|
|
{ 979, 1213, 1857, 246, 13729834, 129 },
|
|
{ 1093, 1199, 1737, 246, 13664300, 129 },
|
|
{ 47, 1239, 1737, 234, 13709358, 136 },
|
|
{ 199, 1227, 1642, 234, 13688880, 136 },
|
|
{ 327, 1251, 1642, 224, 13692978, 142 },
|
|
{ 447, 1251, 1571, 224, 13692979, 142 },
|
|
{ 566, 1251, 1571, 224, 13692980, 142 },
|
|
{ 688, 1251, 1501, 224, 13692981, 142 },
|
|
{ 795, 1251, 1501, 224, 13692982, 142 },
|
|
{ 905, 1251, 1431, 224, 13692983, 142 },
|
|
{ 1015, 1251, 1431, 224, 13692984, 142 },
|
|
{ 1125, 1251, 1328, 224, 13692985, 142 },
|
|
{ 83, 1251, 1328, 224, 13692986, 142 },
|
|
{ 231, 1251, 1267, 224, 13692987, 142 },
|
|
{ 372, 3130, 981, 22, 12689428, 9 },
|
|
{ 617, 3158, 2675, 22, 12689432, 9 },
|
|
{ 849, 3186, 2773, 22, 12689436, 9 },
|
|
{ 1069, 3214, 2764, 22, 12689440, 9 },
|
|
{ 19, 3242, 2755, 22, 12689444, 9 },
|
|
{ 296, 3270, 2746, 22, 12689448, 9 },
|
|
{ 538, 3298, 2737, 22, 12689452, 9 },
|
|
{ 783, 2195, 2728, 3, 11976752, 14 },
|
|
{ 1003, 2654, 2719, 0, 10874931, 18 },
|
|
{ 71, 2657, 2710, 0, 10874933, 18 },
|
|
{ 351, 2660, 2701, 0, 10874935, 18 },
|
|
{ 590, 2663, 2692, 0, 10874937, 18 },
|
|
{ 819, 2666, 2683, 0, 10874939, 18 },
|
|
{ 1039, 2669, 919, 0, 10874941, 18 },
|
|
{ 107, 2672, 940, 0, 10874943, 18 },
|
|
{ 611, 815, 960, 148, 12673044, 55 },
|
|
{ 843, 795, 2680, 148, 12673048, 55 },
|
|
{ 1063, 775, 2680, 148, 12673052, 55 },
|
|
{ 13, 755, 2680, 148, 12673056, 55 },
|
|
{ 289, 735, 2680, 148, 12673060, 55 },
|
|
{ 530, 715, 2680, 148, 12673064, 55 },
|
|
{ 775, 697, 2680, 130, 12677164, 64 },
|
|
{ 995, 683, 2680, 116, 12685360, 79 },
|
|
{ 63, 60, 2680, 104, 12689459, 85 },
|
|
{ 343, 48, 2680, 104, 12689461, 85 },
|
|
{ 582, 36, 2680, 104, 12689463, 85 },
|
|
{ 811, 24, 2680, 104, 12689465, 85 },
|
|
{ 1031, 12, 2680, 104, 12689467, 85 },
|
|
{ 99, 0, 854, 104, 12689469, 85 },
|
|
};
|
|
|
|
// HPR Register Class...
|
|
static const MCPhysReg HPR[] = {
|
|
ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31,
|
|
};
|
|
|
|
// HPR Bit set.
|
|
static const uint8_t HPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
|
};
|
|
|
|
// FPWithVPR Register Class...
|
|
static const MCPhysReg FPWithVPR[] = {
|
|
ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31, ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31, ARM_VPR,
|
|
};
|
|
|
|
// FPWithVPR Bit set.
|
|
static const uint8_t FPWithVPRBits[] = {
|
|
0x00, 0x00, 0xf4, 0xff, 0xff, 0xff, 0x0f, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
|
};
|
|
|
|
// SPR Register Class...
|
|
static const MCPhysReg SPR[] = {
|
|
ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15, ARM_S16, ARM_S17, ARM_S18, ARM_S19, ARM_S20, ARM_S21, ARM_S22, ARM_S23, ARM_S24, ARM_S25, ARM_S26, ARM_S27, ARM_S28, ARM_S29, ARM_S30, ARM_S31,
|
|
};
|
|
|
|
// SPR Bit set.
|
|
static const uint8_t SPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x3f,
|
|
};
|
|
|
|
// FPWithVPR_with_ssub_0 Register Class...
|
|
static const MCPhysReg FPWithVPR_with_ssub_0[] = {
|
|
ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15,
|
|
};
|
|
|
|
// FPWithVPR_with_ssub_0 Bit set.
|
|
static const uint8_t FPWithVPR_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0xf0, 0xff, 0x0f,
|
|
};
|
|
|
|
// GPR Register Class...
|
|
static const MCPhysReg GPR[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
|
|
};
|
|
|
|
// GPR Bit set.
|
|
static const uint8_t GPRBits[] = {
|
|
0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRwithAPSR Register Class...
|
|
static const MCPhysReg GPRwithAPSR[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_APSR_NZCV,
|
|
};
|
|
|
|
// GPRwithAPSR Bit set.
|
|
static const uint8_t GPRwithAPSRBits[] = {
|
|
0x04, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRwithZR Register Class...
|
|
static const MCPhysReg GPRwithZR[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_ZR,
|
|
};
|
|
|
|
// GPRwithZR Bit set.
|
|
static const uint8_t GPRwithZRBits[] = {
|
|
0x00, 0x20, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// SPR_8 Register Class...
|
|
static const MCPhysReg SPR_8[] = {
|
|
ARM_S0, ARM_S1, ARM_S2, ARM_S3, ARM_S4, ARM_S5, ARM_S6, ARM_S7, ARM_S8, ARM_S9, ARM_S10, ARM_S11, ARM_S12, ARM_S13, ARM_S14, ARM_S15,
|
|
};
|
|
|
|
// SPR_8 Bit set.
|
|
static const uint8_t SPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
|
|
};
|
|
|
|
// GPRnopc Register Class...
|
|
static const MCPhysReg GPRnopc[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
|
|
};
|
|
|
|
// GPRnopc Bit set.
|
|
static const uint8_t GPRnopcBits[] = {
|
|
0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRnosp Register Class...
|
|
static const MCPhysReg GPRnosp[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_PC,
|
|
};
|
|
|
|
// GPRnosp Bit set.
|
|
static const uint8_t GPRnospBits[] = {
|
|
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRwithAPSR_NZCVnosp Register Class...
|
|
static const MCPhysReg GPRwithAPSR_NZCVnosp[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR_NZCV,
|
|
};
|
|
|
|
// GPRwithAPSR_NZCVnosp Bit set.
|
|
static const uint8_t GPRwithAPSR_NZCVnospBits[] = {
|
|
0x04, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRwithAPSRnosp Register Class...
|
|
static const MCPhysReg GPRwithAPSRnosp[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_APSR,
|
|
};
|
|
|
|
// GPRwithAPSRnosp Bit set.
|
|
static const uint8_t GPRwithAPSRnospBits[] = {
|
|
0x02, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRwithZRnosp Register Class...
|
|
static const MCPhysReg GPRwithZRnosp[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_ZR,
|
|
};
|
|
|
|
// GPRwithZRnosp Bit set.
|
|
static const uint8_t GPRwithZRnospBits[] = {
|
|
0x00, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRnoip Register Class...
|
|
static const MCPhysReg GPRnoip[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC,
|
|
};
|
|
|
|
// GPRnoip Bit set.
|
|
static const uint8_t GPRnoipBits[] = {
|
|
0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
|
|
};
|
|
|
|
// rGPR Register Class...
|
|
static const MCPhysReg rGPR[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR,
|
|
};
|
|
|
|
// rGPR Bit set.
|
|
static const uint8_t rGPRBits[] = {
|
|
0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x3f,
|
|
};
|
|
|
|
// GPRnoip_and_GPRnopc Register Class...
|
|
static const MCPhysReg GPRnoip_and_GPRnopc[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP,
|
|
};
|
|
|
|
// GPRnoip_and_GPRnopc Bit set.
|
|
static const uint8_t GPRnoip_and_GPRnopcBits[] = {
|
|
0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
|
|
};
|
|
|
|
// GPRnoip_and_GPRnosp Register Class...
|
|
static const MCPhysReg GPRnoip_and_GPRnosp[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_PC,
|
|
};
|
|
|
|
// GPRnoip_and_GPRnosp Bit set.
|
|
static const uint8_t GPRnoip_and_GPRnospBits[] = {
|
|
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
|
|
};
|
|
|
|
// GPRnoip_and_GPRwithAPSR_NZCVnosp Register Class...
|
|
static const MCPhysReg GPRnoip_and_GPRwithAPSR_NZCVnosp[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_R8, ARM_R9, ARM_R10, ARM_R11,
|
|
};
|
|
|
|
// GPRnoip_and_GPRwithAPSR_NZCVnosp Bit set.
|
|
static const uint8_t GPRnoip_and_GPRwithAPSR_NZCVnospBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x1f,
|
|
};
|
|
|
|
// tGPRwithpc Register Class...
|
|
static const MCPhysReg tGPRwithpc[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7, ARM_PC,
|
|
};
|
|
|
|
// tGPRwithpc Bit set.
|
|
static const uint8_t tGPRwithpcBits[] = {
|
|
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
|
|
};
|
|
|
|
// FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Register Class...
|
|
static const MCPhysReg FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8[] = {
|
|
ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7,
|
|
};
|
|
|
|
// FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8 Bit set.
|
|
static const uint8_t FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits[] = {
|
|
0x00, 0x00, 0xf0, 0x0f,
|
|
};
|
|
|
|
// hGPR Register Class...
|
|
static const MCPhysReg hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR, ARM_PC,
|
|
};
|
|
|
|
// hGPR Bit set.
|
|
static const uint8_t hGPRBits[] = {
|
|
0x00, 0x60, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
|
|
};
|
|
|
|
// tGPR Register Class...
|
|
static const MCPhysReg tGPR[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R4, ARM_R5, ARM_R6, ARM_R7,
|
|
};
|
|
|
|
// tGPR Bit set.
|
|
static const uint8_t tGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
|
|
};
|
|
|
|
// tGPREven Register Class...
|
|
static const MCPhysReg tGPREven[] = {
|
|
ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10, ARM_R12, ARM_LR,
|
|
};
|
|
|
|
// tGPREven Bit set.
|
|
static const uint8_t tGPREvenBits[] = {
|
|
0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x2a,
|
|
};
|
|
|
|
// GPRnopc_and_hGPR Register Class...
|
|
static const MCPhysReg GPRnopc_and_hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_SP, ARM_LR,
|
|
};
|
|
|
|
// GPRnopc_and_hGPR Bit set.
|
|
static const uint8_t GPRnopc_and_hGPRBits[] = {
|
|
0x00, 0x20, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
|
|
};
|
|
|
|
// GPRnosp_and_hGPR Register Class...
|
|
static const MCPhysReg GPRnosp_and_hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR, ARM_PC,
|
|
};
|
|
|
|
// GPRnosp_and_hGPR Bit set.
|
|
static const uint8_t GPRnosp_and_hGPRBits[] = {
|
|
0x00, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
|
|
};
|
|
|
|
// GPRnoip_and_hGPR Register Class...
|
|
static const MCPhysReg GPRnoip_and_hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP, ARM_PC,
|
|
};
|
|
|
|
// GPRnoip_and_hGPR Bit set.
|
|
static const uint8_t GPRnoip_and_hGPRBits[] = {
|
|
0x00, 0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
|
|
};
|
|
|
|
// GPRnoip_and_tGPREven Register Class...
|
|
static const MCPhysReg GPRnoip_and_tGPREven[] = {
|
|
ARM_R0, ARM_R2, ARM_R4, ARM_R6, ARM_R8, ARM_R10,
|
|
};
|
|
|
|
// GPRnoip_and_tGPREven Bit set.
|
|
static const uint8_t GPRnoip_and_tGPREvenBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0x0a,
|
|
};
|
|
|
|
// GPRnosp_and_GPRnopc_and_hGPR Register Class...
|
|
static const MCPhysReg GPRnosp_and_GPRnopc_and_hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_R12, ARM_LR,
|
|
};
|
|
|
|
// GPRnosp_and_GPRnopc_and_hGPR Bit set.
|
|
static const uint8_t GPRnosp_and_GPRnopc_and_hGPRBits[] = {
|
|
0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e,
|
|
};
|
|
|
|
// tGPROdd Register Class...
|
|
static const MCPhysReg tGPROdd[] = {
|
|
ARM_R1, ARM_R3, ARM_R5, ARM_R7, ARM_R9, ARM_R11,
|
|
};
|
|
|
|
// tGPROdd Bit set.
|
|
static const uint8_t tGPROddBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x15,
|
|
};
|
|
|
|
// GPRnopc_and_GPRnoip_and_hGPR Register Class...
|
|
static const MCPhysReg GPRnopc_and_GPRnoip_and_hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_SP,
|
|
};
|
|
|
|
// GPRnopc_and_GPRnoip_and_hGPR Bit set.
|
|
static const uint8_t GPRnopc_and_GPRnoip_and_hGPRBits[] = {
|
|
0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
|
|
};
|
|
|
|
// GPRnosp_and_GPRnoip_and_hGPR Register Class...
|
|
static const MCPhysReg GPRnosp_and_GPRnoip_and_hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11, ARM_PC,
|
|
};
|
|
|
|
// GPRnosp_and_GPRnoip_and_hGPR Bit set.
|
|
static const uint8_t GPRnosp_and_GPRnoip_and_hGPRBits[] = {
|
|
0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
|
|
};
|
|
|
|
// tcGPR Register Class...
|
|
static const MCPhysReg tcGPR[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3, ARM_R12,
|
|
};
|
|
|
|
// tcGPR Bit set.
|
|
static const uint8_t tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x20,
|
|
};
|
|
|
|
// GPRnoip_and_tcGPR Register Class...
|
|
static const MCPhysReg GPRnoip_and_tcGPR[] = {
|
|
ARM_R0, ARM_R1, ARM_R2, ARM_R3,
|
|
};
|
|
|
|
// GPRnoip_and_tcGPR Bit set.
|
|
static const uint8_t GPRnoip_and_tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
|
|
};
|
|
|
|
// GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Register Class...
|
|
static const MCPhysReg GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR[] = {
|
|
ARM_R8, ARM_R9, ARM_R10, ARM_R11,
|
|
};
|
|
|
|
// GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR Bit set.
|
|
static const uint8_t GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
|
|
};
|
|
|
|
// hGPR_and_tGPREven Register Class...
|
|
static const MCPhysReg hGPR_and_tGPREven[] = {
|
|
ARM_R8, ARM_R10, ARM_R12, ARM_LR,
|
|
};
|
|
|
|
// hGPR_and_tGPREven Bit set.
|
|
static const uint8_t hGPR_and_tGPREvenBits[] = {
|
|
0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2a,
|
|
};
|
|
|
|
// tGPR_and_tGPREven Register Class...
|
|
static const MCPhysReg tGPR_and_tGPREven[] = {
|
|
ARM_R0, ARM_R2, ARM_R4, ARM_R6,
|
|
};
|
|
|
|
// tGPR_and_tGPREven Bit set.
|
|
static const uint8_t tGPR_and_tGPREvenBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa,
|
|
};
|
|
|
|
// tGPR_and_tGPROdd Register Class...
|
|
static const MCPhysReg tGPR_and_tGPROdd[] = {
|
|
ARM_R1, ARM_R3, ARM_R5, ARM_R7,
|
|
};
|
|
|
|
// tGPR_and_tGPROdd Bit set.
|
|
static const uint8_t tGPR_and_tGPROddBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x01,
|
|
};
|
|
|
|
// tGPREven_and_tcGPR Register Class...
|
|
static const MCPhysReg tGPREven_and_tcGPR[] = {
|
|
ARM_R0, ARM_R2, ARM_R12,
|
|
};
|
|
|
|
// tGPREven_and_tcGPR Bit set.
|
|
static const uint8_t tGPREven_and_tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a, 0x20,
|
|
};
|
|
|
|
// hGPR_and_GPRnoip_and_tGPREven Register Class...
|
|
static const MCPhysReg hGPR_and_GPRnoip_and_tGPREven[] = {
|
|
ARM_R8, ARM_R10,
|
|
};
|
|
|
|
// hGPR_and_GPRnoip_and_tGPREven Bit set.
|
|
static const uint8_t hGPR_and_GPRnoip_and_tGPREvenBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
|
|
};
|
|
|
|
// hGPR_and_tGPROdd Register Class...
|
|
static const MCPhysReg hGPR_and_tGPROdd[] = {
|
|
ARM_R9, ARM_R11,
|
|
};
|
|
|
|
// hGPR_and_tGPROdd Bit set.
|
|
static const uint8_t hGPR_and_tGPROddBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
|
|
};
|
|
|
|
// tGPREven_and_GPRnoip_and_tcGPR Register Class...
|
|
static const MCPhysReg tGPREven_and_GPRnoip_and_tcGPR[] = {
|
|
ARM_R0, ARM_R2,
|
|
};
|
|
|
|
// tGPREven_and_GPRnoip_and_tcGPR Bit set.
|
|
static const uint8_t tGPREven_and_GPRnoip_and_tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0a,
|
|
};
|
|
|
|
// tGPROdd_and_tcGPR Register Class...
|
|
static const MCPhysReg tGPROdd_and_tcGPR[] = {
|
|
ARM_R1, ARM_R3,
|
|
};
|
|
|
|
// tGPROdd_and_tcGPR Bit set.
|
|
static const uint8_t tGPROdd_and_tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14,
|
|
};
|
|
|
|
// CCR Register Class...
|
|
static const MCPhysReg CCR[] = {
|
|
ARM_CPSR,
|
|
};
|
|
|
|
// CCR Bit set.
|
|
static const uint8_t CCRBits[] = {
|
|
0x08,
|
|
};
|
|
|
|
// FPCXTRegs Register Class...
|
|
static const MCPhysReg FPCXTRegs[] = {
|
|
ARM_FPCXTNS,
|
|
};
|
|
|
|
// FPCXTRegs Bit set.
|
|
static const uint8_t FPCXTRegsBits[] = {
|
|
0x10,
|
|
};
|
|
|
|
// GPRlr Register Class...
|
|
static const MCPhysReg GPRlr[] = {
|
|
ARM_LR,
|
|
};
|
|
|
|
// GPRlr Bit set.
|
|
static const uint8_t GPRlrBits[] = {
|
|
0x00, 0x20,
|
|
};
|
|
|
|
// GPRsp Register Class...
|
|
static const MCPhysReg GPRsp[] = {
|
|
ARM_SP,
|
|
};
|
|
|
|
// GPRsp Bit set.
|
|
static const uint8_t GPRspBits[] = {
|
|
0x00, 0x00, 0x01,
|
|
};
|
|
|
|
// VCCR Register Class...
|
|
static const MCPhysReg VCCR[] = {
|
|
ARM_VPR,
|
|
};
|
|
|
|
// VCCR Bit set.
|
|
static const uint8_t VCCRBits[] = {
|
|
0x00, 0x00, 0x04,
|
|
};
|
|
|
|
// cl_FPSCR_NZCV Register Class...
|
|
static const MCPhysReg cl_FPSCR_NZCV[] = {
|
|
ARM_FPSCR_NZCV,
|
|
};
|
|
|
|
// cl_FPSCR_NZCV Bit set.
|
|
static const uint8_t cl_FPSCR_NZCVBits[] = {
|
|
0x00, 0x02,
|
|
};
|
|
|
|
// hGPR_and_tGPRwithpc Register Class...
|
|
static const MCPhysReg hGPR_and_tGPRwithpc[] = {
|
|
ARM_PC,
|
|
};
|
|
|
|
// hGPR_and_tGPRwithpc Bit set.
|
|
static const uint8_t hGPR_and_tGPRwithpcBits[] = {
|
|
0x00, 0x40,
|
|
};
|
|
|
|
// hGPR_and_tcGPR Register Class...
|
|
static const MCPhysReg hGPR_and_tcGPR[] = {
|
|
ARM_R12,
|
|
};
|
|
|
|
// hGPR_and_tcGPR Bit set.
|
|
static const uint8_t hGPR_and_tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20,
|
|
};
|
|
|
|
// DPR Register Class...
|
|
static const MCPhysReg DPR[] = {
|
|
ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15, ARM_D16, ARM_D17, ARM_D18, ARM_D19, ARM_D20, ARM_D21, ARM_D22, ARM_D23, ARM_D24, ARM_D25, ARM_D26, ARM_D27, ARM_D28, ARM_D29, ARM_D30, ARM_D31,
|
|
};
|
|
|
|
// DPR Bit set.
|
|
static const uint8_t DPRBits[] = {
|
|
0x00, 0x00, 0xf0, 0xff, 0xff, 0xff, 0x0f,
|
|
};
|
|
|
|
// DPR_VFP2 Register Class...
|
|
static const MCPhysReg DPR_VFP2[] = {
|
|
ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7, ARM_D8, ARM_D9, ARM_D10, ARM_D11, ARM_D12, ARM_D13, ARM_D14, ARM_D15,
|
|
};
|
|
|
|
// DPR_VFP2 Bit set.
|
|
static const uint8_t DPR_VFP2Bits[] = {
|
|
0x00, 0x00, 0xf0, 0xff, 0x0f,
|
|
};
|
|
|
|
// DPR_8 Register Class...
|
|
static const MCPhysReg DPR_8[] = {
|
|
ARM_D0, ARM_D1, ARM_D2, ARM_D3, ARM_D4, ARM_D5, ARM_D6, ARM_D7,
|
|
};
|
|
|
|
// DPR_8 Bit set.
|
|
static const uint8_t DPR_8Bits[] = {
|
|
0x00, 0x00, 0xf0, 0x0f,
|
|
};
|
|
|
|
// GPRPair Register Class...
|
|
static const MCPhysReg GPRPair[] = {
|
|
ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11, ARM_R12_SP,
|
|
};
|
|
|
|
// GPRPair Bit set.
|
|
static const uint8_t GPRPairBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7f,
|
|
};
|
|
|
|
// GPRPairnosp Register Class...
|
|
static const MCPhysReg GPRPairnosp[] = {
|
|
ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7, ARM_R8_R9, ARM_R10_R11,
|
|
};
|
|
|
|
// GPRPairnosp Bit set.
|
|
static const uint8_t GPRPairnospBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3f,
|
|
};
|
|
|
|
// GPRPair_with_gsub_0_in_tGPR Register Class...
|
|
static const MCPhysReg GPRPair_with_gsub_0_in_tGPR[] = {
|
|
ARM_R0_R1, ARM_R2_R3, ARM_R4_R5, ARM_R6_R7,
|
|
};
|
|
|
|
// GPRPair_with_gsub_0_in_tGPR Bit set.
|
|
static const uint8_t GPRPair_with_gsub_0_in_tGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f,
|
|
};
|
|
|
|
// GPRPair_with_gsub_0_in_hGPR Register Class...
|
|
static const MCPhysReg GPRPair_with_gsub_0_in_hGPR[] = {
|
|
ARM_R8_R9, ARM_R10_R11, ARM_R12_SP,
|
|
};
|
|
|
|
// GPRPair_with_gsub_0_in_hGPR Bit set.
|
|
static const uint8_t GPRPair_with_gsub_0_in_hGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
|
|
};
|
|
|
|
// GPRPair_with_gsub_0_in_tcGPR Register Class...
|
|
static const MCPhysReg GPRPair_with_gsub_0_in_tcGPR[] = {
|
|
ARM_R0_R1, ARM_R2_R3, ARM_R12_SP,
|
|
};
|
|
|
|
// GPRPair_with_gsub_0_in_tcGPR Bit set.
|
|
static const uint8_t GPRPair_with_gsub_0_in_tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x43,
|
|
};
|
|
|
|
// GPRPair_with_gsub_1_in_tcGPR Register Class...
|
|
static const MCPhysReg GPRPair_with_gsub_1_in_tcGPR[] = {
|
|
ARM_R0_R1, ARM_R2_R3,
|
|
};
|
|
|
|
// GPRPair_with_gsub_1_in_tcGPR Bit set.
|
|
static const uint8_t GPRPair_with_gsub_1_in_tcGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
|
|
};
|
|
|
|
// GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Register Class...
|
|
static const MCPhysReg GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR[] = {
|
|
ARM_R8_R9, ARM_R10_R11,
|
|
};
|
|
|
|
// GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR Bit set.
|
|
static const uint8_t GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30,
|
|
};
|
|
|
|
// GPRPair_with_gsub_1_in_GPRsp Register Class...
|
|
static const MCPhysReg GPRPair_with_gsub_1_in_GPRsp[] = {
|
|
ARM_R12_SP,
|
|
};
|
|
|
|
// GPRPair_with_gsub_1_in_GPRsp Bit set.
|
|
static const uint8_t GPRPair_with_gsub_1_in_GPRspBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,
|
|
};
|
|
|
|
// DPairSpc Register Class...
|
|
static const MCPhysReg DPairSpc[] = {
|
|
ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17, ARM_D16_D18, ARM_D17_D19, ARM_D18_D20, ARM_D19_D21, ARM_D20_D22, ARM_D21_D23, ARM_D22_D24, ARM_D23_D25, ARM_D24_D26, ARM_D25_D27, ARM_D26_D28, ARM_D27_D29, ARM_D28_D30, ARM_D29_D31,
|
|
};
|
|
|
|
// DPairSpc Bit set.
|
|
static const uint8_t DPairSpcBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0xff, 0xff, 0x0f,
|
|
};
|
|
|
|
// DPairSpc_with_ssub_0 Register Class...
|
|
static const MCPhysReg DPairSpc_with_ssub_0[] = {
|
|
ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15, ARM_D14_D16, ARM_D15_D17,
|
|
};
|
|
|
|
// DPairSpc_with_ssub_0 Bit set.
|
|
static const uint8_t DPairSpc_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x3f,
|
|
};
|
|
|
|
// DPairSpc_with_ssub_4 Register Class...
|
|
static const MCPhysReg DPairSpc_with_ssub_4[] = {
|
|
ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9, ARM_D8_D10, ARM_D9_D11, ARM_D10_D12, ARM_D11_D13, ARM_D12_D14, ARM_D13_D15,
|
|
};
|
|
|
|
// DPairSpc_with_ssub_4 Bit set.
|
|
static const uint8_t DPairSpc_with_ssub_4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xff, 0x0f,
|
|
};
|
|
|
|
// DPairSpc_with_dsub_0_in_DPR_8 Register Class...
|
|
static const MCPhysReg DPairSpc_with_dsub_0_in_DPR_8[] = {
|
|
ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7, ARM_D6_D8, ARM_D7_D9,
|
|
};
|
|
|
|
// DPairSpc_with_dsub_0_in_DPR_8 Bit set.
|
|
static const uint8_t DPairSpc_with_dsub_0_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x3f,
|
|
};
|
|
|
|
// DPairSpc_with_dsub_2_in_DPR_8 Register Class...
|
|
static const MCPhysReg DPairSpc_with_dsub_2_in_DPR_8[] = {
|
|
ARM_D0_D2, ARM_D1_D3, ARM_D2_D4, ARM_D3_D5, ARM_D4_D6, ARM_D5_D7,
|
|
};
|
|
|
|
// DPairSpc_with_dsub_2_in_DPR_8 Bit set.
|
|
static const uint8_t DPairSpc_with_dsub_2_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x0f,
|
|
};
|
|
|
|
// DPair Register Class...
|
|
static const MCPhysReg DPair[] = {
|
|
ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16, ARM_Q8, ARM_D17_D18, ARM_Q9, ARM_D19_D20, ARM_Q10, ARM_D21_D22, ARM_Q11, ARM_D23_D24, ARM_Q12, ARM_D25_D26, ARM_Q13, ARM_D27_D28, ARM_Q14, ARM_D29_D30, ARM_Q15,
|
|
};
|
|
|
|
// DPair Bit set.
|
|
static const uint8_t DPairBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff, 0x03,
|
|
};
|
|
|
|
// DPair_with_ssub_0 Register Class...
|
|
static const MCPhysReg DPair_with_ssub_0[] = {
|
|
ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7, ARM_D15_D16,
|
|
};
|
|
|
|
// DPair_with_ssub_0 Bit set.
|
|
static const uint8_t DPair_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
|
};
|
|
|
|
// QPR Register Class...
|
|
static const MCPhysReg QPR[] = {
|
|
ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7, ARM_Q8, ARM_Q9, ARM_Q10, ARM_Q11, ARM_Q12, ARM_Q13, ARM_Q14, ARM_Q15,
|
|
};
|
|
|
|
// QPR Bit set.
|
|
static const uint8_t QPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0xff, 0x01,
|
|
};
|
|
|
|
// DPair_with_ssub_2 Register Class...
|
|
static const MCPhysReg DPair_with_ssub_2[] = {
|
|
ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8, ARM_Q4, ARM_D9_D10, ARM_Q5, ARM_D11_D12, ARM_Q6, ARM_D13_D14, ARM_Q7,
|
|
};
|
|
|
|
// DPair_with_ssub_2 Bit set.
|
|
static const uint8_t DPair_with_ssub_2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
|
};
|
|
|
|
// DPair_with_dsub_0_in_DPR_8 Register Class...
|
|
static const MCPhysReg DPair_with_dsub_0_in_DPR_8[] = {
|
|
ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3, ARM_D7_D8,
|
|
};
|
|
|
|
// DPair_with_dsub_0_in_DPR_8 Bit set.
|
|
static const uint8_t DPair_with_dsub_0_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
|
};
|
|
|
|
// MQPR Register Class...
|
|
static const MCPhysReg MQPR[] = {
|
|
ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7,
|
|
};
|
|
|
|
// MQPR Bit set.
|
|
static const uint8_t MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
|
|
};
|
|
|
|
// QPR_VFP2 Register Class...
|
|
static const MCPhysReg QPR_VFP2[] = {
|
|
ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3, ARM_Q4, ARM_Q5, ARM_Q6, ARM_Q7,
|
|
};
|
|
|
|
// QPR_VFP2 Bit set.
|
|
static const uint8_t QPR_VFP2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x01,
|
|
};
|
|
|
|
// DPair_with_dsub_1_in_DPR_8 Register Class...
|
|
static const MCPhysReg DPair_with_dsub_1_in_DPR_8[] = {
|
|
ARM_Q0, ARM_D1_D2, ARM_Q1, ARM_D3_D4, ARM_Q2, ARM_D5_D6, ARM_Q3,
|
|
};
|
|
|
|
// DPair_with_dsub_1_in_DPR_8 Bit set.
|
|
static const uint8_t DPair_with_dsub_1_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
|
|
};
|
|
|
|
// QPR_8 Register Class...
|
|
static const MCPhysReg QPR_8[] = {
|
|
ARM_Q0, ARM_Q1, ARM_Q2, ARM_Q3,
|
|
};
|
|
|
|
// QPR_8 Bit set.
|
|
static const uint8_t QPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1e,
|
|
};
|
|
|
|
// DTriple Register Class...
|
|
static const MCPhysReg DTriple[] = {
|
|
ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17, ARM_D16_D17_D18, ARM_D17_D18_D19, ARM_D18_D19_D20, ARM_D19_D20_D21, ARM_D20_D21_D22, ARM_D21_D22_D23, ARM_D22_D23_D24, ARM_D23_D24_D25, ARM_D24_D25_D26, ARM_D25_D26_D27, ARM_D26_D27_D28, ARM_D27_D28_D29, ARM_D28_D29_D30, ARM_D29_D30_D31,
|
|
};
|
|
|
|
// DTriple Bit set.
|
|
static const uint8_t DTripleBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff, 0x1f,
|
|
};
|
|
|
|
// DTripleSpc Register Class...
|
|
static const MCPhysReg DTripleSpc[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31,
|
|
};
|
|
|
|
// DTripleSpc Bit set.
|
|
static const uint8_t DTripleSpcBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x01,
|
|
};
|
|
|
|
// DTripleSpc_with_ssub_0 Register Class...
|
|
static const MCPhysReg DTripleSpc_with_ssub_0[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19,
|
|
};
|
|
|
|
// DTripleSpc_with_ssub_0 Bit set.
|
|
static const uint8_t DTripleSpc_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
|
|
};
|
|
|
|
// DTriple_with_ssub_0 Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_0[] = {
|
|
ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16, ARM_D15_D16_D17,
|
|
};
|
|
|
|
// DTriple_with_ssub_0 Bit set.
|
|
static const uint8_t DTriple_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x7f,
|
|
};
|
|
|
|
// DTriple_with_qsub_0_in_QPR Register Class...
|
|
static const MCPhysReg DTriple_with_qsub_0_in_QPR[] = {
|
|
ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16, ARM_D16_D17_D18, ARM_D18_D19_D20, ARM_D20_D21_D22, ARM_D22_D23_D24, ARM_D24_D25_D26, ARM_D26_D27_D28, ARM_D28_D29_D30,
|
|
};
|
|
|
|
// DTriple_with_qsub_0_in_QPR Bit set.
|
|
static const uint8_t DTriple_with_qsub_0_in_QPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0xaa, 0xaa, 0x0a,
|
|
};
|
|
|
|
// DTriple_with_ssub_2 Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_2[] = {
|
|
ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15, ARM_D14_D15_D16,
|
|
};
|
|
|
|
// DTriple_with_ssub_2 Bit set.
|
|
static const uint8_t DTriple_with_ssub_2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x3f,
|
|
};
|
|
|
|
// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
|
|
ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17, ARM_D17_D18_D19, ARM_D19_D20_D21, ARM_D21_D22_D23, ARM_D23_D24_D25, ARM_D25_D26_D27, ARM_D27_D28_D29, ARM_D29_D30_D31,
|
|
};
|
|
|
|
// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
|
|
static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55, 0x55, 0x15,
|
|
};
|
|
|
|
// DTripleSpc_with_ssub_4 Register Class...
|
|
static const MCPhysReg DTripleSpc_with_ssub_4[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17,
|
|
};
|
|
|
|
// DTripleSpc_with_ssub_4 Bit set.
|
|
static const uint8_t DTripleSpc_with_ssub_4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
|
|
};
|
|
|
|
// DTriple_with_ssub_4 Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_4[] = {
|
|
ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9, ARM_D8_D9_D10, ARM_D9_D10_D11, ARM_D10_D11_D12, ARM_D11_D12_D13, ARM_D12_D13_D14, ARM_D13_D14_D15,
|
|
};
|
|
|
|
// DTriple_with_ssub_4 Bit set.
|
|
static const uint8_t DTriple_with_ssub_4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0x1f,
|
|
};
|
|
|
|
// DTripleSpc_with_ssub_8 Register Class...
|
|
static const MCPhysReg DTripleSpc_with_ssub_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15,
|
|
};
|
|
|
|
// DTripleSpc_with_ssub_8 Bit set.
|
|
static const uint8_t DTripleSpc_with_ssub_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01,
|
|
};
|
|
|
|
// DTripleSpc_with_dsub_0_in_DPR_8 Register Class...
|
|
static const MCPhysReg DTripleSpc_with_dsub_0_in_DPR_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11,
|
|
};
|
|
|
|
// DTripleSpc_with_dsub_0_in_DPR_8 Bit set.
|
|
static const uint8_t DTripleSpc_with_dsub_0_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
|
|
};
|
|
|
|
// DTriple_with_dsub_0_in_DPR_8 Register Class...
|
|
static const MCPhysReg DTriple_with_dsub_0_in_DPR_8[] = {
|
|
ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8, ARM_D7_D8_D9,
|
|
};
|
|
|
|
// DTriple_with_dsub_0_in_DPR_8 Bit set.
|
|
static const uint8_t DTriple_with_dsub_0_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7f,
|
|
};
|
|
|
|
// DTriple_with_qsub_0_in_MQPR Register Class...
|
|
static const MCPhysReg DTriple_with_qsub_0_in_MQPR[] = {
|
|
ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14, ARM_D14_D15_D16,
|
|
};
|
|
|
|
// DTriple_with_qsub_0_in_MQPR Bit set.
|
|
static const uint8_t DTriple_with_qsub_0_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x2a,
|
|
};
|
|
|
|
// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
|
|
ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15, ARM_D15_D16_D17,
|
|
};
|
|
|
|
// DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
|
|
static const uint8_t DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x55,
|
|
};
|
|
|
|
// DTriple_with_dsub_1_in_DPR_8 Register Class...
|
|
static const MCPhysReg DTriple_with_dsub_1_in_DPR_8[] = {
|
|
ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7, ARM_D6_D7_D8,
|
|
};
|
|
|
|
// DTriple_with_dsub_1_in_DPR_8 Bit set.
|
|
static const uint8_t DTriple_with_dsub_1_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x3f,
|
|
};
|
|
|
|
// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
|
|
ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9, ARM_D9_D10_D11, ARM_D11_D12_D13, ARM_D13_D14_D15,
|
|
};
|
|
|
|
// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
|
|
static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0x15,
|
|
};
|
|
|
|
// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR[] = {
|
|
ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8, ARM_D8_D9_D10, ARM_D10_D11_D12, ARM_D12_D13_D14,
|
|
};
|
|
|
|
// DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR Bit set.
|
|
static const uint8_t DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xaa, 0x0a,
|
|
};
|
|
|
|
// DTripleSpc_with_dsub_2_in_DPR_8 Register Class...
|
|
static const MCPhysReg DTripleSpc_with_dsub_2_in_DPR_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9,
|
|
};
|
|
|
|
// DTripleSpc_with_dsub_2_in_DPR_8 Bit set.
|
|
static const uint8_t DTripleSpc_with_dsub_2_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
|
|
};
|
|
|
|
// DTriple_with_dsub_2_in_DPR_8 Register Class...
|
|
static const MCPhysReg DTriple_with_dsub_2_in_DPR_8[] = {
|
|
ARM_D0_D1_D2, ARM_D1_D2_D3, ARM_D2_D3_D4, ARM_D3_D4_D5, ARM_D4_D5_D6, ARM_D5_D6_D7,
|
|
};
|
|
|
|
// DTriple_with_dsub_2_in_DPR_8 Bit set.
|
|
static const uint8_t DTriple_with_dsub_2_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x1f,
|
|
};
|
|
|
|
// DTripleSpc_with_dsub_4_in_DPR_8 Register Class...
|
|
static const MCPhysReg DTripleSpc_with_dsub_4_in_DPR_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7,
|
|
};
|
|
|
|
// DTripleSpc_with_dsub_4_in_DPR_8 Bit set.
|
|
static const uint8_t DTripleSpc_with_dsub_4_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
|
|
};
|
|
|
|
// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
|
|
static const MCPhysReg DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
|
|
ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7, ARM_D7_D8_D9,
|
|
};
|
|
|
|
// DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
|
|
static const uint8_t DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55,
|
|
};
|
|
|
|
// DTriple_with_qsub_0_in_QPR_8 Register Class...
|
|
static const MCPhysReg DTriple_with_qsub_0_in_QPR_8[] = {
|
|
ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6, ARM_D6_D7_D8,
|
|
};
|
|
|
|
// DTriple_with_qsub_0_in_QPR_8 Bit set.
|
|
static const uint8_t DTriple_with_qsub_0_in_QPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x2a,
|
|
};
|
|
|
|
// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Register Class...
|
|
static const MCPhysReg DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR[] = {
|
|
ARM_D0_D1_D2, ARM_D2_D3_D4, ARM_D4_D5_D6,
|
|
};
|
|
|
|
// DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR Bit set.
|
|
static const uint8_t DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0a,
|
|
};
|
|
|
|
// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
|
|
static const MCPhysReg DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
|
|
ARM_D1_D2_D3, ARM_D3_D4_D5, ARM_D5_D6_D7,
|
|
};
|
|
|
|
// DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
|
|
static const uint8_t DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x15,
|
|
};
|
|
|
|
// DQuadSpc Register Class...
|
|
static const MCPhysReg DQuadSpc[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19, ARM_D16_D18_D20, ARM_D17_D19_D21, ARM_D18_D20_D22, ARM_D19_D21_D23, ARM_D20_D22_D24, ARM_D21_D23_D25, ARM_D22_D24_D26, ARM_D23_D25_D27, ARM_D24_D26_D28, ARM_D25_D27_D29, ARM_D26_D28_D30, ARM_D27_D29_D31,
|
|
};
|
|
|
|
// DQuadSpc Bit set.
|
|
static const uint8_t DQuadSpcBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0xff, 0xff, 0x01,
|
|
};
|
|
|
|
// DQuadSpc_with_ssub_0 Register Class...
|
|
static const MCPhysReg DQuadSpc_with_ssub_0[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17, ARM_D14_D16_D18, ARM_D15_D17_D19,
|
|
};
|
|
|
|
// DQuadSpc_with_ssub_0 Bit set.
|
|
static const uint8_t DQuadSpc_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x1f,
|
|
};
|
|
|
|
// DQuadSpc_with_ssub_4 Register Class...
|
|
static const MCPhysReg DQuadSpc_with_ssub_4[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15, ARM_D12_D14_D16, ARM_D13_D15_D17,
|
|
};
|
|
|
|
// DQuadSpc_with_ssub_4 Bit set.
|
|
static const uint8_t DQuadSpc_with_ssub_4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x07,
|
|
};
|
|
|
|
// DQuadSpc_with_ssub_8 Register Class...
|
|
static const MCPhysReg DQuadSpc_with_ssub_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11, ARM_D8_D10_D12, ARM_D9_D11_D13, ARM_D10_D12_D14, ARM_D11_D13_D15,
|
|
};
|
|
|
|
// DQuadSpc_with_ssub_8 Bit set.
|
|
static const uint8_t DQuadSpc_with_ssub_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xff, 0x01,
|
|
};
|
|
|
|
// DQuadSpc_with_dsub_0_in_DPR_8 Register Class...
|
|
static const MCPhysReg DQuadSpc_with_dsub_0_in_DPR_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9, ARM_D6_D8_D10, ARM_D7_D9_D11,
|
|
};
|
|
|
|
// DQuadSpc_with_dsub_0_in_DPR_8 Bit set.
|
|
static const uint8_t DQuadSpc_with_dsub_0_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x1f,
|
|
};
|
|
|
|
// DQuadSpc_with_dsub_2_in_DPR_8 Register Class...
|
|
static const MCPhysReg DQuadSpc_with_dsub_2_in_DPR_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7, ARM_D4_D6_D8, ARM_D5_D7_D9,
|
|
};
|
|
|
|
// DQuadSpc_with_dsub_2_in_DPR_8 Bit set.
|
|
static const uint8_t DQuadSpc_with_dsub_2_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x07,
|
|
};
|
|
|
|
// DQuadSpc_with_dsub_4_in_DPR_8 Register Class...
|
|
static const MCPhysReg DQuadSpc_with_dsub_4_in_DPR_8[] = {
|
|
ARM_D0_D2_D4, ARM_D1_D3_D5, ARM_D2_D4_D6, ARM_D3_D5_D7,
|
|
};
|
|
|
|
// DQuadSpc_with_dsub_4_in_DPR_8 Bit set.
|
|
static const uint8_t DQuadSpc_with_dsub_4_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01,
|
|
};
|
|
|
|
// DQuad Register Class...
|
|
static const MCPhysReg DQuad[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18, ARM_Q8_Q9, ARM_D17_D18_D19_D20, ARM_Q9_Q10, ARM_D19_D20_D21_D22, ARM_Q10_Q11, ARM_D21_D22_D23_D24, ARM_Q11_Q12, ARM_D23_D24_D25_D26, ARM_Q12_Q13, ARM_D25_D26_D27_D28, ARM_Q13_Q14, ARM_D27_D28_D29_D30, ARM_Q14_Q15,
|
|
};
|
|
|
|
// DQuad Bit set.
|
|
static const uint8_t DQuadBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff,
|
|
};
|
|
|
|
// DQuad_with_ssub_0 Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_0[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8, ARM_D15_D16_D17_D18,
|
|
};
|
|
|
|
// DQuad_with_ssub_0 Bit set.
|
|
static const uint8_t DQuad_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
|
};
|
|
|
|
// DQuad_with_ssub_2 Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_2[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16, ARM_Q7_Q8,
|
|
};
|
|
|
|
// DQuad_with_ssub_2 Bit set.
|
|
static const uint8_t DQuad_with_ssub_2Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
|
|
};
|
|
|
|
// QQPR Register Class...
|
|
static const MCPhysReg QQPR[] = {
|
|
ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8, ARM_Q8_Q9, ARM_Q9_Q10, ARM_Q10_Q11, ARM_Q11_Q12, ARM_Q12_Q13, ARM_Q13_Q14, ARM_Q14_Q15,
|
|
};
|
|
|
|
// QQPR Bit set.
|
|
static const uint8_t QQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xff, 0x07,
|
|
};
|
|
|
|
// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
|
|
ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18, ARM_D17_D18_D19_D20, ARM_D19_D20_D21_D22, ARM_D21_D22_D23_D24, ARM_D23_D24_D25_D26, ARM_D25_D26_D27_D28, ARM_D27_D28_D29_D30,
|
|
};
|
|
|
|
// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
|
|
static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0xff,
|
|
};
|
|
|
|
// DQuad_with_ssub_4 Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_4[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7, ARM_D13_D14_D15_D16,
|
|
};
|
|
|
|
// DQuad_with_ssub_4 Bit set.
|
|
static const uint8_t DQuad_with_ssub_4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
|
|
};
|
|
|
|
// DQuad_with_ssub_6 Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_6[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10, ARM_Q4_Q5, ARM_D9_D10_D11_D12, ARM_Q5_Q6, ARM_D11_D12_D13_D14, ARM_Q6_Q7,
|
|
};
|
|
|
|
// DQuad_with_ssub_6 Bit set.
|
|
static const uint8_t DQuad_with_ssub_6Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
|
|
};
|
|
|
|
// DQuad_with_dsub_0_in_DPR_8 Register Class...
|
|
static const MCPhysReg DQuad_with_dsub_0_in_DPR_8[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4, ARM_D7_D8_D9_D10,
|
|
};
|
|
|
|
// DQuad_with_dsub_0_in_DPR_8 Bit set.
|
|
static const uint8_t DQuad_with_dsub_0_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
|
|
};
|
|
|
|
// DQuad_with_qsub_0_in_MQPR Register Class...
|
|
static const MCPhysReg DQuad_with_qsub_0_in_MQPR[] = {
|
|
ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7, ARM_Q7_Q8,
|
|
};
|
|
|
|
// DQuad_with_qsub_0_in_MQPR Bit set.
|
|
static const uint8_t DQuad_with_qsub_0_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x0f,
|
|
};
|
|
|
|
// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR[] = {
|
|
ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16, ARM_D15_D16_D17_D18,
|
|
};
|
|
|
|
// DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR Bit set.
|
|
static const uint8_t DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x03,
|
|
};
|
|
|
|
// DQuad_with_dsub_1_in_DPR_8 Register Class...
|
|
static const MCPhysReg DQuad_with_dsub_1_in_DPR_8[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8, ARM_Q3_Q4,
|
|
};
|
|
|
|
// DQuad_with_dsub_1_in_DPR_8 Bit set.
|
|
static const uint8_t DQuad_with_dsub_1_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
|
|
};
|
|
|
|
// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
|
|
ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14, ARM_D13_D14_D15_D16,
|
|
};
|
|
|
|
// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
|
|
static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc, 0x01,
|
|
};
|
|
|
|
// MQQPR Register Class...
|
|
static const MCPhysReg MQQPR[] = {
|
|
ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4, ARM_Q4_Q5, ARM_Q5_Q6, ARM_Q6_Q7,
|
|
};
|
|
|
|
// MQQPR Bit set.
|
|
static const uint8_t MQQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0x07,
|
|
};
|
|
|
|
// DQuad_with_dsub_2_in_DPR_8 Register Class...
|
|
static const MCPhysReg DQuad_with_dsub_2_in_DPR_8[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3, ARM_D5_D6_D7_D8,
|
|
};
|
|
|
|
// DQuad_with_dsub_2_in_DPR_8 Bit set.
|
|
static const uint8_t DQuad_with_dsub_2_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
|
|
};
|
|
|
|
// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
|
|
ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10, ARM_D9_D10_D11_D12, ARM_D11_D12_D13_D14,
|
|
};
|
|
|
|
// DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
|
|
static const uint8_t DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfc,
|
|
};
|
|
|
|
// DQuad_with_dsub_3_in_DPR_8 Register Class...
|
|
static const MCPhysReg DQuad_with_dsub_3_in_DPR_8[] = {
|
|
ARM_Q0_Q1, ARM_D1_D2_D3_D4, ARM_Q1_Q2, ARM_D3_D4_D5_D6, ARM_Q2_Q3,
|
|
};
|
|
|
|
// DQuad_with_dsub_3_in_DPR_8 Bit set.
|
|
static const uint8_t DQuad_with_dsub_3_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
|
|
};
|
|
|
|
// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
|
|
static const MCPhysReg DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
|
|
ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8, ARM_D7_D8_D9_D10,
|
|
};
|
|
|
|
// DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
|
|
static const uint8_t DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c,
|
|
};
|
|
|
|
// DQuad_with_qsub_0_in_QPR_8 Register Class...
|
|
static const MCPhysReg DQuad_with_qsub_0_in_QPR_8[] = {
|
|
ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3, ARM_Q3_Q4,
|
|
};
|
|
|
|
// DQuad_with_qsub_0_in_QPR_8 Bit set.
|
|
static const uint8_t DQuad_with_qsub_0_in_QPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0,
|
|
};
|
|
|
|
// DQuad_with_qsub_1_in_QPR_8 Register Class...
|
|
static const MCPhysReg DQuad_with_qsub_1_in_QPR_8[] = {
|
|
ARM_Q0_Q1, ARM_Q1_Q2, ARM_Q2_Q3,
|
|
};
|
|
|
|
// DQuad_with_qsub_1_in_QPR_8 Bit set.
|
|
static const uint8_t DQuad_with_qsub_1_in_QPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70,
|
|
};
|
|
|
|
// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Register Class...
|
|
static const MCPhysReg DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8[] = {
|
|
ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6, ARM_D5_D6_D7_D8,
|
|
};
|
|
|
|
// DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8 Bit set.
|
|
static const uint8_t DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1c,
|
|
};
|
|
|
|
// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Register Class...
|
|
static const MCPhysReg DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR[] = {
|
|
ARM_D1_D2_D3_D4, ARM_D3_D4_D5_D6,
|
|
};
|
|
|
|
// DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR Bit set.
|
|
static const uint8_t DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c,
|
|
};
|
|
|
|
// QQQQPR Register Class...
|
|
static const MCPhysReg QQQQPR[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10, ARM_Q8_Q9_Q10_Q11, ARM_Q9_Q10_Q11_Q12, ARM_Q10_Q11_Q12_Q13, ARM_Q11_Q12_Q13_Q14, ARM_Q12_Q13_Q14_Q15,
|
|
};
|
|
|
|
// QQQQPR Bit set.
|
|
static const uint8_t QQQQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0xff,
|
|
};
|
|
|
|
// QQQQPR_with_ssub_0 Register Class...
|
|
static const MCPhysReg QQQQPR_with_ssub_0[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9, ARM_Q7_Q8_Q9_Q10,
|
|
};
|
|
|
|
// QQQQPR_with_ssub_0 Bit set.
|
|
static const uint8_t QQQQPR_with_ssub_0Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x07,
|
|
};
|
|
|
|
// QQQQPR_with_ssub_4 Register Class...
|
|
static const MCPhysReg QQQQPR_with_ssub_4[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8, ARM_Q6_Q7_Q8_Q9,
|
|
};
|
|
|
|
// QQQQPR_with_ssub_4 Bit set.
|
|
static const uint8_t QQQQPR_with_ssub_4Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x03,
|
|
};
|
|
|
|
// QQQQPR_with_ssub_8 Register Class...
|
|
static const MCPhysReg QQQQPR_with_ssub_8[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7, ARM_Q5_Q6_Q7_Q8,
|
|
};
|
|
|
|
// QQQQPR_with_ssub_8 Bit set.
|
|
static const uint8_t QQQQPR_with_ssub_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8, 0x01,
|
|
};
|
|
|
|
// MQQQQPR Register Class...
|
|
static const MCPhysReg MQQQQPR[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6, ARM_Q4_Q5_Q6_Q7,
|
|
};
|
|
|
|
// MQQQQPR Bit set.
|
|
static const uint8_t MQQQQPRBits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf8,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_0_in_DPR_8 Register Class...
|
|
static const MCPhysReg MQQQQPR_with_dsub_0_in_DPR_8[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5, ARM_Q3_Q4_Q5_Q6,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_0_in_DPR_8 Bit set.
|
|
static const uint8_t MQQQQPR_with_dsub_0_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x78,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_2_in_DPR_8 Register Class...
|
|
static const MCPhysReg MQQQQPR_with_dsub_2_in_DPR_8[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4, ARM_Q2_Q3_Q4_Q5,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_2_in_DPR_8 Bit set.
|
|
static const uint8_t MQQQQPR_with_dsub_2_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x38,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_4_in_DPR_8 Register Class...
|
|
static const MCPhysReg MQQQQPR_with_dsub_4_in_DPR_8[] = {
|
|
ARM_Q0_Q1_Q2_Q3, ARM_Q1_Q2_Q3_Q4,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_4_in_DPR_8 Bit set.
|
|
static const uint8_t MQQQQPR_with_dsub_4_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_6_in_DPR_8 Register Class...
|
|
static const MCPhysReg MQQQQPR_with_dsub_6_in_DPR_8[] = {
|
|
ARM_Q0_Q1_Q2_Q3,
|
|
};
|
|
|
|
// MQQQQPR_with_dsub_6_in_DPR_8 Bit set.
|
|
static const uint8_t MQQQQPR_with_dsub_6_in_DPR_8Bits[] = {
|
|
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08,
|
|
};
|
|
|
|
static const MCRegisterClass ARMMCRegisterClasses[] = {
|
|
{ HPR, HPRBits, sizeof(HPRBits) },
|
|
{ FPWithVPR, FPWithVPRBits, sizeof(FPWithVPRBits) },
|
|
{ SPR, SPRBits, sizeof(SPRBits) },
|
|
{ FPWithVPR_with_ssub_0, FPWithVPR_with_ssub_0Bits, sizeof(FPWithVPR_with_ssub_0Bits) },
|
|
{ GPR, GPRBits, sizeof(GPRBits) },
|
|
{ GPRwithAPSR, GPRwithAPSRBits, sizeof(GPRwithAPSRBits) },
|
|
{ GPRwithZR, GPRwithZRBits, sizeof(GPRwithZRBits) },
|
|
{ SPR_8, SPR_8Bits, sizeof(SPR_8Bits) },
|
|
{ GPRnopc, GPRnopcBits, sizeof(GPRnopcBits) },
|
|
{ GPRnosp, GPRnospBits, sizeof(GPRnospBits) },
|
|
{ GPRwithAPSR_NZCVnosp, GPRwithAPSR_NZCVnospBits, sizeof(GPRwithAPSR_NZCVnospBits) },
|
|
{ GPRwithAPSRnosp, GPRwithAPSRnospBits, sizeof(GPRwithAPSRnospBits) },
|
|
{ GPRwithZRnosp, GPRwithZRnospBits, sizeof(GPRwithZRnospBits) },
|
|
{ GPRnoip, GPRnoipBits, sizeof(GPRnoipBits) },
|
|
{ rGPR, rGPRBits, sizeof(rGPRBits) },
|
|
{ GPRnoip_and_GPRnopc, GPRnoip_and_GPRnopcBits, sizeof(GPRnoip_and_GPRnopcBits) },
|
|
{ GPRnoip_and_GPRnosp, GPRnoip_and_GPRnospBits, sizeof(GPRnoip_and_GPRnospBits) },
|
|
{ GPRnoip_and_GPRwithAPSR_NZCVnosp, GPRnoip_and_GPRwithAPSR_NZCVnospBits, sizeof(GPRnoip_and_GPRwithAPSR_NZCVnospBits) },
|
|
{ tGPRwithpc, tGPRwithpcBits, sizeof(tGPRwithpcBits) },
|
|
{ FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8, FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits, sizeof(FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Bits) },
|
|
{ hGPR, hGPRBits, sizeof(hGPRBits) },
|
|
{ tGPR, tGPRBits, sizeof(tGPRBits) },
|
|
{ tGPREven, tGPREvenBits, sizeof(tGPREvenBits) },
|
|
{ GPRnopc_and_hGPR, GPRnopc_and_hGPRBits, sizeof(GPRnopc_and_hGPRBits) },
|
|
{ GPRnosp_and_hGPR, GPRnosp_and_hGPRBits, sizeof(GPRnosp_and_hGPRBits) },
|
|
{ GPRnoip_and_hGPR, GPRnoip_and_hGPRBits, sizeof(GPRnoip_and_hGPRBits) },
|
|
{ GPRnoip_and_tGPREven, GPRnoip_and_tGPREvenBits, sizeof(GPRnoip_and_tGPREvenBits) },
|
|
{ GPRnosp_and_GPRnopc_and_hGPR, GPRnosp_and_GPRnopc_and_hGPRBits, sizeof(GPRnosp_and_GPRnopc_and_hGPRBits) },
|
|
{ tGPROdd, tGPROddBits, sizeof(tGPROddBits) },
|
|
{ GPRnopc_and_GPRnoip_and_hGPR, GPRnopc_and_GPRnoip_and_hGPRBits, sizeof(GPRnopc_and_GPRnoip_and_hGPRBits) },
|
|
{ GPRnosp_and_GPRnoip_and_hGPR, GPRnosp_and_GPRnoip_and_hGPRBits, sizeof(GPRnosp_and_GPRnoip_and_hGPRBits) },
|
|
{ tcGPR, tcGPRBits, sizeof(tcGPRBits) },
|
|
{ GPRnoip_and_tcGPR, GPRnoip_and_tcGPRBits, sizeof(GPRnoip_and_tcGPRBits) },
|
|
{ GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPR, GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits, sizeof(GPRnosp_and_GPRnopc_and_GPRnoip_and_hGPRBits) },
|
|
{ hGPR_and_tGPREven, hGPR_and_tGPREvenBits, sizeof(hGPR_and_tGPREvenBits) },
|
|
{ tGPR_and_tGPREven, tGPR_and_tGPREvenBits, sizeof(tGPR_and_tGPREvenBits) },
|
|
{ tGPR_and_tGPROdd, tGPR_and_tGPROddBits, sizeof(tGPR_and_tGPROddBits) },
|
|
{ tGPREven_and_tcGPR, tGPREven_and_tcGPRBits, sizeof(tGPREven_and_tcGPRBits) },
|
|
{ hGPR_and_GPRnoip_and_tGPREven, hGPR_and_GPRnoip_and_tGPREvenBits, sizeof(hGPR_and_GPRnoip_and_tGPREvenBits) },
|
|
{ hGPR_and_tGPROdd, hGPR_and_tGPROddBits, sizeof(hGPR_and_tGPROddBits) },
|
|
{ tGPREven_and_GPRnoip_and_tcGPR, tGPREven_and_GPRnoip_and_tcGPRBits, sizeof(tGPREven_and_GPRnoip_and_tcGPRBits) },
|
|
{ tGPROdd_and_tcGPR, tGPROdd_and_tcGPRBits, sizeof(tGPROdd_and_tcGPRBits) },
|
|
{ CCR, CCRBits, sizeof(CCRBits) },
|
|
{ FPCXTRegs, FPCXTRegsBits, sizeof(FPCXTRegsBits) },
|
|
{ GPRlr, GPRlrBits, sizeof(GPRlrBits) },
|
|
{ GPRsp, GPRspBits, sizeof(GPRspBits) },
|
|
{ VCCR, VCCRBits, sizeof(VCCRBits) },
|
|
{ cl_FPSCR_NZCV, cl_FPSCR_NZCVBits, sizeof(cl_FPSCR_NZCVBits) },
|
|
{ hGPR_and_tGPRwithpc, hGPR_and_tGPRwithpcBits, sizeof(hGPR_and_tGPRwithpcBits) },
|
|
{ hGPR_and_tcGPR, hGPR_and_tcGPRBits, sizeof(hGPR_and_tcGPRBits) },
|
|
{ DPR, DPRBits, sizeof(DPRBits) },
|
|
{ DPR_VFP2, DPR_VFP2Bits, sizeof(DPR_VFP2Bits) },
|
|
{ DPR_8, DPR_8Bits, sizeof(DPR_8Bits) },
|
|
{ GPRPair, GPRPairBits, sizeof(GPRPairBits) },
|
|
{ GPRPairnosp, GPRPairnospBits, sizeof(GPRPairnospBits) },
|
|
{ GPRPair_with_gsub_0_in_tGPR, GPRPair_with_gsub_0_in_tGPRBits, sizeof(GPRPair_with_gsub_0_in_tGPRBits) },
|
|
{ GPRPair_with_gsub_0_in_hGPR, GPRPair_with_gsub_0_in_hGPRBits, sizeof(GPRPair_with_gsub_0_in_hGPRBits) },
|
|
{ GPRPair_with_gsub_0_in_tcGPR, GPRPair_with_gsub_0_in_tcGPRBits, sizeof(GPRPair_with_gsub_0_in_tcGPRBits) },
|
|
{ GPRPair_with_gsub_1_in_tcGPR, GPRPair_with_gsub_1_in_tcGPRBits, sizeof(GPRPair_with_gsub_1_in_tcGPRBits) },
|
|
{ GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPR, GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits, sizeof(GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRBits) },
|
|
{ GPRPair_with_gsub_1_in_GPRsp, GPRPair_with_gsub_1_in_GPRspBits, sizeof(GPRPair_with_gsub_1_in_GPRspBits) },
|
|
{ DPairSpc, DPairSpcBits, sizeof(DPairSpcBits) },
|
|
{ DPairSpc_with_ssub_0, DPairSpc_with_ssub_0Bits, sizeof(DPairSpc_with_ssub_0Bits) },
|
|
{ DPairSpc_with_ssub_4, DPairSpc_with_ssub_4Bits, sizeof(DPairSpc_with_ssub_4Bits) },
|
|
{ DPairSpc_with_dsub_0_in_DPR_8, DPairSpc_with_dsub_0_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_0_in_DPR_8Bits) },
|
|
{ DPairSpc_with_dsub_2_in_DPR_8, DPairSpc_with_dsub_2_in_DPR_8Bits, sizeof(DPairSpc_with_dsub_2_in_DPR_8Bits) },
|
|
{ DPair, DPairBits, sizeof(DPairBits) },
|
|
{ DPair_with_ssub_0, DPair_with_ssub_0Bits, sizeof(DPair_with_ssub_0Bits) },
|
|
{ QPR, QPRBits, sizeof(QPRBits) },
|
|
{ DPair_with_ssub_2, DPair_with_ssub_2Bits, sizeof(DPair_with_ssub_2Bits) },
|
|
{ DPair_with_dsub_0_in_DPR_8, DPair_with_dsub_0_in_DPR_8Bits, sizeof(DPair_with_dsub_0_in_DPR_8Bits) },
|
|
{ MQPR, MQPRBits, sizeof(MQPRBits) },
|
|
{ QPR_VFP2, QPR_VFP2Bits, sizeof(QPR_VFP2Bits) },
|
|
{ DPair_with_dsub_1_in_DPR_8, DPair_with_dsub_1_in_DPR_8Bits, sizeof(DPair_with_dsub_1_in_DPR_8Bits) },
|
|
{ QPR_8, QPR_8Bits, sizeof(QPR_8Bits) },
|
|
{ DTriple, DTripleBits, sizeof(DTripleBits) },
|
|
{ DTripleSpc, DTripleSpcBits, sizeof(DTripleSpcBits) },
|
|
{ DTripleSpc_with_ssub_0, DTripleSpc_with_ssub_0Bits, sizeof(DTripleSpc_with_ssub_0Bits) },
|
|
{ DTriple_with_ssub_0, DTriple_with_ssub_0Bits, sizeof(DTriple_with_ssub_0Bits) },
|
|
{ DTriple_with_qsub_0_in_QPR, DTriple_with_qsub_0_in_QPRBits, sizeof(DTriple_with_qsub_0_in_QPRBits) },
|
|
{ DTriple_with_ssub_2, DTriple_with_ssub_2Bits, sizeof(DTriple_with_ssub_2Bits) },
|
|
{ DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
|
|
{ DTripleSpc_with_ssub_4, DTripleSpc_with_ssub_4Bits, sizeof(DTripleSpc_with_ssub_4Bits) },
|
|
{ DTriple_with_ssub_4, DTriple_with_ssub_4Bits, sizeof(DTriple_with_ssub_4Bits) },
|
|
{ DTripleSpc_with_ssub_8, DTripleSpc_with_ssub_8Bits, sizeof(DTripleSpc_with_ssub_8Bits) },
|
|
{ DTripleSpc_with_dsub_0_in_DPR_8, DTripleSpc_with_dsub_0_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_0_in_DPR_8Bits) },
|
|
{ DTriple_with_dsub_0_in_DPR_8, DTriple_with_dsub_0_in_DPR_8Bits, sizeof(DTriple_with_dsub_0_in_DPR_8Bits) },
|
|
{ DTriple_with_qsub_0_in_MQPR, DTriple_with_qsub_0_in_MQPRBits, sizeof(DTriple_with_qsub_0_in_MQPRBits) },
|
|
{ DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
|
|
{ DTriple_with_dsub_1_in_DPR_8, DTriple_with_dsub_1_in_DPR_8Bits, sizeof(DTriple_with_dsub_1_in_DPR_8Bits) },
|
|
{ DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
|
|
{ DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits, sizeof(DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRBits) },
|
|
{ DTripleSpc_with_dsub_2_in_DPR_8, DTripleSpc_with_dsub_2_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_2_in_DPR_8Bits) },
|
|
{ DTriple_with_dsub_2_in_DPR_8, DTriple_with_dsub_2_in_DPR_8Bits, sizeof(DTriple_with_dsub_2_in_DPR_8Bits) },
|
|
{ DTripleSpc_with_dsub_4_in_DPR_8, DTripleSpc_with_dsub_4_in_DPR_8Bits, sizeof(DTripleSpc_with_dsub_4_in_DPR_8Bits) },
|
|
{ DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
|
|
{ DTriple_with_qsub_0_in_QPR_8, DTriple_with_qsub_0_in_QPR_8Bits, sizeof(DTriple_with_qsub_0_in_QPR_8Bits) },
|
|
{ DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPR, DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits, sizeof(DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRBits) },
|
|
{ DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) },
|
|
{ DQuadSpc, DQuadSpcBits, sizeof(DQuadSpcBits) },
|
|
{ DQuadSpc_with_ssub_0, DQuadSpc_with_ssub_0Bits, sizeof(DQuadSpc_with_ssub_0Bits) },
|
|
{ DQuadSpc_with_ssub_4, DQuadSpc_with_ssub_4Bits, sizeof(DQuadSpc_with_ssub_4Bits) },
|
|
{ DQuadSpc_with_ssub_8, DQuadSpc_with_ssub_8Bits, sizeof(DQuadSpc_with_ssub_8Bits) },
|
|
{ DQuadSpc_with_dsub_0_in_DPR_8, DQuadSpc_with_dsub_0_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_0_in_DPR_8Bits) },
|
|
{ DQuadSpc_with_dsub_2_in_DPR_8, DQuadSpc_with_dsub_2_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_2_in_DPR_8Bits) },
|
|
{ DQuadSpc_with_dsub_4_in_DPR_8, DQuadSpc_with_dsub_4_in_DPR_8Bits, sizeof(DQuadSpc_with_dsub_4_in_DPR_8Bits) },
|
|
{ DQuad, DQuadBits, sizeof(DQuadBits) },
|
|
{ DQuad_with_ssub_0, DQuad_with_ssub_0Bits, sizeof(DQuad_with_ssub_0Bits) },
|
|
{ DQuad_with_ssub_2, DQuad_with_ssub_2Bits, sizeof(DQuad_with_ssub_2Bits) },
|
|
{ QQPR, QQPRBits, sizeof(QQPRBits) },
|
|
{ DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
|
|
{ DQuad_with_ssub_4, DQuad_with_ssub_4Bits, sizeof(DQuad_with_ssub_4Bits) },
|
|
{ DQuad_with_ssub_6, DQuad_with_ssub_6Bits, sizeof(DQuad_with_ssub_6Bits) },
|
|
{ DQuad_with_dsub_0_in_DPR_8, DQuad_with_dsub_0_in_DPR_8Bits, sizeof(DQuad_with_dsub_0_in_DPR_8Bits) },
|
|
{ DQuad_with_qsub_0_in_MQPR, DQuad_with_qsub_0_in_MQPRBits, sizeof(DQuad_with_qsub_0_in_MQPRBits) },
|
|
{ DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR, DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits, sizeof(DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRBits) },
|
|
{ DQuad_with_dsub_1_in_DPR_8, DQuad_with_dsub_1_in_DPR_8Bits, sizeof(DQuad_with_dsub_1_in_DPR_8Bits) },
|
|
{ DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
|
|
{ MQQPR, MQQPRBits, sizeof(MQQPRBits) },
|
|
{ DQuad_with_dsub_2_in_DPR_8, DQuad_with_dsub_2_in_DPR_8Bits, sizeof(DQuad_with_dsub_2_in_DPR_8Bits) },
|
|
{ DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
|
|
{ DQuad_with_dsub_3_in_DPR_8, DQuad_with_dsub_3_in_DPR_8Bits, sizeof(DQuad_with_dsub_3_in_DPR_8Bits) },
|
|
{ DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
|
|
{ DQuad_with_qsub_0_in_QPR_8, DQuad_with_qsub_0_in_QPR_8Bits, sizeof(DQuad_with_qsub_0_in_QPR_8Bits) },
|
|
{ DQuad_with_qsub_1_in_QPR_8, DQuad_with_qsub_1_in_QPR_8Bits, sizeof(DQuad_with_qsub_1_in_QPR_8Bits) },
|
|
{ DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8, DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits, sizeof(DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Bits) },
|
|
{ DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPR, DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits, sizeof(DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRBits) },
|
|
{ QQQQPR, QQQQPRBits, sizeof(QQQQPRBits) },
|
|
{ QQQQPR_with_ssub_0, QQQQPR_with_ssub_0Bits, sizeof(QQQQPR_with_ssub_0Bits) },
|
|
{ QQQQPR_with_ssub_4, QQQQPR_with_ssub_4Bits, sizeof(QQQQPR_with_ssub_4Bits) },
|
|
{ QQQQPR_with_ssub_8, QQQQPR_with_ssub_8Bits, sizeof(QQQQPR_with_ssub_8Bits) },
|
|
{ MQQQQPR, MQQQQPRBits, sizeof(MQQQQPRBits) },
|
|
{ MQQQQPR_with_dsub_0_in_DPR_8, MQQQQPR_with_dsub_0_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_0_in_DPR_8Bits) },
|
|
{ MQQQQPR_with_dsub_2_in_DPR_8, MQQQQPR_with_dsub_2_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_2_in_DPR_8Bits) },
|
|
{ MQQQQPR_with_dsub_4_in_DPR_8, MQQQQPR_with_dsub_4_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_4_in_DPR_8Bits) },
|
|
{ MQQQQPR_with_dsub_6_in_DPR_8, MQQQQPR_with_dsub_6_in_DPR_8Bits, sizeof(MQQQQPR_with_dsub_6_in_DPR_8Bits) },
|
|
};
|
|
|
|
static const uint16_t ARMRegEncodingTable[] = {
|
|
0,
|
|
15,
|
|
15,
|
|
0,
|
|
14,
|
|
15,
|
|
8,
|
|
9,
|
|
3,
|
|
3,
|
|
2,
|
|
0,
|
|
4,
|
|
14,
|
|
15,
|
|
12,
|
|
13,
|
|
2,
|
|
32,
|
|
15,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
10,
|
|
7,
|
|
6,
|
|
5,
|
|
13,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
30,
|
|
31,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
0,
|
|
2,
|
|
4,
|
|
6,
|
|
8,
|
|
10,
|
|
12,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
28,
|
|
29,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
26,
|
|
27,
|
|
0,
|
|
1,
|
|
2,
|
|
3,
|
|
4,
|
|
5,
|
|
6,
|
|
7,
|
|
8,
|
|
9,
|
|
10,
|
|
11,
|
|
12,
|
|
13,
|
|
14,
|
|
15,
|
|
16,
|
|
17,
|
|
18,
|
|
19,
|
|
20,
|
|
21,
|
|
22,
|
|
23,
|
|
24,
|
|
25,
|
|
1,
|
|
3,
|
|
5,
|
|
7,
|
|
9,
|
|
11,
|
|
13,
|
|
15,
|
|
17,
|
|
19,
|
|
21,
|
|
23,
|
|
25,
|
|
27,
|
|
29,
|
|
1,
|
|
3,
|
|
5,
|
|
7,
|
|
9,
|
|
11,
|
|
13,
|
|
15,
|
|
17,
|
|
19,
|
|
21,
|
|
23,
|
|
25,
|
|
27,
|
|
};
|
|
#endif // GET_REGINFO_MC_DESC
|
|
|
|
|
|
|