137 lines
3.6 KiB
C++
137 lines
3.6 KiB
C++
#include <n64/core/Cpu.hpp>
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#include <n64/core/mmio/MI.hpp>
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#include <n64/core/mmio/Interrupt.hpp>
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#include <util.hpp>
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namespace n64 {
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Cpu::Cpu() {
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#ifndef NDEBUG
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if (cs_open(CS_ARCH_MIPS, CS_MODE_MIPS64, &handle)) {
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util::panic("Could not initialize capstone!\n");
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}
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#endif
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}
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Cpu::~Cpu() {
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#ifndef NDEBUG
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cs_close(&handle);
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#endif
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}
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inline bool ShouldServiceInterrupt(Registers& regs) {
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bool interrupts_pending = (regs.cop0.status.im & regs.cop0.cause.interruptPending) != 0;
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bool interrupts_enabled = regs.cop0.status.ie == 1;
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bool currently_handling_exception = regs.cop0.status.exl == 1;
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bool currently_handling_error = regs.cop0.status.erl == 1;
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return interrupts_pending && interrupts_enabled &&
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!currently_handling_exception && !currently_handling_error;
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}
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inline void CheckCompareInterrupt(MI& mi, Registers& regs) {
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regs.cop0.count++;
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regs.cop0.count &= 0x1FFFFFFFF;
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if(regs.cop0.count == (u64)regs.cop0.compare << 1) {
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regs.cop0.cause.ip7 = 1;
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UpdateInterrupt(mi, regs);
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}
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}
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inline bool Is64BitAddressing(Cop0& cp0, u64 addr) {
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u8 region = (addr >> 62) & 3;
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switch(region) {
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case 0b00: return cp0.status.ux;
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case 0b01: return cp0.status.sx;
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case 0b11: return cp0.status.kx;
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default: return false;
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}
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}
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void FireException(Registers& regs, ExceptionCode code, int cop, s64 pc) {
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bool old_exl = regs.cop0.status.exl;
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if(!regs.cop0.status.exl) {
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if(regs.prevDelaySlot) { // TODO: cached value of delay_slot should be used, but Namco Museum breaks!
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regs.cop0.cause.branchDelay = true;
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pc -= 4;
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} else {
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regs.cop0.cause.branchDelay = false;
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}
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regs.cop0.EPC = pc;
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}
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regs.cop0.status.exl = true;
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regs.cop0.cause.copError = cop;
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regs.cop0.cause.exceptionCode = code;
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if(regs.cop0.status.bev) {
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util::panic("BEV bit set!\n");
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} else {
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switch(code) {
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case Interrupt: case TLBModification:
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case AddressErrorLoad: case AddressErrorStore:
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case InstructionBusError: case DataBusError:
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case Syscall: case Breakpoint:
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case ReservedInstruction: case CoprocessorUnusable:
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case Overflow: case Trap:
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case FloatingPointError: case Watch:
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regs.SetPC((s64)((s32)0x80000180));
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break;
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case TLBLoad: case TLBStore:
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if(old_exl || regs.cop0.tlbError == INVALID) {
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regs.SetPC((s64)((s32)0x80000180));
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} else if(Is64BitAddressing(regs.cop0, regs.cop0.badVaddr)) {
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regs.SetPC((s64)((s32)0x80000080));
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} else {
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regs.SetPC((s64)((s32)0x80000000));
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}
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break;
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default: util::panic("Unhandled exception! {}\n", code);
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}
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}
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}
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inline void HandleInterrupt(Registers& regs) {
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if(ShouldServiceInterrupt(regs)) {
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FireException(regs, ExceptionCode::Interrupt, 0, regs.pc);
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}
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}
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void Cpu::LogInstruction(u32 instruction) {
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#ifndef NDEBUG
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/*u8 code[4]{};
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u32 bswapped = be32toh(instruction);
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memcpy(code, &instruction, 4);
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count = cs_disasm(handle, code, 4, regs.pc, 0, &insn);
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if (count > 0) {
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for(auto j = 0; j < count; j++) {
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printf("%016lX:\t%s\t\t%s\n", insn[j].address, insn[j].mnemonic, insn[j].op_str);
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}
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cs_free(insn, count);
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} else {
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util::panic("Failed to disassemble {:08X}!", instruction);
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}*/
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#endif
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}
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void Cpu::Step(Mem& mem) {
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regs.gpr[0] = 0;
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regs.prevDelaySlot = regs.delaySlot;
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regs.delaySlot = false;
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CheckCompareInterrupt(mem.mmio.mi, regs);
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u32 instruction = mem.Read<u32>(regs, regs.pc, regs.pc);
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LogInstruction(instruction);
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HandleInterrupt(regs);
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regs.oldPC = regs.pc;
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regs.pc = regs.nextPC;
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regs.nextPC += 4;
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Exec(mem, instruction);
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}
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} |