112 lines
2.7 KiB
C++
112 lines
2.7 KiB
C++
#include <core/mmio/AI.hpp>
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#include <log.hpp>
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#include <core/Mem.hpp>
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#include <core/registers/Registers.hpp>
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#include <core/Audio.hpp>
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namespace n64 {
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void AI::Reset() {
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dmaEnable = 0;
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dacRate = 0;
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bitrate = 0;
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dmaCount = 0;
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dmaAddrCarry = false;
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cycles = 0;
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memset(dmaLen, 0, 2);
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memset(dmaAddr, 0, 2);
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dac = {44100, N64_CPU_FREQ / dac.freq, 16};
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}
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auto AI::Read(u32 addr) const -> u32 {
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if(addr == 0x0450000C) {
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u32 val = 0;
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val |= (dmaCount > 1);
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val |= 1 << 20;
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val |= 1 << 24;
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val |= (dmaEnable << 25);
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val |= (dmaCount > 0) << 30;
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val |= (dmaCount > 1) << 31;
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return val;
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}
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return dmaLen[0];
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}
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#define max(x, y) ((x) > (y) ? (x) : (y))
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void AI::Write(Mem& mem, Registers& regs, u32 addr, u32 val) {
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switch(addr) {
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case 0x04500000:
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if(dmaCount < 2) {
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dmaAddr[dmaCount] = val & 0xFFFFFF & ~7;
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}
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break;
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case 0x04500004: {
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u32 len = (val & 0x3FFFF) & ~7;
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if((dmaCount < 2) && len) {
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// if(dmaCount == 0) InterruptRaise(mem.mmio.mi, regs, Interrupt::AI);
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dmaLen[dmaCount] = len;
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dmaCount++;
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}
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} break;
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case 0x04500008:
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dmaEnable = val & 1;
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break;
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case 0x0450000C:
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InterruptLower(mem.mmio.mi, regs, Interrupt::AI);
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break;
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case 0x04500010: {
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u32 old_dac_freq = dac.freq;
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dacRate = val & 0x3FFF;
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dac.freq = max(1, N64_CPU_FREQ / 2 / (dacRate + 1)) * 1.037;
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dac.period = N64_CPU_FREQ / dac.freq;
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if(old_dac_freq != dac.freq) {
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AdjustSampleRate(dac.freq);
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}
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} break;
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case 0x04500014:
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bitrate = val & 0xF;
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dac.precision = bitrate + 1;
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break;
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default:
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Util::panic("Unhandled AI write at addr {:08X} with val {:08X}", addr, val);
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}
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}
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void AI::Step(Mem& mem, Registers& regs, int cpuCycles, float volumeL, float volumeR) {
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cycles += cpuCycles;
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while(cycles > dac.period) {
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if (dmaCount == 0) {
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return;
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}
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if(dmaLen[0] && dmaEnable) {u32 addrHi = ((dmaAddr[0] >> 13) + dmaAddrCarry) & 0x7FF;
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dmaAddr[0] = (addrHi << 13) | (dmaAddr[0] & 0x1FFF);
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u32 data = Util::ReadAccess<u32>(mem.mmio.rdp.rdram, dmaAddr[0] & RDRAM_DSIZE);
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s16 l = s16(data >> 16);
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s16 r = s16(data);
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if(volumeR > 0 && volumeL > 0) {
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PushSample((float) l / INT16_MAX, volumeL, (float) r / INT16_MAX, volumeR);
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}
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u32 addrLo = (dmaAddr[0] + 4) & 0x1FFF;
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dmaAddr[0] = (dmaAddr[0] & ~0x1FFF) | addrLo;
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dmaAddrCarry = addrLo == 0;
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dmaLen[0] -= 4;
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}
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if(!dmaLen[0]) {
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if(--dmaCount > 0) {
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InterruptRaise(mem.mmio.mi, regs, Interrupt::AI);
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dmaAddr[0] = dmaAddr[1];
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dmaLen[0] = dmaLen[1];
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}
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}
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cycles -= dac.period;
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}
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}
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}
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