name change

backend/Cargo.toml

@@ -0,0 +1,7 @@
+[package]
+name = "backend"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+proc-bitfield = "0.5.3"

backend/src/cpu/cpu.rs

@@ -0,0 +1,4 @@
+pub trait Cpu {
+    fn new() -> Self;
+    fn run(&mut self) -> Option<u64>;
+}

backend/src/cpu/mod.rs

@@ -0,0 +1,5 @@
+pub mod cpu;
+pub mod registers;
+
+pub use cpu::*;
+pub use registers::*;

backend/src/cpu/registers.rs

@@ -0,0 +1,117 @@
+pub struct Registers {
+    delay_slot: bool,
+    prev_delay_slot: bool,
+    pc: i64,
+    next_pc: i64,
+    old_pc: i64,
+    hi: i64,
+    lo: i64,
+    constant_regs: u64,
+    gpr: [i64; 32],
+}
+
+impl Registers {
+    pub fn new() -> Self {
+        Self {
+            delay_slot: false,
+            prev_delay_slot: false,
+            pc: 0,
+            next_pc: 0,
+            old_pc: 0,
+            hi: 0,
+            lo: 0,
+            constant_regs: 1,
+            gpr: [0; 32],
+        }
+    }
+
+    pub fn set_pc64(&mut self, val: i64) {
+        self.old_pc = self.pc;
+        self.pc = val;
+        self.next_pc = self.pc + 4;
+    }
+
+    pub fn set_pc32(&mut self, val: i32) {
+        self.old_pc = self.pc;
+        self.pc = val as i64;
+        self.next_pc = self.pc + 4;
+    }
+
+    pub fn read_u8(&self, idx: usize) -> u8 {
+        self.gpr[idx] as u8
+    }
+
+    pub fn read_i8(&self, idx: usize) -> i8 {
+        self.gpr[idx] as i8
+    }
+
+    pub fn read_u16(&self, idx: usize) -> u16 {
+        self.gpr[idx] as u16
+    }
+
+    pub fn read_u32(&self, idx: usize) -> u32 {
+        self.gpr[idx] as u32
+    }
+
+    pub fn read_i16(&self, idx: usize) -> i16 {
+        self.gpr[idx] as i16
+    }
+
+    pub fn read_i32(&self, idx: usize) -> i32 {
+        self.gpr[idx] as i32
+    }
+
+    pub fn write_u8(&mut self, idx: usize, val: u8) {
+        if idx == 0 {
+            return;
+        }
+
+        self.constant_regs |= 1 << idx;
+        self.gpr[idx] = val as i64;
+    }
+
+    pub fn write_i8(&mut self, idx: usize, val: i8) {
+        if idx == 0 {
+            return;
+        }
+
+        self.constant_regs |= 1 << idx;
+        self.gpr[idx] = val as i64;
+    }
+
+    pub fn write_u16(&mut self, idx: usize, val: u16) {
+        if idx == 0 {
+            return;
+        }
+
+        self.constant_regs |= 1 << idx;
+        self.gpr[idx] = val as i64;
+    }
+
+    pub fn write_u32(&mut self, idx: usize, val: u32) {
+        if idx == 0 {
+            return;
+        }
+
+        self.constant_regs |= 1 << idx;
+        self.gpr[idx] = val as i64;
+    }
+
+    pub fn write_i16(&mut self, idx: usize, val: i16) {
+        if idx == 0 {
+            return;
+        }
+
+        self.constant_regs |= 1 << idx;
+        self.gpr[idx] = val as i64;
+    }
+
+    pub fn write_i32(&mut self, idx: usize, val: i32) {
+        if idx == 0 {
+            return;
+        }
+
+        self.constant_regs |= 1 << idx;
+        self.gpr[idx] = val as i64;
+    }
+}

backend/src/lib.rs

@@ -0,0 +1,36 @@
+use proc_bitfield::bitfield;
+
+bitfield! {
+    pub struct ImmediateType(pub u32) {
+        pub opcode: u8 @ 26..32,
+        pub rs: usize @ 21..26,
+        pub rt: usize @ 16..21,
+        pub imm: u16 @ 0..16
+    }
+}
+
+bitfield! {
+    pub struct JumpType(pub u32) {
+        pub opcode: u8 @ 26..32,
+        pub target: u32 @ 0..26
+    }
+}
+
+bitfield! {
+    pub struct RegisterType(pub u32) {
+        pub opcode: u8 @ 26..32,
+        pub rs: usize @ 21..26,
+        pub rt: usize @ 16..21,
+        pub rd: usize @ 11..16,
+        pub sa: u8 @ 6..11,
+        pub funct: u8 @ 0..6,
+    }
+}
+
+pub enum Instruction {
+    IType(ImmediateType),
+    JType(JumpType),
+    RType(RegisterType),
+}
+
+pub mod cpu;