754 lines
24 KiB
C
754 lines
24 KiB
C
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
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/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
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/* Rot127 <unisono@quyllur.org> 2022-2023 */
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/* Automatically translated source file from LLVM. */
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/* LLVM-commit: <commit> */
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/* LLVM-tag: <tag> */
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/* Only small edits allowed. */
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/* For multiple similar edits, please create a Patch for the translator. */
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/* Capstone's C++ file translator: */
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/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
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//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <capstone/platform.h>
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#include "../../MCInst.h"
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#include "../../MathExtras.h"
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#include "../../MCInstPrinter.h"
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#include "../../MCDisassembler.h"
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#include "../../MCFixedLenDisassembler.h"
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#include "../../cs_priv.h"
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#include "../../utils.h"
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#include "RISCVDisassemblerExtension.h"
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#include "RISCVBaseInfo.h"
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#include "RISCVMapping.h"
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#define GET_SUBTARGETINFO_ENUM
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#include "RISCVGenSubtargetInfo.inc"
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#define GET_REGINFO_ENUM
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#include "RISCVGenRegisterInfo.inc"
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#define GET_INSTRINFO_ENUM
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#define GET_INSTRINFO_MC_DESC
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#include "RISCVGenInstrInfo.inc"
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#define CONCAT(a, b) CONCAT_(a, b)
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#define CONCAT_(a, b) a##_##b
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#define DEBUG_TYPE "riscv-disassembler"
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DecodeStatus RISCV_getInstruction(MCInst *Instr, uint16_t *Size,
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const uint8_t *Bytes, size_t BytesLen,
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uint64_t Address, SStream *CStream);
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void addSPOperands(MCInst *MI);
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;
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// end anonymous namespace
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static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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bool IsRVE = RISCV_getFeatureBits(Inst->csh->mode, RISCV_FeatureRVE);
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if (RegNo >= 32 || (IsRVE && RegNo >= 16))
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return MCDisassembler_Fail;
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MCRegister Reg = RISCV_X0 + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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MCRegister Reg = RISCV_X0 + RegNo;
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if (Reg != RISCV_X1 && Reg != RISCV_X5)
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return MCDisassembler_Fail;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPR16RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 32)
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return MCDisassembler_Fail;
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MCRegister Reg = RISCV_F0_H + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 32)
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return MCDisassembler_Fail;
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MCRegister Reg = RISCV_F0_F + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 8) {
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return MCDisassembler_Fail;
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}
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MCRegister Reg = RISCV_F8_F + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 32)
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return MCDisassembler_Fail;
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MCRegister Reg = RISCV_F0_D + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 8) {
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return MCDisassembler_Fail;
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}
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MCRegister Reg = RISCV_F8_D + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo == 0) {
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return MCDisassembler_Fail;
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}
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo,
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uint32_t Address,
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const void *Decoder)
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{
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if (RegNo == 2) {
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return MCDisassembler_Fail;
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}
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return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 8)
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return MCDisassembler_Fail;
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MCRegister Reg = RISCV_X8 + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeGPRPairRegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 32 || RegNo & 1)
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return MCDisassembler_Fail;
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MCRegister Reg = RISCV_X0 + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeSR07RegisterClass(MCInst *Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 8)
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return MCDisassembler_Fail;
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MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV_X8) :
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(RegNo - 2 + RISCV_X18);
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeVRRegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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if (RegNo >= 32)
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return MCDisassembler_Fail;
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MCRegister Reg = RISCV_V0 + RegNo;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeVRM2RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 32 || RegNo % 2)
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return MCDisassembler_Fail;
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MCRegister Reg = MCRegisterInfo_getMatchingSuperReg(
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Inst->MRI, RISCV_V0 + RegNo, RISCV_sub_vrm1_0,
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MCRegisterInfo_getRegClass(Inst->MRI, RISCV_VRM2RegClassID));
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeVRM4RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 32 || RegNo % 4)
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return MCDisassembler_Fail;
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MCRegister Reg = MCRegisterInfo_getMatchingSuperReg(
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Inst->MRI, RISCV_V0 + RegNo, RISCV_sub_vrm1_0,
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MCRegisterInfo_getRegClass(Inst->MRI, RISCV_VRM4RegClassID));
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus DecodeVRM8RegisterClass(MCInst *Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder)
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{
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if (RegNo >= 32 || RegNo % 8)
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return MCDisassembler_Fail;
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MCRegister Reg = MCRegisterInfo_getMatchingSuperReg(
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Inst->MRI, RISCV_V0 + RegNo, RISCV_sub_vrm1_0,
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MCRegisterInfo_getRegClass(Inst->MRI, RISCV_VRM8RegClassID));
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeVMaskReg(MCInst *Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder)
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{
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if (RegNo > 2) {
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return MCDisassembler_Fail;
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}
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MCRegister Reg = (RegNo == 0) ? RISCV_V0 : RISCV_NoRegister;
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MCOperand_CreateReg0(Inst, (Reg));
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return MCDisassembler_Success;
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}
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#define DEFINE_decodeUImmOperand(N) \
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static DecodeStatus CONCAT(decodeUImmOperand, \
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N)(MCInst * Inst, uint32_t Imm, \
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int64_t Address, const void *Decoder) \
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{ \
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CS_ASSERT(isUIntN(N, Imm) && "Invalid immediate"); \
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MCOperand_CreateImm0(Inst, (Imm)); \
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return MCDisassembler_Success; \
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}
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DEFINE_decodeUImmOperand(6);
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DEFINE_decodeUImmOperand(2);
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DEFINE_decodeUImmOperand(8);
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DEFINE_decodeUImmOperand(9);
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DEFINE_decodeUImmOperand(7);
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DEFINE_decodeUImmOperand(4);
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DEFINE_decodeUImmOperand(20);
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DEFINE_decodeUImmOperand(5);
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DEFINE_decodeUImmOperand(11);
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DEFINE_decodeUImmOperand(10);
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DEFINE_decodeUImmOperand(12);
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DEFINE_decodeUImmOperand(3);
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DEFINE_decodeUImmOperand(1);
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#define DEFINE_decodeUImmNonZeroOperand(N) \
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static DecodeStatus CONCAT(decodeUImmNonZeroOperand, \
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N)(MCInst * Inst, uint32_t Imm, \
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int64_t Address, const void *Decoder) \
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{ \
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if (Imm == 0) \
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return MCDisassembler_Fail; \
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return CONCAT(decodeUImmOperand, N)(Inst, Imm, Address, \
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Decoder); \
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}
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DEFINE_decodeUImmNonZeroOperand(10);
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#define DEFINE_decodeSImmOperand(N) \
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static DecodeStatus CONCAT(decodeSImmOperand, \
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N)(MCInst * Inst, uint32_t Imm, \
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int64_t Address, const void *Decoder) \
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{ \
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CS_ASSERT(isUIntN(N, Imm) && "Invalid immediate"); \
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\
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MCOperand_CreateImm0(Inst, (SignExtend64((Imm), N))); \
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return MCDisassembler_Success; \
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}
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DEFINE_decodeSImmOperand(6);
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DEFINE_decodeSImmOperand(12);
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DEFINE_decodeSImmOperand(5);
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DEFINE_decodeSImmOperand(10);
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#define DEFINE_decodeSImmNonZeroOperand(N) \
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static DecodeStatus CONCAT(decodeSImmNonZeroOperand, \
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N)(MCInst * Inst, uint32_t Imm, \
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int64_t Address, const void *Decoder) \
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{ \
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if (Imm == 0) \
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return MCDisassembler_Fail; \
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return CONCAT(decodeSImmOperand, N)(Inst, Imm, Address, \
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Decoder); \
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}
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DEFINE_decodeSImmNonZeroOperand(6);
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DEFINE_decodeSImmNonZeroOperand(10);
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#define DEFINE_decodeSImmOperandAndLsl1(N) \
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static DecodeStatus CONCAT(decodeSImmOperandAndLsl1, \
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N)(MCInst * Inst, uint32_t Imm, \
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int64_t Address, const void *Decoder) \
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{ \
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CS_ASSERT(isUIntN(N, Imm) && "Invalid immediate"); \
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\
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MCOperand_CreateImm0(Inst, (SignExtend64((Imm << 1), N))); \
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return MCDisassembler_Success; \
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}
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DEFINE_decodeSImmOperandAndLsl1(12);
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DEFINE_decodeSImmOperandAndLsl1(9);
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DEFINE_decodeSImmOperandAndLsl1(13);
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DEFINE_decodeSImmOperandAndLsl1(21);
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static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint32_t Imm,
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int64_t Address, const void *Decoder)
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{
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CS_ASSERT(isUIntN(6, Imm) && "Invalid immediate");
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if (Imm > 31) {
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Imm = (SignExtend64((Imm), 6) & 0xfffff);
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}
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MCOperand_CreateImm0(Inst, (Imm));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeFRMArg(MCInst *Inst, uint32_t Imm, int64_t Address,
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const void *Decoder)
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{
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CS_ASSERT(isUIntN(3, Imm) && "Invalid immediate");
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if (!RISCVFPRndMode_isValidRoundingMode(Imm))
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return MCDisassembler_Fail;
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MCOperand_CreateImm0(Inst, (Imm));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst *Inst, uint32_t Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus decodeRVCInstrRdSImm(MCInst *Inst, uint32_t Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst *Inst, uint32_t Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs2(MCInst *Inst, uint32_t Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst *Inst, uint32_t Insn,
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uint64_t Address,
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const void *Decoder);
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static DecodeStatus decodeXTHeadMemPair(MCInst *Inst, uint32_t Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeZcmpRlist(MCInst *Inst, unsigned Imm,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeRegReg(MCInst *Inst, uint32_t Insn, uint64_t Address,
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const void *Decoder);
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static DecodeStatus decodeZcmpSpimm(MCInst *Inst, unsigned Imm,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeCSSPushPopchk(MCInst *Inst, uint32_t Insn,
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uint64_t Address, const void *Decoder);
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static DecodeStatus decodeUImmLog2XLenOperand(MCInst *Inst, uint32_t Imm,
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int64_t Address,
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const void *Decoder)
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{
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CS_ASSERT(isUIntN(6, Imm) && "Invalid immediate");
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if (!RISCV_getFeatureBits(Inst->csh->mode, RISCV_Feature64Bit) &&
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!isUIntN(5, Imm))
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return MCDisassembler_Fail;
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MCOperand_CreateImm0(Inst, (Imm));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeUImmLog2XLenNonZeroOperand(MCInst *Inst, uint32_t Imm,
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int64_t Address,
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const void *Decoder)
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{
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if (Imm == 0)
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return MCDisassembler_Fail;
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return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
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}
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#include "RISCVGenDisassemblerTables.inc"
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static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst *Inst, uint32_t Insn,
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uint64_t Address,
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const void *Decoder)
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{
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uint32_t Rd = fieldFromInstruction_4(Insn, 7, 5);
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DecodeStatus Result =
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DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder);
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(void)Result;
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CS_ASSERT(Result == MCDisassembler_Success && "Invalid register");
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MCInst_addOperand2(Inst, (MCInst_getOperand(Inst, (0))));
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MCOperand_CreateImm0(Inst, (0));
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeCSSPushPopchk(MCInst *Inst, uint32_t Insn,
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uint64_t Address, const void *Decoder)
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{
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uint32_t Rs1 = fieldFromInstruction_4(Insn, 7, 5);
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DecodeStatus Result =
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DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
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(void)Result;
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CS_ASSERT(Result == MCDisassembler_Success && "Invalid register");
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeRVCInstrRdSImm(MCInst *Inst, uint32_t Insn,
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uint64_t Address, const void *Decoder)
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{
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MCOperand_CreateReg0(Inst, (RISCV_X0));
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uint32_t SImm6 = fieldFromInstruction_4(Insn, 12, 1) << 5 |
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fieldFromInstruction_4(Insn, 2, 5);
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DecodeStatus Result =
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CONCAT(decodeSImmOperand, 6)(Inst, SImm6, Address, Decoder);
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(void)Result;
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CS_ASSERT(Result == MCDisassembler_Success && "Invalid immediate");
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return MCDisassembler_Success;
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}
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static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst *Inst, uint32_t Insn,
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uint64_t Address,
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const void *Decoder)
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{
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MCOperand_CreateReg0(Inst, (RISCV_X0));
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MCInst_addOperand2(Inst, (MCInst_getOperand(Inst, (0))));
|
|
uint32_t UImm6 = fieldFromInstruction_4(Insn, 12, 1) << 5 |
|
|
fieldFromInstruction_4(Insn, 2, 5);
|
|
DecodeStatus Result =
|
|
CONCAT(decodeUImmOperand, 6)(Inst, UImm6, Address, Decoder);
|
|
(void)Result;
|
|
CS_ASSERT(Result == MCDisassembler_Success && "Invalid immediate");
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus decodeRVCInstrRdRs2(MCInst *Inst, uint32_t Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
uint32_t Rd = fieldFromInstruction_4(Insn, 7, 5);
|
|
uint32_t Rs2 = fieldFromInstruction_4(Insn, 2, 5);
|
|
DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
|
|
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus decodeRVCInstrRdRs1Rs2(MCInst *Inst, uint32_t Insn,
|
|
uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
uint32_t Rd = fieldFromInstruction_4(Insn, 7, 5);
|
|
uint32_t Rs2 = fieldFromInstruction_4(Insn, 2, 5);
|
|
DecodeGPRRegisterClass(Inst, Rd, Address, Decoder);
|
|
MCInst_addOperand2(Inst, (MCInst_getOperand(Inst, (0))));
|
|
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus decodeXTHeadMemPair(MCInst *Inst, uint32_t Insn,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
uint32_t Rd1 = fieldFromInstruction_4(Insn, 7, 5);
|
|
uint32_t Rs1 = fieldFromInstruction_4(Insn, 15, 5);
|
|
uint32_t Rd2 = fieldFromInstruction_4(Insn, 20, 5);
|
|
uint32_t UImm2 = fieldFromInstruction_4(Insn, 25, 2);
|
|
DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder);
|
|
DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder);
|
|
DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
|
|
DecodeStatus Result =
|
|
CONCAT(decodeUImmOperand, 2)(Inst, UImm2, Address, Decoder);
|
|
(void)Result;
|
|
CS_ASSERT(Result == MCDisassembler_Success && "Invalid immediate");
|
|
|
|
// Disassemble the final operand which is implicit.
|
|
unsigned Opcode = MCInst_getOpcode(Inst);
|
|
bool IsWordOp = (Opcode == RISCV_TH_LWD || Opcode == RISCV_TH_LWUD ||
|
|
Opcode == RISCV_TH_SWD);
|
|
if (IsWordOp)
|
|
MCOperand_CreateImm0(Inst, (3));
|
|
else
|
|
MCOperand_CreateImm0(Inst, (4));
|
|
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus decodeZcmpRlist(MCInst *Inst, unsigned Imm,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
if (Imm <= 3)
|
|
return MCDisassembler_Fail;
|
|
MCOperand_CreateImm0(Inst, (Imm));
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus decodeRegReg(MCInst *Inst, uint32_t Insn, uint64_t Address,
|
|
const void *Decoder)
|
|
{
|
|
uint32_t Rs1 = fieldFromInstruction_4(Insn, 0, 5);
|
|
uint32_t Rs2 = fieldFromInstruction_4(Insn, 5, 5);
|
|
DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder);
|
|
DecodeGPRRegisterClass(Inst, Rs2, Address, Decoder);
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
static DecodeStatus decodeZcmpSpimm(MCInst *Inst, unsigned Imm,
|
|
uint64_t Address, const void *Decoder)
|
|
{
|
|
MCOperand_CreateImm0(Inst, (Imm));
|
|
return MCDisassembler_Success;
|
|
}
|
|
|
|
// Add implied SP operand for C.*SP compressed instructions. The SP operand
|
|
// isn't explicitly encoded in the instruction.
|
|
void addSPOperands(MCInst *MI)
|
|
{
|
|
const MCInstrDesc *MCID = MCInstrDesc_get(MCInst_getOpcode(MI),
|
|
RISCVDescs.Insts,
|
|
ARR_SIZE(RISCVDescs.Insts));
|
|
MCOperand SPReg;
|
|
SPReg.MachineOperandType = kRegister;
|
|
SPReg.Kind = kRegister;
|
|
SPReg.RegVal = RISCV_X2;
|
|
for (unsigned i = 0; i < MCID->NumOperands; i++)
|
|
if (MCID->OpInfo[i].RegClass == RISCV_SPRegClassID)
|
|
MCInst_insert0(MI, i, &SPReg);
|
|
}
|
|
|
|
DecodeStatus RISCV_getInstruction(MCInst *MI, uint16_t *Size,
|
|
const uint8_t *Bytes, size_t BytesLen,
|
|
uint64_t Address, SStream *CS)
|
|
{
|
|
// TODO: This will need modification when supporting instruction set
|
|
// extensions with instructions > 32-bits (up to 176 bits wide).
|
|
uint32_t Insn;
|
|
DecodeStatus Result;
|
|
|
|
#define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION( \
|
|
width, FEATURE_CHECKS, DECODER_TABLE, DESC, ADDITIONAL_OPERATION) \
|
|
do { \
|
|
if (FEATURE_CHECKS) { \
|
|
Result = decodeInstruction_##width( \
|
|
DECODER_TABLE, MI, Insn, Address, NULL); \
|
|
if (Result != MCDisassembler_Fail) { \
|
|
ADDITIONAL_OPERATION; \
|
|
return Result; \
|
|
} \
|
|
} \
|
|
} while (false)
|
|
#define TRY_TO_DECODE_AND_ADD_SP(width, FEATURE_CHECKS, DECODER_TABLE, DESC) \
|
|
TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION( \
|
|
width, FEATURE_CHECKS, DECODER_TABLE, DESC, addSPOperands(MI))
|
|
#define TRY_TO_DECODE(width, FEATURE_CHECKS, DECODER_TABLE, DESC) \
|
|
TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION( \
|
|
width, FEATURE_CHECKS, DECODER_TABLE, DESC, (void)NULL)
|
|
#define TRY_TO_DECODE_FEATURE(width, FEATURE, DECODER_TABLE, DESC) \
|
|
TRY_TO_DECODE(width, RISCV_getFeatureBits(MI->csh->mode, FEATURE), \
|
|
DECODER_TABLE, DESC)
|
|
|
|
// It's a 32 bit instruction if bit 0 and 1 are 1.
|
|
if ((Bytes[0] & 0x3) == 0x3) {
|
|
if (BytesLen < 4) {
|
|
*Size = 0;
|
|
return MCDisassembler_Fail;
|
|
}
|
|
*Size = 4;
|
|
|
|
Insn = readBytes32(MI, Bytes);
|
|
|
|
TRY_TO_DECODE(4,
|
|
RISCV_getFeatureBits(MI->csh->mode,
|
|
RISCV_FeatureStdExtZdinx) &&
|
|
!RISCV_getFeatureBits(MI->csh->mode,
|
|
RISCV_Feature64Bit),
|
|
DecoderTableRV32Zdinx32,
|
|
"RV32Zdinx table (Double in Integer and rv32)");
|
|
TRY_TO_DECODE(4,
|
|
RISCV_getFeatureBits(MI->csh->mode,
|
|
RISCV_FeatureStdExtZacas) &&
|
|
!RISCV_getFeatureBits(MI->csh->mode,
|
|
RISCV_Feature64Bit),
|
|
DecoderTableRV32Zacas32,
|
|
"RV32Zacas table (Compare-And-Swap and rv32)");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureStdExtZfinx,
|
|
DecoderTableRVZfinx32,
|
|
"RVZfinx table (Float in Integer)");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXVentanaCondOps,
|
|
DecoderTableXVentana32,
|
|
"Ventana custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadBa,
|
|
DecoderTableXTHeadBa32,
|
|
"XTHeadBa custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadBb,
|
|
DecoderTableXTHeadBb32,
|
|
"XTHeadBb custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadBs,
|
|
DecoderTableXTHeadBs32,
|
|
"XTHeadBs custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadCondMov,
|
|
DecoderTableXTHeadCondMov32,
|
|
"XTHeadCondMov custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadCmo,
|
|
DecoderTableXTHeadCmo32,
|
|
"XTHeadCmo custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadFMemIdx,
|
|
DecoderTableXTHeadFMemIdx32,
|
|
"XTHeadFMemIdx custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadMac,
|
|
DecoderTableXTHeadMac32,
|
|
"XTHeadMac custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadMemIdx,
|
|
DecoderTableXTHeadMemIdx32,
|
|
"XTHeadMemIdx custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadMemPair,
|
|
DecoderTableXTHeadMemPair32,
|
|
"XTHeadMemPair custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadSync,
|
|
DecoderTableXTHeadSync32,
|
|
"XTHeadSync custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXTHeadVdot,
|
|
DecoderTableXTHeadVdot32,
|
|
"XTHeadVdot custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXSfvcp,
|
|
DecoderTableXSfvcp32,
|
|
"SiFive VCIX custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
4, RISCV_FeatureVendorXSfvqmaccdod,
|
|
DecoderTableXSfvqmaccdod32,
|
|
"SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
4, RISCV_FeatureVendorXSfvqmaccqoq,
|
|
DecoderTableXSfvqmaccqoq32,
|
|
"SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
4, RISCV_FeatureVendorXSfvfwmaccqqq,
|
|
DecoderTableXSfvfwmaccqqq32,
|
|
"SiFive Matrix Multiplication Instruction opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
4, RISCV_FeatureVendorXSfvfnrclipxfqf,
|
|
DecoderTableXSfvfnrclipxfqf32,
|
|
"SiFive FP32-to-int8 Ranged Clip Instructions opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
4, RISCV_FeatureVendorXCVbitmanip,
|
|
DecoderTableXCVbitmanip32,
|
|
"CORE-V Bit Manipulation custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCVelw,
|
|
DecoderTableXCVelw32,
|
|
"CORE-V Event load custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCVmac,
|
|
DecoderTableXCVmac32,
|
|
"CORE-V MAC custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCVmem,
|
|
DecoderTableXCVmem32,
|
|
"CORE-V MEM custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(4, RISCV_FeatureVendorXCValu,
|
|
DecoderTableXCValu32,
|
|
"CORE-V ALU custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
4, RISCV_FeatureVendorXCVsimd, DecoderTableXCVsimd32,
|
|
"CORE-V SIMD extensions custom opcode table");
|
|
TRY_TO_DECODE_FEATURE(
|
|
4, RISCV_FeatureVendorXCVbi, DecoderTableXCVbi32,
|
|
"CORE-V Immediate Branching custom opcode table");
|
|
TRY_TO_DECODE(4, true, DecoderTable32, "RISCV32 table");
|
|
|
|
return MCDisassembler_Fail;
|
|
}
|
|
|
|
if (BytesLen < 2) {
|
|
*Size = 0;
|
|
return MCDisassembler_Fail;
|
|
}
|
|
*Size = 2;
|
|
|
|
Insn = readBytes16(MI, Bytes);
|
|
TRY_TO_DECODE_AND_ADD_SP(
|
|
2, !RISCV_getFeatureBits(MI->csh->mode, RISCV_Feature64Bit),
|
|
DecoderTableRISCV32Only_16,
|
|
"RISCV32Only_16 table (16-bit Instruction)");
|
|
TRY_TO_DECODE_FEATURE(2, RISCV_FeatureStdExtZicfiss,
|
|
DecoderTableZicfiss16,
|
|
"RVZicfiss table (Shadow Stack)");
|
|
TRY_TO_DECODE_FEATURE(2, RISCV_FeatureStdExtZcmt, DecoderTableRVZcmt16,
|
|
"Zcmt table (16-bit Table Jump Instructions)");
|
|
TRY_TO_DECODE_FEATURE(
|
|
2, RISCV_FeatureStdExtZcmp, DecoderTableRVZcmp16,
|
|
"Zcmp table (16-bit Push/Pop & Double Move Instructions)");
|
|
TRY_TO_DECODE_AND_ADD_SP(2, true, DecoderTable16,
|
|
"RISCV_C table (16-bit Instruction)");
|
|
|
|
return MCDisassembler_Fail;
|
|
}
|
|
|
|
bool RISCV_LLVM_getInstruction(csh handle, const uint8_t *Bytes, size_t ByteLen,
|
|
MCInst *MI, uint16_t *Size, uint64_t Address,
|
|
void *Info)
|
|
{
|
|
RISCV_init_cs_detail(MI);
|
|
MI->MRI = (MCRegisterInfo *)Info;
|
|
return RISCV_getInstruction(MI, Size, Bytes, ByteLen, Address, NULL) !=
|
|
MCDisassembler_Fail;
|
|
}
|