Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd
de6e324bdseparate emu thread10d3daf86Roms List improvements95d202f37Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.fc306967fWow the ROM Header was just completely busted. Game list view works nowbad1691eefuck this shit2b59e5f46game list in progressd26417b83remappable inputs in progressac4af8106inpute72abc240update readme430139dc9Qt6 frontend3080d4d45Fix this small bug too08cd13b85Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.61bb4fb44make idle loop detection a little more specific with where the load goesb037de4c3SAZDFsdff12e81e73eneed to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)204f0e13bidle skipping seems to work!cb8bb634asdkfjlasdf58e5c89c1Fix compilation issue on my machine (no idea)24fb2898eattempting more serious idle skipping214719577Place rsp.Step inside cached interpreter. Gains about 3 more fpsbb97dcc23mmmmm920b77d38wjkhasdfjhkasdf430ccdab4it's a start...4f42a673aCached interpreter plays Mario 64. Start looking into RSP as wellc9a030787idle skipping works!5fbda03cenew idea366637abaIdle skipping... maybe?609fa2fb0Cache instructions implemented but broken lmao. Commented out for nowe140a6d12- Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work68e613057prep cache impl811b4d809fix clang formatfda755f7didkd5024ebbfsmall MI refactor in preparation of (eventually) implementing the RDRAM interface properly694b45341Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'206dcdedfSquashed 'external/SDL/' content from commit 4d17b99d0a4d16e1cb4need to update sdl848b19920Fix compilation errordb61b5299Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'e94a94559Squashed 'external/imgui/' content from commit 02e9b8cac52edb3757need to update imguic1a705e86Emulate weird JALR behaviour4b4c32f4bFix exception for "unusable COP1" in 4 instructions i missed accidentally (again)df5828142Bug putting 0s in the log everywheref8b580048Make isviewer a sink to file8241e9735Fix exception for "unusable COP1" in 4 instructions i missed accidentallyb29715f20small changesd9a620bc1make use of my new small utility library0d1aa938eAdd 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'e64eb40b3Fuck git git-subtree-dir: external/ircolib git-subtree-split:de6e324bde
This commit is contained in:
@@ -0,0 +1,544 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */
|
||||
|
||||
#include "capstone/mos65xx.h"
|
||||
#include "MOS65XXDisassembler.h"
|
||||
#include "MOS65XXDisassemblerInternals.h"
|
||||
|
||||
typedef struct OpInfo {
|
||||
mos65xx_insn ins;
|
||||
mos65xx_address_mode am;
|
||||
int operand_bytes;
|
||||
} OpInfo;
|
||||
|
||||
static const struct OpInfo OpInfoTable[]= {
|
||||
|
||||
#include "m6502.inc"
|
||||
#include "m65c02.inc"
|
||||
#include "mw65c02.inc"
|
||||
#include "m65816.inc"
|
||||
|
||||
};
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static const char* const RegNames[] = {
|
||||
"invalid", "A", "X", "Y", "P", "SP", "DP", "B", "K"
|
||||
};
|
||||
|
||||
static const char* const GroupNames[] = {
|
||||
NULL,
|
||||
"jump",
|
||||
"call",
|
||||
"ret",
|
||||
"int",
|
||||
"iret",
|
||||
"branch_relative"
|
||||
};
|
||||
|
||||
typedef struct InstructionInfo {
|
||||
const char* name;
|
||||
mos65xx_group_type group_type;
|
||||
mos65xx_reg write, read;
|
||||
bool modifies_status;
|
||||
} InstructionInfo;
|
||||
|
||||
static const struct InstructionInfo InstructionInfoTable[]= {
|
||||
|
||||
#include "instruction_info.inc"
|
||||
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
static void fillDetails(MCInst *MI, struct OpInfo opinfo, int cpu_type)
|
||||
{
|
||||
int i;
|
||||
cs_detail *detail = MI->flat_insn->detail;
|
||||
|
||||
InstructionInfo insinfo = InstructionInfoTable[opinfo.ins];
|
||||
|
||||
detail->mos65xx.am = opinfo.am;
|
||||
detail->mos65xx.modifies_flags = insinfo.modifies_status;
|
||||
detail->groups_count = 0;
|
||||
detail->regs_read_count = 0;
|
||||
detail->regs_write_count = 0;
|
||||
detail->mos65xx.op_count = 0;
|
||||
|
||||
if (insinfo.group_type != MOS65XX_GRP_INVALID) {
|
||||
detail->groups[detail->groups_count] = insinfo.group_type;
|
||||
detail->groups_count++;
|
||||
}
|
||||
|
||||
if (opinfo.am == MOS65XX_AM_REL || opinfo.am == MOS65XX_AM_ZP_REL) {
|
||||
detail->groups[detail->groups_count] = MOS65XX_GRP_BRANCH_RELATIVE;
|
||||
detail->groups_count++;
|
||||
}
|
||||
|
||||
if (insinfo.read != MOS65XX_REG_INVALID) {
|
||||
detail->regs_read[detail->regs_read_count++] = insinfo.read;
|
||||
} else switch(opinfo.am) {
|
||||
case MOS65XX_AM_ACC:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC;
|
||||
break;
|
||||
case MOS65XX_AM_ZP_Y:
|
||||
case MOS65XX_AM_ZP_IND_Y:
|
||||
case MOS65XX_AM_ABS_Y:
|
||||
case MOS65XX_AM_ZP_IND_LONG_Y:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_X:
|
||||
case MOS65XX_AM_ZP_X_IND:
|
||||
case MOS65XX_AM_ABS_X:
|
||||
case MOS65XX_AM_ABS_X_IND:
|
||||
case MOS65XX_AM_ABS_LONG_X:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X;
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_SR:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
|
||||
break;
|
||||
case MOS65XX_AM_SR_IND_Y:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (insinfo.write != MOS65XX_REG_INVALID) {
|
||||
detail->regs_write[detail->regs_write_count++] = insinfo.write;
|
||||
} else if (opinfo.am == MOS65XX_AM_ACC) {
|
||||
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC;
|
||||
}
|
||||
|
||||
|
||||
switch(opinfo.ins) {
|
||||
case MOS65XX_INS_ADC:
|
||||
case MOS65XX_INS_SBC:
|
||||
case MOS65XX_INS_ROL:
|
||||
case MOS65XX_INS_ROR:
|
||||
/* these read carry flag (and decimal for ADC/SBC) */
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_P;
|
||||
break;
|
||||
/* stack operations */
|
||||
case MOS65XX_INS_JSL:
|
||||
case MOS65XX_INS_JSR:
|
||||
case MOS65XX_INS_PEA:
|
||||
case MOS65XX_INS_PEI:
|
||||
case MOS65XX_INS_PER:
|
||||
case MOS65XX_INS_PHA:
|
||||
case MOS65XX_INS_PHB:
|
||||
case MOS65XX_INS_PHD:
|
||||
case MOS65XX_INS_PHK:
|
||||
case MOS65XX_INS_PHP:
|
||||
case MOS65XX_INS_PHX:
|
||||
case MOS65XX_INS_PHY:
|
||||
case MOS65XX_INS_PLA:
|
||||
case MOS65XX_INS_PLB:
|
||||
case MOS65XX_INS_PLD:
|
||||
case MOS65XX_INS_PLP:
|
||||
case MOS65XX_INS_PLX:
|
||||
case MOS65XX_INS_PLY:
|
||||
case MOS65XX_INS_RTI:
|
||||
case MOS65XX_INS_RTL:
|
||||
case MOS65XX_INS_RTS:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_SP;
|
||||
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_SP;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (cpu_type == MOS65XX_CPU_TYPE_65816) {
|
||||
switch (opinfo.am) {
|
||||
case MOS65XX_AM_ZP:
|
||||
case MOS65XX_AM_ZP_X:
|
||||
case MOS65XX_AM_ZP_Y:
|
||||
case MOS65XX_AM_ZP_IND:
|
||||
case MOS65XX_AM_ZP_X_IND:
|
||||
case MOS65XX_AM_ZP_IND_Y:
|
||||
case MOS65XX_AM_ZP_IND_LONG:
|
||||
case MOS65XX_AM_ZP_IND_LONG_Y:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_DP;
|
||||
break;
|
||||
case MOS65XX_AM_BLOCK:
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_ACC;
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_X;
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_Y;
|
||||
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_ACC;
|
||||
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_X;
|
||||
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_Y;
|
||||
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_B;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
switch (opinfo.am) {
|
||||
case MOS65XX_AM_ZP_IND:
|
||||
case MOS65XX_AM_ZP_X_IND:
|
||||
case MOS65XX_AM_ZP_IND_Y:
|
||||
case MOS65XX_AM_ABS:
|
||||
case MOS65XX_AM_ABS_X:
|
||||
case MOS65XX_AM_ABS_Y:
|
||||
case MOS65XX_AM_ABS_X_IND:
|
||||
/* these depend on the databank to generate a 24-bit address */
|
||||
/* exceptions: PEA, PEI, and JMP (abs) */
|
||||
if (opinfo.ins == MOS65XX_INS_PEI || opinfo.ins == MOS65XX_INS_PEA) break;
|
||||
detail->regs_read[detail->regs_read_count++] = MOS65XX_REG_B;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (insinfo.modifies_status) {
|
||||
detail->regs_write[detail->regs_write_count++] = MOS65XX_REG_P;
|
||||
}
|
||||
|
||||
switch(opinfo.am) {
|
||||
case MOS65XX_AM_IMP:
|
||||
break;
|
||||
case MOS65XX_AM_IMM:
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_IMM;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].imm = MI->Operands[0].ImmVal;
|
||||
detail->mos65xx.op_count++;
|
||||
break;
|
||||
case MOS65XX_AM_ACC:
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_REG;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].reg = MOS65XX_REG_ACC;
|
||||
detail->mos65xx.op_count++;
|
||||
break;
|
||||
case MOS65XX_AM_REL: {
|
||||
int value = MI->Operands[0].ImmVal;
|
||||
if (MI->op1_size == 1)
|
||||
value = 2 + (signed char)value;
|
||||
else
|
||||
value = 3 + (signed short)value;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].mem = (MI->address + value) & 0xffff;
|
||||
detail->mos65xx.op_count++;
|
||||
break;
|
||||
}
|
||||
case MOS65XX_AM_ZP_REL: {
|
||||
int value = 3 + (signed char)MI->Operands[1].ImmVal;
|
||||
/* BBR0, zp, rel and BBS0, zp, rel */
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[0].ImmVal;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count+1].type = MOS65XX_OP_MEM;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count+1].mem = (MI->address + value) & 0xffff;
|
||||
detail->mos65xx.op_count+=2;
|
||||
break;
|
||||
}
|
||||
default:
|
||||
for (i = 0; i < MI->size; ++i) {
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].type = MOS65XX_OP_MEM;
|
||||
detail->mos65xx.operands[detail->mos65xx.op_count].mem = MI->Operands[i].ImmVal;
|
||||
detail->mos65xx.op_count++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo)
|
||||
{
|
||||
#ifndef CAPSTONE_DIET
|
||||
unsigned int value;
|
||||
unsigned opcode = MCInst_getOpcode(MI);
|
||||
mos65xx_info *info = (mos65xx_info *)PrinterInfo;
|
||||
|
||||
OpInfo opinfo = OpInfoTable[opcode];
|
||||
|
||||
const char *prefix = info->hex_prefix ? info->hex_prefix : "0x";
|
||||
|
||||
SStream_concat0(O, InstructionInfoTable[opinfo.ins].name);
|
||||
switch (opinfo.ins) {
|
||||
/* special case - bit included as part of the instruction name */
|
||||
case MOS65XX_INS_BBR:
|
||||
case MOS65XX_INS_BBS:
|
||||
case MOS65XX_INS_RMB:
|
||||
case MOS65XX_INS_SMB:
|
||||
SStream_concat(O, "%d", (opcode >> 4) & 0x07);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
value = MI->Operands[0].ImmVal;
|
||||
|
||||
switch (opinfo.am) {
|
||||
default:
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_IMP:
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ACC:
|
||||
SStream_concat0(O, " a");
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_IMM:
|
||||
if (MI->imm_size == 1)
|
||||
SStream_concat(O, " #%s%02x", prefix, value);
|
||||
else
|
||||
SStream_concat(O, " #%s%04x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP:
|
||||
SStream_concat(O, " %s%02x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS:
|
||||
SStream_concat(O, " %s%04x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS_LONG_X:
|
||||
SStream_concat(O, " %s%06x, x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_INT:
|
||||
SStream_concat(O, " %s%02x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS_X:
|
||||
SStream_concat(O, " %s%04x, x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS_Y:
|
||||
SStream_concat(O, " %s%04x, y", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS_LONG:
|
||||
SStream_concat(O, " %s%06x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_X:
|
||||
SStream_concat(O, " %s%02x, x", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_Y:
|
||||
SStream_concat(O, " %s%02x, y", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_REL:
|
||||
if (MI->op1_size == 1)
|
||||
value = 2 + (signed char)value;
|
||||
else
|
||||
value = 3 + (signed short)value;
|
||||
|
||||
SStream_concat(O, " %s%04x", prefix,
|
||||
(MI->address + value) & 0xffff);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS_IND:
|
||||
SStream_concat(O, " (%s%04x)", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS_X_IND:
|
||||
SStream_concat(O, " (%s%04x, x)", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ABS_IND_LONG:
|
||||
SStream_concat(O, " [%s%04x]", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_IND:
|
||||
SStream_concat(O, " (%s%02x)", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_X_IND:
|
||||
SStream_concat(O, " (%s%02x, x)", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_IND_Y:
|
||||
SStream_concat(O, " (%s%02x), y", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_IND_LONG:
|
||||
SStream_concat(O, " [%s%02x]", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_IND_LONG_Y:
|
||||
SStream_concat(O, " [%s%02x], y", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_SR:
|
||||
SStream_concat(O, " %s%02x, s", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_SR_IND_Y:
|
||||
SStream_concat(O, " (%s%02x, s), y", prefix, value);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_BLOCK:
|
||||
SStream_concat(O, " %s%02x, %s%02x",
|
||||
prefix, MI->Operands[0].ImmVal,
|
||||
prefix, MI->Operands[1].ImmVal);
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_ZP_REL:
|
||||
value = 3 + (signed char)MI->Operands[1].ImmVal;
|
||||
/* BBR0, zp, rel and BBS0, zp, rel */
|
||||
SStream_concat(O, " %s%02x, %s%04x",
|
||||
prefix, MI->Operands[0].ImmVal,
|
||||
prefix, (MI->address + value) & 0xffff);
|
||||
break;
|
||||
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
|
||||
MCInst *MI, uint16_t *size, uint64_t address, void *inst_info)
|
||||
{
|
||||
int i;
|
||||
unsigned char opcode;
|
||||
unsigned char len;
|
||||
unsigned cpu_offset = 0;
|
||||
int cpu_type = MOS65XX_CPU_TYPE_6502;
|
||||
cs_struct* handle = MI->csh;
|
||||
mos65xx_info *info = (mos65xx_info *)handle->printer_info;
|
||||
OpInfo opinfo;
|
||||
|
||||
if (code_len == 0) {
|
||||
*size = 1;
|
||||
return false;
|
||||
}
|
||||
|
||||
cpu_type = info->cpu_type;
|
||||
cpu_offset = cpu_type * 256;
|
||||
|
||||
opcode = code[0];
|
||||
opinfo = OpInfoTable[cpu_offset + opcode];
|
||||
if (opinfo.ins == MOS65XX_INS_INVALID) {
|
||||
*size = 1;
|
||||
return false;
|
||||
}
|
||||
|
||||
len = opinfo.operand_bytes + 1;
|
||||
|
||||
if (cpu_type == MOS65XX_CPU_TYPE_65816 && opinfo.am == MOS65XX_AM_IMM) {
|
||||
switch(opinfo.ins) {
|
||||
case MOS65XX_INS_CPX:
|
||||
case MOS65XX_INS_CPY:
|
||||
case MOS65XX_INS_LDX:
|
||||
case MOS65XX_INS_LDY:
|
||||
if (info->long_x) ++len;
|
||||
break;
|
||||
case MOS65XX_INS_ADC:
|
||||
case MOS65XX_INS_AND:
|
||||
case MOS65XX_INS_BIT:
|
||||
case MOS65XX_INS_CMP:
|
||||
case MOS65XX_INS_EOR:
|
||||
case MOS65XX_INS_LDA:
|
||||
case MOS65XX_INS_ORA:
|
||||
case MOS65XX_INS_SBC:
|
||||
if (info->long_m) ++len;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
if (code_len < len) {
|
||||
*size = 1;
|
||||
return false;
|
||||
}
|
||||
|
||||
MI->address = address;
|
||||
|
||||
MCInst_setOpcode(MI, cpu_offset + opcode);
|
||||
MCInst_setOpcodePub(MI, opinfo.ins);
|
||||
|
||||
*size = len;
|
||||
|
||||
/* needed to differentiate relative vs relative long */
|
||||
MI->op1_size = len - 1;
|
||||
if (opinfo.ins == MOS65XX_INS_NOP) {
|
||||
for (i = 1; i < len; ++i)
|
||||
MCOperand_CreateImm0(MI, code[i]);
|
||||
}
|
||||
|
||||
switch (opinfo.am) {
|
||||
case MOS65XX_AM_ZP_REL:
|
||||
MCOperand_CreateImm0(MI, code[1]);
|
||||
MCOperand_CreateImm0(MI, code[2]);
|
||||
break;
|
||||
case MOS65XX_AM_BLOCK:
|
||||
MCOperand_CreateImm0(MI, code[2]);
|
||||
MCOperand_CreateImm0(MI, code[1]);
|
||||
break;
|
||||
case MOS65XX_AM_IMP:
|
||||
case MOS65XX_AM_ACC:
|
||||
break;
|
||||
|
||||
case MOS65XX_AM_IMM:
|
||||
MI->has_imm = 1;
|
||||
MI->imm_size = len - 1;
|
||||
/* 65816 immediate is either 1 or 2 bytes */
|
||||
/* drop through */
|
||||
default:
|
||||
if (len == 2)
|
||||
MCOperand_CreateImm0(MI, code[1]);
|
||||
else if (len == 3)
|
||||
MCOperand_CreateImm0(MI, (code[2]<<8) | code[1]);
|
||||
else if (len == 4)
|
||||
MCOperand_CreateImm0(MI, (code[3]<<16) | (code[2]<<8) | code[1]);
|
||||
break;
|
||||
}
|
||||
|
||||
#ifndef CAPSTONE_DIET
|
||||
if (MI->flat_insn->detail) {
|
||||
fillDetails(MI, opinfo, cpu_type);
|
||||
}
|
||||
#endif
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
const char *MOS65XX_insn_name(csh handle, unsigned int id)
|
||||
{
|
||||
#ifdef CAPSTONE_DIET
|
||||
return NULL;
|
||||
#else
|
||||
if (id >= ARR_SIZE(InstructionInfoTable)) {
|
||||
return NULL;
|
||||
}
|
||||
return InstructionInfoTable[id].name;
|
||||
#endif
|
||||
}
|
||||
|
||||
const char* MOS65XX_reg_name(csh handle, unsigned int reg)
|
||||
{
|
||||
#ifdef CAPSTONE_DIET
|
||||
return NULL;
|
||||
#else
|
||||
if (reg >= ARR_SIZE(RegNames)) {
|
||||
return NULL;
|
||||
}
|
||||
return RegNames[(int)reg];
|
||||
#endif
|
||||
}
|
||||
|
||||
void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
|
||||
{
|
||||
/* id is cpu_offset + opcode */
|
||||
if (id < ARR_SIZE(OpInfoTable)) {
|
||||
insn->id = OpInfoTable[id].ins;
|
||||
}
|
||||
}
|
||||
|
||||
const char *MOS65XX_group_name(csh handle, unsigned int id)
|
||||
{
|
||||
#ifdef CAPSTONE_DIET
|
||||
return NULL;
|
||||
#else
|
||||
if (id >= ARR_SIZE(GroupNames)) {
|
||||
return NULL;
|
||||
}
|
||||
return GroupNames[(int)id];
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,22 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */
|
||||
|
||||
#ifndef CAPSTONE_MOS65XXDISASSEMBLER_H
|
||||
#define CAPSTONE_MOS65XXDISASSEMBLER_H
|
||||
|
||||
#include "../../utils.h"
|
||||
|
||||
void MOS65XX_printInst(MCInst *MI, struct SStream *O, void *PrinterInfo);
|
||||
|
||||
void MOS65XX_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
|
||||
|
||||
const char *MOS65XX_insn_name(csh handle, unsigned int id);
|
||||
|
||||
const char *MOS65XX_group_name(csh handle, unsigned int id);
|
||||
|
||||
const char* MOS65XX_reg_name(csh handle, unsigned int reg);
|
||||
|
||||
bool MOS65XX_getInstruction(csh ud, const uint8_t *code, size_t code_len,
|
||||
MCInst *MI, uint16_t *size, uint64_t address, void *inst_info);
|
||||
|
||||
#endif //CAPSTONE_MOS65XXDISASSEMBLER_H
|
||||
@@ -0,0 +1,23 @@
|
||||
#ifndef CS_MOS65XXDISASSEMBLERINTERNALS_H
|
||||
#define CS_MOS65XXDISASSEMBLERINTERNALS_H
|
||||
|
||||
#include "capstone/mos65xx.h"
|
||||
|
||||
enum {
|
||||
MOS65XX_CPU_TYPE_6502,
|
||||
MOS65XX_CPU_TYPE_65C02,
|
||||
MOS65XX_CPU_TYPE_W65C02,
|
||||
MOS65XX_CPU_TYPE_65816,
|
||||
};
|
||||
|
||||
typedef struct mos65xx_info {
|
||||
|
||||
const char *hex_prefix;
|
||||
unsigned cpu_type;
|
||||
unsigned long_m;
|
||||
unsigned long_x;
|
||||
|
||||
} mos65xx_info;
|
||||
|
||||
|
||||
#endif
|
||||
+79
@@ -0,0 +1,79 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* MOS65XX Backend by Sebastian Macke <sebastian@macke.de> 2018 */
|
||||
|
||||
#ifdef CAPSTONE_HAS_MOS65XX
|
||||
|
||||
#include "../../utils.h"
|
||||
#include "../../MCRegisterInfo.h"
|
||||
#include "MOS65XXDisassembler.h"
|
||||
#include "MOS65XXDisassemblerInternals.h"
|
||||
#include "MOS65XXModule.h"
|
||||
|
||||
cs_err MOS65XX_global_init(cs_struct *ud)
|
||||
{
|
||||
mos65xx_info *info;
|
||||
|
||||
info = cs_mem_malloc(sizeof(*info));
|
||||
info->hex_prefix = NULL;
|
||||
info->cpu_type = MOS65XX_CPU_TYPE_6502;
|
||||
info->long_m = 0;
|
||||
info->long_x = 0;
|
||||
|
||||
|
||||
ud->printer = MOS65XX_printInst;
|
||||
ud->printer_info = info;
|
||||
ud->insn_id = MOS65XX_get_insn_id;
|
||||
ud->insn_name = MOS65XX_insn_name;
|
||||
ud->group_name = MOS65XX_group_name;
|
||||
ud->disasm = MOS65XX_getInstruction;
|
||||
ud->reg_name = MOS65XX_reg_name;
|
||||
|
||||
if (ud->mode) {
|
||||
MOS65XX_option(ud, CS_OPT_MODE, ud->mode);
|
||||
}
|
||||
|
||||
return CS_ERR_OK;
|
||||
}
|
||||
|
||||
cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value)
|
||||
{
|
||||
mos65xx_info *info = (mos65xx_info *)handle->printer_info;
|
||||
switch(type) {
|
||||
default:
|
||||
break;
|
||||
case CS_OPT_MODE:
|
||||
|
||||
if (value & CS_MODE_MOS65XX_6502)
|
||||
info->cpu_type = MOS65XX_CPU_TYPE_6502;
|
||||
if (value & CS_MODE_MOS65XX_65C02)
|
||||
info->cpu_type = MOS65XX_CPU_TYPE_65C02;
|
||||
if (value & CS_MODE_MOS65XX_W65C02)
|
||||
info->cpu_type = MOS65XX_CPU_TYPE_W65C02;
|
||||
if (value & (CS_MODE_MOS65XX_65816|CS_MODE_MOS65XX_65816_LONG_M|CS_MODE_MOS65XX_65816_LONG_X))
|
||||
info->cpu_type = MOS65XX_CPU_TYPE_65816;
|
||||
|
||||
info->long_m = value & CS_MODE_MOS65XX_65816_LONG_M ? 1 : 0;
|
||||
info->long_x = value & CS_MODE_MOS65XX_65816_LONG_X ? 1 : 0;
|
||||
|
||||
handle->mode = (cs_mode)value; // NOLINT(clang-analyzer-optin.core.EnumCastOutOfRange)
|
||||
break;
|
||||
case CS_OPT_SYNTAX:
|
||||
switch(value) {
|
||||
default:
|
||||
// wrong syntax value
|
||||
handle->errnum = CS_ERR_OPTION;
|
||||
return CS_ERR_OPTION;
|
||||
case CS_OPT_SYNTAX_DEFAULT:
|
||||
info->hex_prefix = NULL;
|
||||
break;
|
||||
case CS_OPT_SYNTAX_MOTOROLA:
|
||||
info->hex_prefix = "$";
|
||||
break;
|
||||
}
|
||||
handle->syntax = (int)value;
|
||||
break;
|
||||
}
|
||||
return CS_ERR_OK;
|
||||
}
|
||||
|
||||
#endif
|
||||
+12
@@ -0,0 +1,12 @@
|
||||
/* Capstone Disassembly Engine */
|
||||
/* By Sebastian Macke <sebastian@macke.de>, 2018 */
|
||||
|
||||
#ifndef CS_MOS65XX_MODULE_H
|
||||
#define CS_MOS65XX_MODULE_H
|
||||
|
||||
#include "../../utils.h"
|
||||
|
||||
cs_err MOS65XX_global_init(cs_struct *ud);
|
||||
cs_err MOS65XX_option(cs_struct *handle, cs_opt_type type, size_t value);
|
||||
|
||||
#endif
|
||||
+106
@@ -0,0 +1,106 @@
|
||||
/*
|
||||
* MOS65XX_GRP_BRANCH_RELATIVE handled elsewhere based on address mode
|
||||
* MOS65XX_REG_SP handled elsewhere for push/pop instructions
|
||||
* BLOCK moves handled elsewhere.
|
||||
* MOS65XX_REG_Y handled elsewhere for abs,y zp, y etc
|
||||
* MOS65XX_REG_X handled elsewhere for abs,x zp, x etc
|
||||
* MOS65XX_REG_DP handled elsewhere for zp zp,x zp,y etc
|
||||
*/
|
||||
|
||||
{ "invalid", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "adc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
|
||||
{ "and", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
|
||||
{ "asl", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "bbr", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bbs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bcc", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bcs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "beq", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bit", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
|
||||
{ "bmi", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bne", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bpl", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bra", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "brk", MOS65XX_GRP_INT, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "brl", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "bvc", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "bvs", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "clc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "cld", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "cli", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "clv", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "cmp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
|
||||
{ "cop", MOS65XX_GRP_INT, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "cpx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, true },
|
||||
{ "cpy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, true },
|
||||
{ "dec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "dex", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true },
|
||||
{ "dey", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true },
|
||||
{ "eor", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
|
||||
{ "inc", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "inx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_X, true },
|
||||
{ "iny", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_Y, true },
|
||||
{ "jml", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "jmp", MOS65XX_GRP_JUMP, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "jsl", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "jsr", MOS65XX_GRP_CALL, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "lda", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
|
||||
{ "ldx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true },
|
||||
{ "ldy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true },
|
||||
{ "lsr", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "mvn", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "mvp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "nop", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "ora", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
|
||||
{ "pea", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "pei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "per", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "pha", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false },
|
||||
{ "phb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_B, false },
|
||||
{ "phd", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_DP, false },
|
||||
{ "phk", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_K, false },
|
||||
{ "php", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_P, false },
|
||||
{ "phx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false },
|
||||
{ "phy", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false },
|
||||
{ "pla", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_INVALID, true },
|
||||
{ "plb", MOS65XX_GRP_INVALID, MOS65XX_REG_B, MOS65XX_REG_INVALID, true },
|
||||
{ "pld", MOS65XX_GRP_INVALID, MOS65XX_REG_DP, MOS65XX_REG_INVALID, true },
|
||||
{ "plp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "plx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_INVALID, true },
|
||||
{ "ply", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_INVALID, true },
|
||||
{ "rep", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "rmb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "rol", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "ror", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "rti", MOS65XX_GRP_IRET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "rtl", MOS65XX_GRP_RET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "rts", MOS65XX_GRP_RET, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "sbc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
|
||||
{ "sec", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "sed", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "sei", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "sep", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
{ "smb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "sta", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, false },
|
||||
{ "stp", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "stx", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_X, false },
|
||||
{ "sty", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_Y, false },
|
||||
{ "stz", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "tax", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_ACC, true },
|
||||
{ "tay", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_ACC, true },
|
||||
{ "tcd", MOS65XX_GRP_INVALID, MOS65XX_REG_DP, MOS65XX_REG_ACC, true },
|
||||
{ "tcs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_ACC, false },
|
||||
{ "tdc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_DP, true },
|
||||
{ "trb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
|
||||
{ "tsb", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_ACC, true },
|
||||
{ "tsc", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_SP, true },
|
||||
{ "tsx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_SP, true },
|
||||
{ "txa", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_X, true },
|
||||
{ "txs", MOS65XX_GRP_INVALID, MOS65XX_REG_SP, MOS65XX_REG_X, false },
|
||||
{ "txy", MOS65XX_GRP_INVALID, MOS65XX_REG_Y, MOS65XX_REG_X, true },
|
||||
{ "tya", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_Y, true },
|
||||
{ "tyx", MOS65XX_GRP_INVALID, MOS65XX_REG_X, MOS65XX_REG_Y, true },
|
||||
{ "wai", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "wdm", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, false },
|
||||
{ "xba", MOS65XX_GRP_INVALID, MOS65XX_REG_ACC, MOS65XX_REG_ACC, true },
|
||||
{ "xce", MOS65XX_GRP_INVALID, MOS65XX_REG_INVALID, MOS65XX_REG_INVALID, true },
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x02
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x03
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x04
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x07
|
||||
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0b
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x0f
|
||||
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x12
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x13
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x14
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x17
|
||||
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1b
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x1f
|
||||
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x22
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x23
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x27
|
||||
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x2b
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x2f
|
||||
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x32
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x33
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x34
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x37
|
||||
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3b
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x3f
|
||||
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x42
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x43
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x44
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x47
|
||||
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x4b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x4f
|
||||
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x52
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x53
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x54
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x57
|
||||
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5b
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x5f
|
||||
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x62
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x63
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x64
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x67
|
||||
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x6b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x6f
|
||||
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x72
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x73
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x74
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x77
|
||||
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7b
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x7f
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x80
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x82
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x83
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x87
|
||||
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x89
|
||||
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x8b
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x8f
|
||||
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x92
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x93
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x97
|
||||
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
|
||||
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9b
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9e
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0x9f
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xa3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xa7
|
||||
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
|
||||
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xab
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xaf
|
||||
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb2
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xb7
|
||||
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
|
||||
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xbb
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xbf
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc2
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc3
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xc7
|
||||
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
|
||||
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xcb
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xcf
|
||||
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd2
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd3
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xd7
|
||||
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xda
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdb
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xdf
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe2
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe3
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xe7
|
||||
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xeb
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xef
|
||||
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf2
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf3
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xf7
|
||||
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfa
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfb
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xfc
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
|
||||
{ MOS65XX_INS_INVALID, MOS65XX_AM_NONE , 0 }, // 0xff
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
|
||||
{ MOS65XX_INS_COP , MOS65XX_AM_INT , 1 }, // 0x02
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_SR , 1 }, // 0x03
|
||||
{ MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x07
|
||||
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
|
||||
{ MOS65XX_INS_PHD , MOS65XX_AM_IMP , 0 }, // 0x0b
|
||||
{ MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_LONG , 3 }, // 0x0f
|
||||
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_SR_IND_Y , 1 }, // 0x13
|
||||
{ MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x17
|
||||
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a
|
||||
{ MOS65XX_INS_TCS , MOS65XX_AM_IMP , 0 }, // 0x1b
|
||||
{ MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x1f
|
||||
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
|
||||
{ MOS65XX_INS_JSL , MOS65XX_AM_ABS_LONG , 3 }, // 0x22
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_SR , 1 }, // 0x23
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x27
|
||||
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
|
||||
{ MOS65XX_INS_PLD , MOS65XX_AM_IMP , 0 }, // 0x2b
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_LONG , 3 }, // 0x2f
|
||||
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_SR_IND_Y , 1 }, // 0x33
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x37
|
||||
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a
|
||||
{ MOS65XX_INS_TSC , MOS65XX_AM_IMP , 0 }, // 0x3b
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x3f
|
||||
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
|
||||
{ MOS65XX_INS_WDM , MOS65XX_AM_INT , 1 }, // 0x42
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_SR , 1 }, // 0x43
|
||||
{ MOS65XX_INS_MVP , MOS65XX_AM_BLOCK , 2 }, // 0x44
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x47
|
||||
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
|
||||
{ MOS65XX_INS_PHK , MOS65XX_AM_IMP , 0 }, // 0x4b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_LONG , 3 }, // 0x4f
|
||||
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_SR_IND_Y , 1 }, // 0x53
|
||||
{ MOS65XX_INS_MVN , MOS65XX_AM_BLOCK , 2 }, // 0x54
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x57
|
||||
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
|
||||
{ MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a
|
||||
{ MOS65XX_INS_TCD , MOS65XX_AM_IMP , 0 }, // 0x5b
|
||||
{ MOS65XX_INS_JML , MOS65XX_AM_ABS_LONG , 3 }, // 0x5c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x5f
|
||||
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
|
||||
{ MOS65XX_INS_PER , MOS65XX_AM_REL , 2 }, // 0x62
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_SR , 1 }, // 0x63
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x67
|
||||
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
|
||||
{ MOS65XX_INS_RTL , MOS65XX_AM_IMP , 0 }, // 0x6b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_LONG , 3 }, // 0x6f
|
||||
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_SR_IND_Y , 1 }, // 0x73
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x77
|
||||
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
|
||||
{ MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a
|
||||
{ MOS65XX_INS_TDC , MOS65XX_AM_IMP , 0 }, // 0x7b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x7f
|
||||
{ MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
|
||||
{ MOS65XX_INS_BRL , MOS65XX_AM_REL , 2 }, // 0x82
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_SR , 1 }, // 0x83
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0x87
|
||||
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89
|
||||
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
|
||||
{ MOS65XX_INS_PHB , MOS65XX_AM_IMP , 0 }, // 0x8b
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_LONG , 3 }, // 0x8f
|
||||
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_SR_IND_Y , 1 }, // 0x93
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0x97
|
||||
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
|
||||
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
|
||||
{ MOS65XX_INS_TXY , MOS65XX_AM_IMP , 0 }, // 0x9b
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0x9f
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_SR , 1 }, // 0xa3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xa7
|
||||
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
|
||||
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
|
||||
{ MOS65XX_INS_PLB , MOS65XX_AM_IMP , 0 }, // 0xab
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_LONG , 3 }, // 0xaf
|
||||
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_SR_IND_Y , 1 }, // 0xb3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xb7
|
||||
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
|
||||
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
|
||||
{ MOS65XX_INS_TYX , MOS65XX_AM_IMP , 0 }, // 0xbb
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xbf
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
|
||||
{ MOS65XX_INS_REP , MOS65XX_AM_IMM , 1 }, // 0xc2
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_SR , 1 }, // 0xc3
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xc7
|
||||
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
|
||||
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
|
||||
{ MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_LONG , 3 }, // 0xcf
|
||||
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_SR_IND_Y , 1 }, // 0xd3
|
||||
{ MOS65XX_INS_PEI , MOS65XX_AM_ZP_IND , 1 }, // 0xd4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xd7
|
||||
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
|
||||
{ MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda
|
||||
{ MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb
|
||||
{ MOS65XX_INS_JML , MOS65XX_AM_ABS_IND_LONG , 2 }, // 0xdc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xdf
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
|
||||
{ MOS65XX_INS_SEP , MOS65XX_AM_IMM , 1 }, // 0xe2
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_SR , 1 }, // 0xe3
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_LONG , 1 }, // 0xe7
|
||||
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
|
||||
{ MOS65XX_INS_XBA , MOS65XX_AM_IMP , 0 }, // 0xeb
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_LONG , 3 }, // 0xef
|
||||
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_SR_IND_Y , 1 }, // 0xf3
|
||||
{ MOS65XX_INS_PEA , MOS65XX_AM_ABS , 2 }, // 0xf4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_LONG_Y, 1 }, // 0xf7
|
||||
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
|
||||
{ MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa
|
||||
{ MOS65XX_INS_XCE , MOS65XX_AM_IMP , 0 }, // 0xfb
|
||||
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS_X_IND , 2 }, // 0xfc
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_LONG_X , 3 }, // 0xff
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x02
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x03
|
||||
{ MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x07
|
||||
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0b
|
||||
{ MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0f
|
||||
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x13
|
||||
{ MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x17
|
||||
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1b
|
||||
{ MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1f
|
||||
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x22
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x23
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x27
|
||||
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2b
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2f
|
||||
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x33
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x37
|
||||
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3b
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3f
|
||||
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x42
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x43
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x44
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x47
|
||||
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4f
|
||||
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x53
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x54
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x57
|
||||
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
|
||||
{ MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5b
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0x5c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5f
|
||||
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x62
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x63
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x67
|
||||
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6f
|
||||
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x73
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x77
|
||||
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
|
||||
{ MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7f
|
||||
{ MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x82
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x83
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x87
|
||||
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89
|
||||
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8b
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8f
|
||||
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x93
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x97
|
||||
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
|
||||
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9b
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9f
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa7
|
||||
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
|
||||
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xab
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xaf
|
||||
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb7
|
||||
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
|
||||
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbb
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbf
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xc2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc3
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc7
|
||||
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
|
||||
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
|
||||
{ MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xcf
|
||||
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd3
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xd4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd7
|
||||
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
|
||||
{ MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda
|
||||
{ MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xdc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xdf
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xe2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe3
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe7
|
||||
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xeb
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xef
|
||||
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf3
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xf4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf7
|
||||
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
|
||||
{ MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xfb
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xfc
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xff
|
||||
+256
@@ -0,0 +1,256 @@
|
||||
{ MOS65XX_INS_BRK , MOS65XX_AM_INT , 1 }, // 0x00
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x01
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x02
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x03
|
||||
{ MOS65XX_INS_TSB , MOS65XX_AM_ZP , 1 }, // 0x04
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP , 1 }, // 0x05
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP , 1 }, // 0x06
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x07
|
||||
{ MOS65XX_INS_PHP , MOS65XX_AM_IMP , 0 }, // 0x08
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_IMM , 1 }, // 0x09
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ACC , 0 }, // 0x0a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x0b
|
||||
{ MOS65XX_INS_TSB , MOS65XX_AM_ABS , 2 }, // 0x0c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS , 2 }, // 0x0d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS , 2 }, // 0x0e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x0f
|
||||
{ MOS65XX_INS_BPL , MOS65XX_AM_REL , 1 }, // 0x10
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x11
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_IND , 1 }, // 0x12
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x13
|
||||
{ MOS65XX_INS_TRB , MOS65XX_AM_ZP , 1 }, // 0x14
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ZP_X , 1 }, // 0x15
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ZP_X , 1 }, // 0x16
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x17
|
||||
{ MOS65XX_INS_CLC , MOS65XX_AM_IMP , 0 }, // 0x18
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_Y , 2 }, // 0x19
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ACC , 0 }, // 0x1a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x1b
|
||||
{ MOS65XX_INS_TRB , MOS65XX_AM_ABS , 2 }, // 0x1c
|
||||
{ MOS65XX_INS_ORA , MOS65XX_AM_ABS_X , 2 }, // 0x1d
|
||||
{ MOS65XX_INS_ASL , MOS65XX_AM_ABS_X , 2 }, // 0x1e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x1f
|
||||
{ MOS65XX_INS_JSR , MOS65XX_AM_ABS , 2 }, // 0x20
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X_IND , 1 }, // 0x21
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x22
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x23
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP , 1 }, // 0x24
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP , 1 }, // 0x25
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP , 1 }, // 0x26
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x27
|
||||
{ MOS65XX_INS_PLP , MOS65XX_AM_IMP , 0 }, // 0x28
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_IMM , 1 }, // 0x29
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ACC , 0 }, // 0x2a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x2b
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS , 2 }, // 0x2c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS , 2 }, // 0x2d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS , 2 }, // 0x2e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x2f
|
||||
{ MOS65XX_INS_BMI , MOS65XX_AM_REL , 1 }, // 0x30
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x31
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_IND , 1 }, // 0x32
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x33
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ZP_X , 1 }, // 0x34
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ZP_X , 1 }, // 0x35
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ZP_X , 1 }, // 0x36
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x37
|
||||
{ MOS65XX_INS_SEC , MOS65XX_AM_IMP , 0 }, // 0x38
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_Y , 2 }, // 0x39
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ACC , 0 }, // 0x3a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x3b
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_ABS_X , 2 }, // 0x3c
|
||||
{ MOS65XX_INS_AND , MOS65XX_AM_ABS_X , 2 }, // 0x3d
|
||||
{ MOS65XX_INS_ROL , MOS65XX_AM_ABS_X , 2 }, // 0x3e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x3f
|
||||
{ MOS65XX_INS_RTI , MOS65XX_AM_IMP , 0 }, // 0x40
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X_IND , 1 }, // 0x41
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x42
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x43
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x44
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP , 1 }, // 0x45
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP , 1 }, // 0x46
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x47
|
||||
{ MOS65XX_INS_PHA , MOS65XX_AM_IMP , 0 }, // 0x48
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_IMM , 1 }, // 0x49
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ACC , 0 }, // 0x4a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x4b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS , 2 }, // 0x4c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS , 2 }, // 0x4d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS , 2 }, // 0x4e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x4f
|
||||
{ MOS65XX_INS_BVC , MOS65XX_AM_REL , 1 }, // 0x50
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x51
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_IND , 1 }, // 0x52
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x53
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x54
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ZP_X , 1 }, // 0x55
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ZP_X , 1 }, // 0x56
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x57
|
||||
{ MOS65XX_INS_CLI , MOS65XX_AM_IMP , 0 }, // 0x58
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_Y , 2 }, // 0x59
|
||||
{ MOS65XX_INS_PHY , MOS65XX_AM_IMP , 0 }, // 0x5a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x5b
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0x5c
|
||||
{ MOS65XX_INS_EOR , MOS65XX_AM_ABS_X , 2 }, // 0x5d
|
||||
{ MOS65XX_INS_LSR , MOS65XX_AM_ABS_X , 2 }, // 0x5e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x5f
|
||||
{ MOS65XX_INS_RTS , MOS65XX_AM_IMP , 0 }, // 0x60
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X_IND , 1 }, // 0x61
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x62
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x63
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP , 1 }, // 0x64
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP , 1 }, // 0x65
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP , 1 }, // 0x66
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x67
|
||||
{ MOS65XX_INS_PLA , MOS65XX_AM_IMP , 0 }, // 0x68
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_IMM , 1 }, // 0x69
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ACC , 0 }, // 0x6a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x6b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_IND , 2 }, // 0x6c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS , 2 }, // 0x6d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS , 2 }, // 0x6e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x6f
|
||||
{ MOS65XX_INS_BVS , MOS65XX_AM_REL , 1 }, // 0x70
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x71
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_IND , 1 }, // 0x72
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x73
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ZP_X , 1 }, // 0x74
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ZP_X , 1 }, // 0x75
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ZP_X , 1 }, // 0x76
|
||||
{ MOS65XX_INS_RMB , MOS65XX_AM_ZP , 1 }, // 0x77
|
||||
{ MOS65XX_INS_SEI , MOS65XX_AM_IMP , 0 }, // 0x78
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_Y , 2 }, // 0x79
|
||||
{ MOS65XX_INS_PLY , MOS65XX_AM_IMP , 0 }, // 0x7a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x7b
|
||||
{ MOS65XX_INS_JMP , MOS65XX_AM_ABS_X_IND , 2 }, // 0x7c
|
||||
{ MOS65XX_INS_ADC , MOS65XX_AM_ABS_X , 2 }, // 0x7d
|
||||
{ MOS65XX_INS_ROR , MOS65XX_AM_ABS_X , 2 }, // 0x7e
|
||||
{ MOS65XX_INS_BBR , MOS65XX_AM_ZP_REL , 2 }, // 0x7f
|
||||
{ MOS65XX_INS_BRA , MOS65XX_AM_REL , 1 }, // 0x80
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X_IND , 1 }, // 0x81
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0x82
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x83
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP , 1 }, // 0x84
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP , 1 }, // 0x85
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP , 1 }, // 0x86
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0x87
|
||||
{ MOS65XX_INS_DEY , MOS65XX_AM_IMP , 0 }, // 0x88
|
||||
{ MOS65XX_INS_BIT , MOS65XX_AM_IMM , 1 }, // 0x89
|
||||
{ MOS65XX_INS_TXA , MOS65XX_AM_IMP , 0 }, // 0x8a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x8b
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ABS , 2 }, // 0x8c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS , 2 }, // 0x8d
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ABS , 2 }, // 0x8e
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0x8f
|
||||
{ MOS65XX_INS_BCC , MOS65XX_AM_REL , 1 }, // 0x90
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0x91
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_IND , 1 }, // 0x92
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x93
|
||||
{ MOS65XX_INS_STY , MOS65XX_AM_ZP_X , 1 }, // 0x94
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ZP_X , 1 }, // 0x95
|
||||
{ MOS65XX_INS_STX , MOS65XX_AM_ZP_Y , 1 }, // 0x96
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0x97
|
||||
{ MOS65XX_INS_TYA , MOS65XX_AM_IMP , 0 }, // 0x98
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_Y , 2 }, // 0x99
|
||||
{ MOS65XX_INS_TXS , MOS65XX_AM_IMP , 0 }, // 0x9a
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0x9b
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS , 2 }, // 0x9c
|
||||
{ MOS65XX_INS_STA , MOS65XX_AM_ABS_X , 2 }, // 0x9d
|
||||
{ MOS65XX_INS_STZ , MOS65XX_AM_ABS_X , 2 }, // 0x9e
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0x9f
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_IMM , 1 }, // 0xa0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X_IND , 1 }, // 0xa1
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_IMM , 1 }, // 0xa2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xa3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP , 1 }, // 0xa4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP , 1 }, // 0xa5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP , 1 }, // 0xa6
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xa7
|
||||
{ MOS65XX_INS_TAY , MOS65XX_AM_IMP , 0 }, // 0xa8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_IMM , 1 }, // 0xa9
|
||||
{ MOS65XX_INS_TAX , MOS65XX_AM_IMP , 0 }, // 0xaa
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xab
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS , 2 }, // 0xac
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS , 2 }, // 0xad
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS , 2 }, // 0xae
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xaf
|
||||
{ MOS65XX_INS_BCS , MOS65XX_AM_REL , 1 }, // 0xb0
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xb1
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_IND , 1 }, // 0xb2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xb3
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ZP_X , 1 }, // 0xb4
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ZP_X , 1 }, // 0xb5
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ZP_Y , 1 }, // 0xb6
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xb7
|
||||
{ MOS65XX_INS_CLV , MOS65XX_AM_IMP , 0 }, // 0xb8
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_Y , 2 }, // 0xb9
|
||||
{ MOS65XX_INS_TSX , MOS65XX_AM_IMP , 0 }, // 0xba
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xbb
|
||||
{ MOS65XX_INS_LDY , MOS65XX_AM_ABS_X , 2 }, // 0xbc
|
||||
{ MOS65XX_INS_LDA , MOS65XX_AM_ABS_X , 2 }, // 0xbd
|
||||
{ MOS65XX_INS_LDX , MOS65XX_AM_ABS_Y , 2 }, // 0xbe
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xbf
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_IMM , 1 }, // 0xc0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X_IND , 1 }, // 0xc1
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xc2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xc3
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ZP , 1 }, // 0xc4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP , 1 }, // 0xc5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP , 1 }, // 0xc6
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xc7
|
||||
{ MOS65XX_INS_INY , MOS65XX_AM_IMP , 0 }, // 0xc8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_IMM , 1 }, // 0xc9
|
||||
{ MOS65XX_INS_DEX , MOS65XX_AM_IMP , 0 }, // 0xca
|
||||
{ MOS65XX_INS_WAI , MOS65XX_AM_IMP , 0 }, // 0xcb
|
||||
{ MOS65XX_INS_CPY , MOS65XX_AM_ABS , 2 }, // 0xcc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS , 2 }, // 0xcd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS , 2 }, // 0xce
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xcf
|
||||
{ MOS65XX_INS_BNE , MOS65XX_AM_REL , 1 }, // 0xd0
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xd1
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_IND , 1 }, // 0xd2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xd3
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xd4
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ZP_X , 1 }, // 0xd5
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ZP_X , 1 }, // 0xd6
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xd7
|
||||
{ MOS65XX_INS_CLD , MOS65XX_AM_IMP , 0 }, // 0xd8
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_Y , 2 }, // 0xd9
|
||||
{ MOS65XX_INS_PHX , MOS65XX_AM_IMP , 0 }, // 0xda
|
||||
{ MOS65XX_INS_STP , MOS65XX_AM_IMP , 0 }, // 0xdb
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xdc
|
||||
{ MOS65XX_INS_CMP , MOS65XX_AM_ABS_X , 2 }, // 0xdd
|
||||
{ MOS65XX_INS_DEC , MOS65XX_AM_ABS_X , 2 }, // 0xde
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xdf
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_IMM , 1 }, // 0xe0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X_IND , 1 }, // 0xe1
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xe2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xe3
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ZP , 1 }, // 0xe4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP , 1 }, // 0xe5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP , 1 }, // 0xe6
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xe7
|
||||
{ MOS65XX_INS_INX , MOS65XX_AM_IMP , 0 }, // 0xe8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_IMM , 1 }, // 0xe9
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xea
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xeb
|
||||
{ MOS65XX_INS_CPX , MOS65XX_AM_ABS , 2 }, // 0xec
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS , 2 }, // 0xed
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS , 2 }, // 0xee
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xef
|
||||
{ MOS65XX_INS_BEQ , MOS65XX_AM_REL , 1 }, // 0xf0
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND_Y , 1 }, // 0xf1
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_IND , 1 }, // 0xf2
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xf3
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 1 }, // 0xf4
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ZP_X , 1 }, // 0xf5
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ZP_X , 1 }, // 0xf6
|
||||
{ MOS65XX_INS_SMB , MOS65XX_AM_ZP , 1 }, // 0xf7
|
||||
{ MOS65XX_INS_SED , MOS65XX_AM_IMP , 0 }, // 0xf8
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_Y , 2 }, // 0xf9
|
||||
{ MOS65XX_INS_PLX , MOS65XX_AM_IMP , 0 }, // 0xfa
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 0 }, // 0xfb
|
||||
{ MOS65XX_INS_NOP , MOS65XX_AM_IMP , 2 }, // 0xfc
|
||||
{ MOS65XX_INS_SBC , MOS65XX_AM_ABS_X , 2 }, // 0xfd
|
||||
{ MOS65XX_INS_INC , MOS65XX_AM_ABS_X , 2 }, // 0xfe
|
||||
{ MOS65XX_INS_BBS , MOS65XX_AM_ZP_REL , 2 }, // 0xff
|
||||
Reference in New Issue
Block a user