iris/kaizen
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd

Browse Source 
de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
This commit is contained in:
iris
2026-06-15 11:56:38 +02:00
parent ce3cd726c8
commit 00cc9309cb
4479 changed files with 2943227 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files
external/capstone/arch/Mips/MipsCP0RegisterMap.h
Vendored
+190
View File
@@ -0,0 +1,190 @@
//===- MipsCP0RegisterMap.h - Co-processor register names for Mips/nanoMIPS -===//
// This has been created by hand.
#ifndef LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
#define LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
struct CP0SelRegister_t {
const char *Name;
int RegNum;
int Select;
int Index;
};
static const struct CP0SelRegister_t CP0SelRegs[] = {
{"index", 0, 0},
{"mvpcontrol", 0, 1},
{"mvpconf0", 0, 2},
{"mvpconf1", 0, 3},
{"vpcontrol", 0, 4},
{"random", 1, 0},
{"vpecontrol", 1, 1},
{"vpeconf0", 1, 2},
{"vpeconf1", 1, 3},
{"yqmask", 1, 4},
{"vpeschedule", 1, 5},
{"vpeschefback", 1, 6},
{"vpeopt", 1, 7},
{"entrylo0", 2, 0},
{"tcstatus", 2, 1},
{"tcbind", 2, 2},
{"tcrestart", 2, 3},
{"tchalt", 2, 4},
{"tccontext", 2, 5},
{"tcschedule", 2, 6},
{"tcschefback", 2, 7},
{"entrylo1", 3, 0},
{"globalnumber", 3, 1},
{"tcopt", 3, 7},
{"context", 4, 0},
{"contextconfig", 4, 1},
{"userlocal", 4, 2},
{"xcontextconfig", 4, 3},
{"debugcontextid", 4, 4},
{"memorymapid", 4, 5},
{"pagemask", 5, 0},
{"pagegrain", 5, 1},
{"segctl0", 5, 2},
{"segctl1", 5, 3},
{"segctl2", 5, 4},
{"pwbase", 5, 5},
{"pwfield", 5, 6},
{"pwsize", 5, 7},
{"wired", 6, 0},
{"srsconf0", 6, 1},
{"srsconf1", 6, 2},
{"srsconf2", 6, 3},
{"srsconf3", 6, 4},
{"srsconf4", 6, 5},
{"pwctl", 6, 6},
{"hwrena", 7, 0},
{"badvaddr", 8, 0},
{"badinst", 8, 1},
{"badinstrp", 8, 2},
{"badinstrx", 8, 3},
{"count", 9, 0},
{"entryhi", 10, 0},
{"guestctl1", 10, 4},
{"guestctl2", 10, 5},
{"guestctl3", 10, 6},
{"compare", 11, 0},
{"guestctl0ext", 11, 4},
{"status", 12, 0},
{"intctl", 12, 1},
{"srsctl", 12, 2},
{"srsmap", 12, 3},
{"view_ipl", 12, 4},
{"srsmap2", 12, 5},
{"guestctl0", 12, 6},
{"gtoffset", 12, 7},
{"cause", 13, 0},
{"view_ripl", 13, 4},
{"nestedexc", 13, 5},
{"epc", 14, 0},
{"nestedepc", 14, 2},
{"prid", 15, 0},
{"ebase", 15, 1},
{"cdmmbase", 15, 2},
{"cmgcrbase", 15, 3},
{"bevva", 15, 4},
{"config", 16, 0},
{"config1", 16, 1},
{"config2", 16, 2},
{"config3", 16, 3},
{"config4", 16, 4},
{"config5", 16, 5},
{"lladdr", 17, 0},
{"maar", 17, 1},
{"maari", 17, 2},
{"watchlo0", 18, 0},
{"watchlo1", 18, 1},
{"watchlo2", 18, 2},
{"watchlo3", 18, 3},
{"watchlo4", 18, 4},
{"watchlo5", 18, 5},
{"watchlo6", 18, 6},
{"watchlo7", 18, 7},
{"watchlo8", 18, 8},
{"watchlo9", 18, 9},
{"watchlo10", 18,10},
{"watchlo11", 18,11},
{"watchlo12", 18,12},
{"watchlo13", 18,13},
{"watchlo14", 18,14},
{"watchlo15", 18,15},
{"watchhi0", 19, 0},
{"watchhi1", 19, 1},
{"watchhi2", 19, 2},
{"watchhi3", 19, 3},
{"watchhi4", 19, 4},
{"watchhi5", 19, 5},
{"watchhi6", 19, 6},
{"watchhi7", 19, 7},
{"watchhi8", 19, 8},
{"watchhi9", 19, 9},
{"watchhi10", 19,10},
{"watchhi11", 19,11},
{"watchhi12", 19,12},
{"watchhi13", 19,13},
{"watchhi14", 19,14},
{"watchhi15", 19,15},
{"xcontext", 20, 0},
{"debug", 23, 0},
{"tracecontrol", 23, 1},
{"tracecontrol2", 23, 2},
{"usertracedata1", 23, 3},
{"traceibpc", 23, 4},
{"tracedbpc", 23, 5},
{"debug2", 23, 6},
{"depc", 24, 0},
{"tracecontrol3", 24, 2},
{"usertracedata2", 24, 3},
{"perfctl0", 25, 0},
{"perfcnt0", 25, 1},
{"perfctl1", 25, 2},
{"perfcnt1", 25, 3},
{"perfctl2", 25, 4},
{"perfcnt2", 25, 5},
{"perfctl3", 25, 6},
{"perfcnt3", 25, 7},
{"perfctl4", 25, 8},
{"perfcnt4", 25, 9},
{"perfctl5", 25,10},
{"perfcnt5", 25,11},
{"perfctl6", 25,12},
{"perfcnt6", 25,13},
{"perfctl7", 25,14},
{"perfcnt7", 25,15},
{"errctl", 26, 0},
{"cacheerr", 27, 0},
{"itaglo", 28, 0},
{"idatalo", 28, 1},
{"dtaglo", 28, 2},
{"ddatalo", 28, 3},
{"itaghi", 29, 0},
{"idatahi", 29, 1},
{"dtaghi", 29, 2},
{"ddatahi", 29, 3},
{"errorepc", 30, 0},
{"desave", 31, 0},
{"kscratch1", 31, 2},
{"kscratch2", 31, 3},
{"kscratch3", 31, 4},
{"kscratch4", 31, 5},
{"kscratch5", 31, 6},
{"kscratch6", 31, 7}
};
inline static int COP0Map_getEncIndexMap(int RegNo)
{
int i;
for (i = 0; i < (sizeof(CP0SelRegs) / sizeof(CP0SelRegs[0])); ++i) {
unsigned RegEnc = (CP0SelRegs[i].RegNum << 5) | CP0SelRegs[i].Select;
if (RegEnc == RegNo) {
return i;
}
}
return -1;
}
#endif // LLVM_LIB_TARGET_MIPS_NANOMIPSCP0REGMAP_H
external/capstone/arch/Mips/MipsDisassembler.c
Vendored
+3427
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsDisassembler.h
Vendored
+15
View File
@@ -0,0 +1,15 @@
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifndef CS_MIPSDISASSEMBLER_H
#define CS_MIPSDISASSEMBLER_H
#include "capstone/capstone.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
void Mips_init(MCRegisterInfo *MRI);
bool Mips_getFeatureBits(unsigned int mode, unsigned int feature);
#endif
external/capstone/arch/Mips/MipsGenAsmWriter.inc
Vendored
+11242
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenCSAliasEnum.inc
Vendored
+119
View File
@@ -0,0 +1,119 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
MIPS_INS_ALIAS_ADDIU_B32, // Real instr.: MIPS_ADDIUGP48_NM
MIPS_INS_ALIAS_BITREVB, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_BITREVH, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_BYTEREVH, // Real instr.: MIPS_ROTX_NM
MIPS_INS_ALIAS_NOT, // Real instr.: MIPS_NOR_NM
MIPS_INS_ALIAS_RESTORE_JRC, // Real instr.: MIPS_RESTOREJRC16_NM
MIPS_INS_ALIAS_RESTORE, // Real instr.: MIPS_RESTORE_NM
MIPS_INS_ALIAS_SAVE, // Real instr.: MIPS_SAVE16_NM
MIPS_INS_ALIAS_MOVE, // Real instr.: MIPS_OR
MIPS_INS_ALIAS_BAL, // Real instr.: MIPS_BGEZAL
MIPS_INS_ALIAS_JALR_HB, // Real instr.: MIPS_JALR_HB
MIPS_INS_ALIAS_NEG, // Real instr.: MIPS_SUB
MIPS_INS_ALIAS_NEGU, // Real instr.: MIPS_SUBu
MIPS_INS_ALIAS_NOP, // Real instr.: MIPS_SLL
MIPS_INS_ALIAS_BNEZL, // Real instr.: MIPS_BNEL
MIPS_INS_ALIAS_BEQZL, // Real instr.: MIPS_BEQL
MIPS_INS_ALIAS_SYSCALL, // Real instr.: MIPS_SYSCALL
MIPS_INS_ALIAS_BREAK, // Real instr.: MIPS_BREAK
MIPS_INS_ALIAS_EI, // Real instr.: MIPS_EI
MIPS_INS_ALIAS_DI, // Real instr.: MIPS_DI
MIPS_INS_ALIAS_TEQ, // Real instr.: MIPS_TEQ
MIPS_INS_ALIAS_TGE, // Real instr.: MIPS_TGE
MIPS_INS_ALIAS_TGEU, // Real instr.: MIPS_TGEU
MIPS_INS_ALIAS_TLT, // Real instr.: MIPS_TLT
MIPS_INS_ALIAS_TLTU, // Real instr.: MIPS_TLTU
MIPS_INS_ALIAS_TNE, // Real instr.: MIPS_TNE
MIPS_INS_ALIAS_RDHWR, // Real instr.: MIPS_RDHWR
MIPS_INS_ALIAS_SDBBP, // Real instr.: MIPS_SDBBP
MIPS_INS_ALIAS_SYNC, // Real instr.: MIPS_SYNC
MIPS_INS_ALIAS_HYPCALL, // Real instr.: MIPS_HYPCALL
MIPS_INS_ALIAS_NOR, // Real instr.: MIPS_NORImm
MIPS_INS_ALIAS_C_F_S, // Real instr.: MIPS_C_F_S
MIPS_INS_ALIAS_C_UN_S, // Real instr.: MIPS_C_UN_S
MIPS_INS_ALIAS_C_EQ_S, // Real instr.: MIPS_C_EQ_S
MIPS_INS_ALIAS_C_UEQ_S, // Real instr.: MIPS_C_UEQ_S
MIPS_INS_ALIAS_C_OLT_S, // Real instr.: MIPS_C_OLT_S
MIPS_INS_ALIAS_C_ULT_S, // Real instr.: MIPS_C_ULT_S
MIPS_INS_ALIAS_C_OLE_S, // Real instr.: MIPS_C_OLE_S
MIPS_INS_ALIAS_C_ULE_S, // Real instr.: MIPS_C_ULE_S
MIPS_INS_ALIAS_C_SF_S, // Real instr.: MIPS_C_SF_S
MIPS_INS_ALIAS_C_NGLE_S, // Real instr.: MIPS_C_NGLE_S
MIPS_INS_ALIAS_C_SEQ_S, // Real instr.: MIPS_C_SEQ_S
MIPS_INS_ALIAS_C_NGL_S, // Real instr.: MIPS_C_NGL_S
MIPS_INS_ALIAS_C_LT_S, // Real instr.: MIPS_C_LT_S
MIPS_INS_ALIAS_C_NGE_S, // Real instr.: MIPS_C_NGE_S
MIPS_INS_ALIAS_C_LE_S, // Real instr.: MIPS_C_LE_S
MIPS_INS_ALIAS_C_NGT_S, // Real instr.: MIPS_C_NGT_S
MIPS_INS_ALIAS_BC1T, // Real instr.: MIPS_BC1T
MIPS_INS_ALIAS_BC1F, // Real instr.: MIPS_BC1F
MIPS_INS_ALIAS_C_F_D, // Real instr.: MIPS_C_F_D32
MIPS_INS_ALIAS_C_UN_D, // Real instr.: MIPS_C_UN_D32
MIPS_INS_ALIAS_C_EQ_D, // Real instr.: MIPS_C_EQ_D32
MIPS_INS_ALIAS_C_UEQ_D, // Real instr.: MIPS_C_UEQ_D32
MIPS_INS_ALIAS_C_OLT_D, // Real instr.: MIPS_C_OLT_D32
MIPS_INS_ALIAS_C_ULT_D, // Real instr.: MIPS_C_ULT_D32
MIPS_INS_ALIAS_C_OLE_D, // Real instr.: MIPS_C_OLE_D32
MIPS_INS_ALIAS_C_ULE_D, // Real instr.: MIPS_C_ULE_D32
MIPS_INS_ALIAS_C_SF_D, // Real instr.: MIPS_C_SF_D32
MIPS_INS_ALIAS_C_NGLE_D, // Real instr.: MIPS_C_NGLE_D32
MIPS_INS_ALIAS_C_SEQ_D, // Real instr.: MIPS_C_SEQ_D32
MIPS_INS_ALIAS_C_NGL_D, // Real instr.: MIPS_C_NGL_D32
MIPS_INS_ALIAS_C_LT_D, // Real instr.: MIPS_C_LT_D32
MIPS_INS_ALIAS_C_NGE_D, // Real instr.: MIPS_C_NGE_D32
MIPS_INS_ALIAS_C_LE_D, // Real instr.: MIPS_C_LE_D32
MIPS_INS_ALIAS_C_NGT_D, // Real instr.: MIPS_C_NGT_D32
MIPS_INS_ALIAS_BC1TL, // Real instr.: MIPS_BC1TL
MIPS_INS_ALIAS_BC1FL, // Real instr.: MIPS_BC1FL
MIPS_INS_ALIAS_DNEG, // Real instr.: MIPS_DSUB
MIPS_INS_ALIAS_DNEGU, // Real instr.: MIPS_DSUBu
MIPS_INS_ALIAS_SLT, // Real instr.: MIPS_SLTImm64
MIPS_INS_ALIAS_SLTU, // Real instr.: MIPS_SLTUImm64
MIPS_INS_ALIAS_SIGRIE, // Real instr.: MIPS_SIGRIE
MIPS_INS_ALIAS_JR, // Real instr.: MIPS_JALR
MIPS_INS_ALIAS_JRC, // Real instr.: MIPS_JIC
MIPS_INS_ALIAS_JALRC, // Real instr.: MIPS_JIALC
MIPS_INS_ALIAS_DIV, // Real instr.: MIPS_DIV
MIPS_INS_ALIAS_DIVU, // Real instr.: MIPS_DIVU
MIPS_INS_ALIAS_LAPC, // Real instr.: MIPS_ADDIUPC
MIPS_INS_ALIAS_WRDSP, // Real instr.: MIPS_WRDSP
MIPS_INS_ALIAS_WAIT, // Real instr.: MIPS_WAIT_MM
MIPS_INS_ALIAS_SW, // Real instr.: MIPS_SWSP_MM
MIPS_INS_ALIAS_JALRC_HB, // Real instr.: MIPS_JALRC_HB_MMR6
MIPS_INS_ALIAS_ADDIU_B, // Real instr.: MIPS_ADDIUGPB_NM
MIPS_INS_ALIAS_ADDIU_W, // Real instr.: MIPS_ADDIUGPW_NM
MIPS_INS_ALIAS_JRC_HB, // Real instr.: MIPS_JALRCHB_NM
MIPS_INS_ALIAS_BEQC, // Real instr.: MIPS_BEQC16_NM
MIPS_INS_ALIAS_BNEC, // Real instr.: MIPS_BNEC16_NM
MIPS_INS_ALIAS_BEQZC, // Real instr.: MIPS_BEQC_NM
MIPS_INS_ALIAS_BNEZC, // Real instr.: MIPS_BNEC_NM
MIPS_INS_ALIAS_MFC0, // Real instr.: MIPS_MFC0_NM
MIPS_INS_ALIAS_MFHC0, // Real instr.: MIPS_MFHC0_NM
MIPS_INS_ALIAS_MTC0, // Real instr.: MIPS_MTC0_NM
MIPS_INS_ALIAS_MTHC0, // Real instr.: MIPS_MTHC0_NM
MIPS_INS_ALIAS_DMT, // Real instr.: MIPS_DMT
MIPS_INS_ALIAS_EMT, // Real instr.: MIPS_EMT
MIPS_INS_ALIAS_DVPE, // Real instr.: MIPS_DVPE
MIPS_INS_ALIAS_EVPE, // Real instr.: MIPS_EVPE
MIPS_INS_ALIAS_YIELD, // Real instr.: MIPS_YIELD
MIPS_INS_ALIAS_MFTC0, // Real instr.: MIPS_MFTC0
MIPS_INS_ALIAS_MFTLO, // Real instr.: MIPS_MFTLO
MIPS_INS_ALIAS_MFTHI, // Real instr.: MIPS_MFTHI
MIPS_INS_ALIAS_MFTACX, // Real instr.: MIPS_MFTACX
MIPS_INS_ALIAS_MTTC0, // Real instr.: MIPS_MTTC0
MIPS_INS_ALIAS_MTTLO, // Real instr.: MIPS_MTTLO
MIPS_INS_ALIAS_MTTHI, // Real instr.: MIPS_MTTHI
MIPS_INS_ALIAS_MTTACX, // Real instr.: MIPS_MTTACX
external/capstone/arch/Mips/MipsGenCSAliasMnemMap.inc
Vendored
+119
View File
@@ -0,0 +1,119 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ MIPS_INS_ALIAS_ADDIU_B32, "addiu_b32" },
{ MIPS_INS_ALIAS_BITREVB, "bitrevb" },
{ MIPS_INS_ALIAS_BITREVH, "bitrevh" },
{ MIPS_INS_ALIAS_BYTEREVH, "byterevh" },
{ MIPS_INS_ALIAS_NOT, "not" },
{ MIPS_INS_ALIAS_RESTORE_JRC, "restore_jrc" },
{ MIPS_INS_ALIAS_RESTORE, "restore" },
{ MIPS_INS_ALIAS_SAVE, "save" },
{ MIPS_INS_ALIAS_MOVE, "move" },
{ MIPS_INS_ALIAS_BAL, "bal" },
{ MIPS_INS_ALIAS_JALR_HB, "jalr_hb" },
{ MIPS_INS_ALIAS_NEG, "neg" },
{ MIPS_INS_ALIAS_NEGU, "negu" },
{ MIPS_INS_ALIAS_NOP, "nop" },
{ MIPS_INS_ALIAS_BNEZL, "bnezl" },
{ MIPS_INS_ALIAS_BEQZL, "beqzl" },
{ MIPS_INS_ALIAS_SYSCALL, "syscall" },
{ MIPS_INS_ALIAS_BREAK, "break" },
{ MIPS_INS_ALIAS_EI, "ei" },
{ MIPS_INS_ALIAS_DI, "di" },
{ MIPS_INS_ALIAS_TEQ, "teq" },
{ MIPS_INS_ALIAS_TGE, "tge" },
{ MIPS_INS_ALIAS_TGEU, "tgeu" },
{ MIPS_INS_ALIAS_TLT, "tlt" },
{ MIPS_INS_ALIAS_TLTU, "tltu" },
{ MIPS_INS_ALIAS_TNE, "tne" },
{ MIPS_INS_ALIAS_RDHWR, "rdhwr" },
{ MIPS_INS_ALIAS_SDBBP, "sdbbp" },
{ MIPS_INS_ALIAS_SYNC, "sync" },
{ MIPS_INS_ALIAS_HYPCALL, "hypcall" },
{ MIPS_INS_ALIAS_NOR, "nor" },
{ MIPS_INS_ALIAS_C_F_S, "c_f_s" },
{ MIPS_INS_ALIAS_C_UN_S, "c_un_s" },
{ MIPS_INS_ALIAS_C_EQ_S, "c_eq_s" },
{ MIPS_INS_ALIAS_C_UEQ_S, "c_ueq_s" },
{ MIPS_INS_ALIAS_C_OLT_S, "c_olt_s" },
{ MIPS_INS_ALIAS_C_ULT_S, "c_ult_s" },
{ MIPS_INS_ALIAS_C_OLE_S, "c_ole_s" },
{ MIPS_INS_ALIAS_C_ULE_S, "c_ule_s" },
{ MIPS_INS_ALIAS_C_SF_S, "c_sf_s" },
{ MIPS_INS_ALIAS_C_NGLE_S, "c_ngle_s" },
{ MIPS_INS_ALIAS_C_SEQ_S, "c_seq_s" },
{ MIPS_INS_ALIAS_C_NGL_S, "c_ngl_s" },
{ MIPS_INS_ALIAS_C_LT_S, "c_lt_s" },
{ MIPS_INS_ALIAS_C_NGE_S, "c_nge_s" },
{ MIPS_INS_ALIAS_C_LE_S, "c_le_s" },
{ MIPS_INS_ALIAS_C_NGT_S, "c_ngt_s" },
{ MIPS_INS_ALIAS_BC1T, "bc1t" },
{ MIPS_INS_ALIAS_BC1F, "bc1f" },
{ MIPS_INS_ALIAS_C_F_D, "c_f_d" },
{ MIPS_INS_ALIAS_C_UN_D, "c_un_d" },
{ MIPS_INS_ALIAS_C_EQ_D, "c_eq_d" },
{ MIPS_INS_ALIAS_C_UEQ_D, "c_ueq_d" },
{ MIPS_INS_ALIAS_C_OLT_D, "c_olt_d" },
{ MIPS_INS_ALIAS_C_ULT_D, "c_ult_d" },
{ MIPS_INS_ALIAS_C_OLE_D, "c_ole_d" },
{ MIPS_INS_ALIAS_C_ULE_D, "c_ule_d" },
{ MIPS_INS_ALIAS_C_SF_D, "c_sf_d" },
{ MIPS_INS_ALIAS_C_NGLE_D, "c_ngle_d" },
{ MIPS_INS_ALIAS_C_SEQ_D, "c_seq_d" },
{ MIPS_INS_ALIAS_C_NGL_D, "c_ngl_d" },
{ MIPS_INS_ALIAS_C_LT_D, "c_lt_d" },
{ MIPS_INS_ALIAS_C_NGE_D, "c_nge_d" },
{ MIPS_INS_ALIAS_C_LE_D, "c_le_d" },
{ MIPS_INS_ALIAS_C_NGT_D, "c_ngt_d" },
{ MIPS_INS_ALIAS_BC1TL, "bc1tl" },
{ MIPS_INS_ALIAS_BC1FL, "bc1fl" },
{ MIPS_INS_ALIAS_DNEG, "dneg" },
{ MIPS_INS_ALIAS_DNEGU, "dnegu" },
{ MIPS_INS_ALIAS_SLT, "slt" },
{ MIPS_INS_ALIAS_SLTU, "sltu" },
{ MIPS_INS_ALIAS_SIGRIE, "sigrie" },
{ MIPS_INS_ALIAS_JR, "jr" },
{ MIPS_INS_ALIAS_JRC, "jrc" },
{ MIPS_INS_ALIAS_JALRC, "jalrc" },
{ MIPS_INS_ALIAS_DIV, "div" },
{ MIPS_INS_ALIAS_DIVU, "divu" },
{ MIPS_INS_ALIAS_LAPC, "lapc" },
{ MIPS_INS_ALIAS_WRDSP, "wrdsp" },
{ MIPS_INS_ALIAS_WAIT, "wait" },
{ MIPS_INS_ALIAS_SW, "sw" },
{ MIPS_INS_ALIAS_JALRC_HB, "jalrc_hb" },
{ MIPS_INS_ALIAS_ADDIU_B, "addiu_b" },
{ MIPS_INS_ALIAS_ADDIU_W, "addiu_w" },
{ MIPS_INS_ALIAS_JRC_HB, "jrc_hb" },
{ MIPS_INS_ALIAS_BEQC, "beqc" },
{ MIPS_INS_ALIAS_BNEC, "bnec" },
{ MIPS_INS_ALIAS_BEQZC, "beqzc" },
{ MIPS_INS_ALIAS_BNEZC, "bnezc" },
{ MIPS_INS_ALIAS_MFC0, "mfc0" },
{ MIPS_INS_ALIAS_MFHC0, "mfhc0" },
{ MIPS_INS_ALIAS_MTC0, "mtc0" },
{ MIPS_INS_ALIAS_MTHC0, "mthc0" },
{ MIPS_INS_ALIAS_DMT, "dmt" },
{ MIPS_INS_ALIAS_EMT, "emt" },
{ MIPS_INS_ALIAS_DVPE, "dvpe" },
{ MIPS_INS_ALIAS_EVPE, "evpe" },
{ MIPS_INS_ALIAS_YIELD, "yield" },
{ MIPS_INS_ALIAS_MFTC0, "mftc0" },
{ MIPS_INS_ALIAS_MFTLO, "mftlo" },
{ MIPS_INS_ALIAS_MFTHI, "mfthi" },
{ MIPS_INS_ALIAS_MFTACX, "mftacx" },
{ MIPS_INS_ALIAS_MTTC0, "mttc0" },
{ MIPS_INS_ALIAS_MTTLO, "mttlo" },
{ MIPS_INS_ALIAS_MTTHI, "mtthi" },
{ MIPS_INS_ALIAS_MTTACX, "mttacx" },
external/capstone/arch/Mips/MipsGenCSFeatureEnum.inc
Vendored
+69
View File
@@ -0,0 +1,69 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
MIPS_FEATURE_HASMIPS2 = 128,
MIPS_FEATURE_HASMIPS3_32,
MIPS_FEATURE_HASMIPS3_32R2,
MIPS_FEATURE_HASMIPS3,
MIPS_FEATURE_NOTMIPS3,
MIPS_FEATURE_HASMIPS4_32,
MIPS_FEATURE_NOTMIPS4_32,
MIPS_FEATURE_HASMIPS4_32R2,
MIPS_FEATURE_HASMIPS5_32R2,
MIPS_FEATURE_HASMIPS32,
MIPS_FEATURE_HASMIPS32R2,
MIPS_FEATURE_HASMIPS32R5,
MIPS_FEATURE_HASMIPS32R6,
MIPS_FEATURE_NOTMIPS32R6,
MIPS_FEATURE_HASNANOMIPS,
MIPS_FEATURE_NOTNANOMIPS,
MIPS_FEATURE_ISGP64BIT,
MIPS_FEATURE_ISGP32BIT,
MIPS_FEATURE_ISPTR64BIT,
MIPS_FEATURE_ISPTR32BIT,
MIPS_FEATURE_HASMIPS64,
MIPS_FEATURE_NOTMIPS64,
MIPS_FEATURE_HASMIPS64R2,
MIPS_FEATURE_HASMIPS64R5,
MIPS_FEATURE_HASMIPS64R6,
MIPS_FEATURE_NOTMIPS64R6,
MIPS_FEATURE_INMIPS16MODE,
MIPS_FEATURE_NOTINMIPS16MODE,
MIPS_FEATURE_HASCNMIPS,
MIPS_FEATURE_NOTCNMIPS,
MIPS_FEATURE_HASCNMIPSP,
MIPS_FEATURE_NOTCNMIPSP,
MIPS_FEATURE_ISSYM32,
MIPS_FEATURE_ISSYM64,
MIPS_FEATURE_HASSTDENC,
MIPS_FEATURE_INMICROMIPS,
MIPS_FEATURE_NOTINMICROMIPS,
MIPS_FEATURE_HASEVA,
MIPS_FEATURE_HASMSA,
MIPS_FEATURE_HASMADD4,
MIPS_FEATURE_HASMT,
MIPS_FEATURE_USEINDIRECTJUMPSHAZARD,
MIPS_FEATURE_NOINDIRECTJUMPGUARDS,
MIPS_FEATURE_HASCRC,
MIPS_FEATURE_HASVIRT,
MIPS_FEATURE_HASGINV,
MIPS_FEATURE_HASTLB,
MIPS_FEATURE_ISFP64BIT,
MIPS_FEATURE_NOTFP64BIT,
MIPS_FEATURE_ISSINGLEFLOAT,
MIPS_FEATURE_ISNOTSINGLEFLOAT,
MIPS_FEATURE_ISNOTSOFTFLOAT,
MIPS_FEATURE_HASMIPS3D,
MIPS_FEATURE_HASDSP,
MIPS_FEATURE_HASDSPR2,
MIPS_FEATURE_HASDSPR3,
external/capstone/arch/Mips/MipsGenCSFeatureName.inc
Vendored
+69
View File
@@ -0,0 +1,69 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
{ MIPS_FEATURE_HASMIPS2, "HasMips2" },
{ MIPS_FEATURE_HASMIPS3_32, "HasMips3_32" },
{ MIPS_FEATURE_HASMIPS3_32R2, "HasMips3_32r2" },
{ MIPS_FEATURE_HASMIPS3, "HasMips3" },
{ MIPS_FEATURE_NOTMIPS3, "NotMips3" },
{ MIPS_FEATURE_HASMIPS4_32, "HasMips4_32" },
{ MIPS_FEATURE_NOTMIPS4_32, "NotMips4_32" },
{ MIPS_FEATURE_HASMIPS4_32R2, "HasMips4_32r2" },
{ MIPS_FEATURE_HASMIPS5_32R2, "HasMips5_32r2" },
{ MIPS_FEATURE_HASMIPS32, "HasMips32" },
{ MIPS_FEATURE_HASMIPS32R2, "HasMips32r2" },
{ MIPS_FEATURE_HASMIPS32R5, "HasMips32r5" },
{ MIPS_FEATURE_HASMIPS32R6, "HasMips32r6" },
{ MIPS_FEATURE_NOTMIPS32R6, "NotMips32r6" },
{ MIPS_FEATURE_HASNANOMIPS, "HasNanoMips" },
{ MIPS_FEATURE_NOTNANOMIPS, "NotNanoMips" },
{ MIPS_FEATURE_ISGP64BIT, "IsGP64bit" },
{ MIPS_FEATURE_ISGP32BIT, "IsGP32bit" },
{ MIPS_FEATURE_ISPTR64BIT, "IsPTR64bit" },
{ MIPS_FEATURE_ISPTR32BIT, "IsPTR32bit" },
{ MIPS_FEATURE_HASMIPS64, "HasMips64" },
{ MIPS_FEATURE_NOTMIPS64, "NotMips64" },
{ MIPS_FEATURE_HASMIPS64R2, "HasMips64r2" },
{ MIPS_FEATURE_HASMIPS64R5, "HasMips64r5" },
{ MIPS_FEATURE_HASMIPS64R6, "HasMips64r6" },
{ MIPS_FEATURE_NOTMIPS64R6, "NotMips64r6" },
{ MIPS_FEATURE_INMIPS16MODE, "InMips16Mode" },
{ MIPS_FEATURE_NOTINMIPS16MODE, "NotInMips16Mode" },
{ MIPS_FEATURE_HASCNMIPS, "HasCnMips" },
{ MIPS_FEATURE_NOTCNMIPS, "NotCnMips" },
{ MIPS_FEATURE_HASCNMIPSP, "HasCnMipsP" },
{ MIPS_FEATURE_NOTCNMIPSP, "NotCnMipsP" },
{ MIPS_FEATURE_ISSYM32, "IsSym32" },
{ MIPS_FEATURE_ISSYM64, "IsSym64" },
{ MIPS_FEATURE_HASSTDENC, "HasStdEnc" },
{ MIPS_FEATURE_INMICROMIPS, "InMicroMips" },
{ MIPS_FEATURE_NOTINMICROMIPS, "NotInMicroMips" },
{ MIPS_FEATURE_HASEVA, "HasEVA" },
{ MIPS_FEATURE_HASMSA, "HasMSA" },
{ MIPS_FEATURE_HASMADD4, "HasMadd4" },
{ MIPS_FEATURE_HASMT, "HasMT" },
{ MIPS_FEATURE_USEINDIRECTJUMPSHAZARD, "UseIndirectJumpsHazard" },
{ MIPS_FEATURE_NOINDIRECTJUMPGUARDS, "NoIndirectJumpGuards" },
{ MIPS_FEATURE_HASCRC, "HasCRC" },
{ MIPS_FEATURE_HASVIRT, "HasVirt" },
{ MIPS_FEATURE_HASGINV, "HasGINV" },
{ MIPS_FEATURE_HASTLB, "HasTLB" },
{ MIPS_FEATURE_ISFP64BIT, "IsFP64bit" },
{ MIPS_FEATURE_NOTFP64BIT, "NotFP64bit" },
{ MIPS_FEATURE_ISSINGLEFLOAT, "IsSingleFloat" },
{ MIPS_FEATURE_ISNOTSINGLEFLOAT, "IsNotSingleFloat" },
{ MIPS_FEATURE_ISNOTSOFTFLOAT, "IsNotSoftFloat" },
{ MIPS_FEATURE_HASMIPS3D, "HasMips3D" },
{ MIPS_FEATURE_HASDSP, "HasDSP" },
{ MIPS_FEATURE_HASDSPR2, "HasDSPR2" },
{ MIPS_FEATURE_HASDSPR3, "HasDSPR3" },
external/capstone/arch/Mips/MipsGenCSInsnEnum.inc
Vendored
+1373
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenCSMappingInsn.inc
Vendored
+24465
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenCSMappingInsnName.inc
Vendored
+1373
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenCSMappingInsnOp.inc
Vendored
+18615
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenCSOpGroup.inc
Vendored
+45
View File
@@ -0,0 +1,45 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
Mips_OP_GROUP_Operand = 0,
Mips_OP_GROUP_BranchOperand = 1,
Mips_OP_GROUP_UImm_1_0 = 2,
Mips_OP_GROUP_UImm_2_0 = 3,
Mips_OP_GROUP_JumpOperand = 4,
Mips_OP_GROUP_MemOperand = 5,
Mips_OP_GROUP_RegisterList = 6,
Mips_OP_GROUP_UImm_3_0 = 7,
Mips_OP_GROUP_PCRel = 8,
Mips_OP_GROUP_UImm_32_0 = 9,
Mips_OP_GROUP_UImm_16_0 = 10,
Mips_OP_GROUP_UImm_8_0 = 11,
Mips_OP_GROUP_UImm_5_0 = 12,
Mips_OP_GROUP_Hi20PCRel = 13,
Mips_OP_GROUP_MemOperandEA = 14,
Mips_OP_GROUP_UImm_6_0 = 15,
Mips_OP_GROUP_UImm_4_0 = 16,
Mips_OP_GROUP_UImm_7_0 = 17,
Mips_OP_GROUP_UImm_10_0 = 18,
Mips_OP_GROUP_UImm_6_1 = 19,
Mips_OP_GROUP_UImm_5_1 = 20,
Mips_OP_GROUP_UImm_5_33 = 21,
Mips_OP_GROUP_UImm_5_32 = 22,
Mips_OP_GROUP_UImm_6_2 = 23,
Mips_OP_GROUP_UImm_2_1 = 24,
Mips_OP_GROUP_FCCOperand = 25,
Mips_OP_GROUP_UImm_0_0 = 26,
Mips_OP_GROUP_UImm_26_0 = 27,
Mips_OP_GROUP_Hi20 = 28,
Mips_OP_GROUP_NanoMipsRegisterList = 29,
Mips_OP_GROUP_UImm_12_0 = 30,
Mips_OP_GROUP_UImm_20_0 = 31,
external/capstone/arch/Mips/MipsGenCSRegEnum.inc
Vendored
+649
View File
@@ -0,0 +1,649 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
MIPS_REG_INVALID = 0,
MIPS_REG_AT = 1,
MIPS_REG_AT_NM = 2,
MIPS_REG_DSPCCOND = 3,
MIPS_REG_DSPCARRY = 4,
MIPS_REG_DSPEFI = 5,
MIPS_REG_DSPOUTFLAG = 6,
MIPS_REG_DSPPOS = 7,
MIPS_REG_DSPSCOUNT = 8,
MIPS_REG_FP = 9,
MIPS_REG_FP_NM = 10,
MIPS_REG_GP = 11,
MIPS_REG_GP_NM = 12,
MIPS_REG_MSAACCESS = 13,
MIPS_REG_MSACSR = 14,
MIPS_REG_MSAIR = 15,
MIPS_REG_MSAMAP = 16,
MIPS_REG_MSAMODIFY = 17,
MIPS_REG_MSAREQUEST = 18,
MIPS_REG_MSASAVE = 19,
MIPS_REG_MSAUNMAP = 20,
MIPS_REG_PC = 21,
MIPS_REG_RA = 22,
MIPS_REG_RA_NM = 23,
MIPS_REG_SP = 24,
MIPS_REG_SP_NM = 25,
MIPS_REG_ZERO = 26,
MIPS_REG_ZERO_NM = 27,
MIPS_REG_A0 = 28,
MIPS_REG_A1 = 29,
MIPS_REG_A2 = 30,
MIPS_REG_A3 = 31,
MIPS_REG_AC0 = 32,
MIPS_REG_AC1 = 33,
MIPS_REG_AC2 = 34,
MIPS_REG_AC3 = 35,
MIPS_REG_AT_64 = 36,
MIPS_REG_COP00 = 37,
MIPS_REG_COP01 = 38,
MIPS_REG_COP02 = 39,
MIPS_REG_COP03 = 40,
MIPS_REG_COP04 = 41,
MIPS_REG_COP05 = 42,
MIPS_REG_COP06 = 43,
MIPS_REG_COP07 = 44,
MIPS_REG_COP08 = 45,
MIPS_REG_COP09 = 46,
MIPS_REG_COP20 = 47,
MIPS_REG_COP21 = 48,
MIPS_REG_COP22 = 49,
MIPS_REG_COP23 = 50,
MIPS_REG_COP24 = 51,
MIPS_REG_COP25 = 52,
MIPS_REG_COP26 = 53,
MIPS_REG_COP27 = 54,
MIPS_REG_COP28 = 55,
MIPS_REG_COP29 = 56,
MIPS_REG_COP30 = 57,
MIPS_REG_COP31 = 58,
MIPS_REG_COP32 = 59,
MIPS_REG_COP33 = 60,
MIPS_REG_COP34 = 61,
MIPS_REG_COP35 = 62,
MIPS_REG_COP36 = 63,
MIPS_REG_COP37 = 64,
MIPS_REG_COP38 = 65,
MIPS_REG_COP39 = 66,
MIPS_REG_COP010 = 67,
MIPS_REG_COP011 = 68,
MIPS_REG_COP012 = 69,
MIPS_REG_COP013 = 70,
MIPS_REG_COP014 = 71,
MIPS_REG_COP015 = 72,
MIPS_REG_COP016 = 73,
MIPS_REG_COP017 = 74,
MIPS_REG_COP018 = 75,
MIPS_REG_COP019 = 76,
MIPS_REG_COP020 = 77,
MIPS_REG_COP021 = 78,
MIPS_REG_COP022 = 79,
MIPS_REG_COP023 = 80,
MIPS_REG_COP024 = 81,
MIPS_REG_COP025 = 82,
MIPS_REG_COP026 = 83,
MIPS_REG_COP027 = 84,
MIPS_REG_COP028 = 85,
MIPS_REG_COP029 = 86,
MIPS_REG_COP030 = 87,
MIPS_REG_COP031 = 88,
MIPS_REG_COP210 = 89,
MIPS_REG_COP211 = 90,
MIPS_REG_COP212 = 91,
MIPS_REG_COP213 = 92,
MIPS_REG_COP214 = 93,
MIPS_REG_COP215 = 94,
MIPS_REG_COP216 = 95,
MIPS_REG_COP217 = 96,
MIPS_REG_COP218 = 97,
MIPS_REG_COP219 = 98,
MIPS_REG_COP220 = 99,
MIPS_REG_COP221 = 100,
MIPS_REG_COP222 = 101,
MIPS_REG_COP223 = 102,
MIPS_REG_COP224 = 103,
MIPS_REG_COP225 = 104,
MIPS_REG_COP226 = 105,
MIPS_REG_COP227 = 106,
MIPS_REG_COP228 = 107,
MIPS_REG_COP229 = 108,
MIPS_REG_COP230 = 109,
MIPS_REG_COP231 = 110,
MIPS_REG_COP310 = 111,
MIPS_REG_COP311 = 112,
MIPS_REG_COP312 = 113,
MIPS_REG_COP313 = 114,
MIPS_REG_COP314 = 115,
MIPS_REG_COP315 = 116,
MIPS_REG_COP316 = 117,
MIPS_REG_COP317 = 118,
MIPS_REG_COP318 = 119,
MIPS_REG_COP319 = 120,
MIPS_REG_COP320 = 121,
MIPS_REG_COP321 = 122,
MIPS_REG_COP322 = 123,
MIPS_REG_COP323 = 124,
MIPS_REG_COP324 = 125,
MIPS_REG_COP325 = 126,
MIPS_REG_COP326 = 127,
MIPS_REG_COP327 = 128,
MIPS_REG_COP328 = 129,
MIPS_REG_COP329 = 130,
MIPS_REG_COP330 = 131,
MIPS_REG_COP331 = 132,
MIPS_REG_D0 = 133,
MIPS_REG_D1 = 134,
MIPS_REG_D2 = 135,
MIPS_REG_D3 = 136,
MIPS_REG_D4 = 137,
MIPS_REG_D5 = 138,
MIPS_REG_D6 = 139,
MIPS_REG_D7 = 140,
MIPS_REG_D8 = 141,
MIPS_REG_D9 = 142,
MIPS_REG_D10 = 143,
MIPS_REG_D11 = 144,
MIPS_REG_D12 = 145,
MIPS_REG_D13 = 146,
MIPS_REG_D14 = 147,
MIPS_REG_D15 = 148,
MIPS_REG_DSPOUTFLAG20 = 149,
MIPS_REG_DSPOUTFLAG21 = 150,
MIPS_REG_DSPOUTFLAG22 = 151,
MIPS_REG_DSPOUTFLAG23 = 152,
MIPS_REG_F0 = 153,
MIPS_REG_F1 = 154,
MIPS_REG_F2 = 155,
MIPS_REG_F3 = 156,
MIPS_REG_F4 = 157,
MIPS_REG_F5 = 158,
MIPS_REG_F6 = 159,
MIPS_REG_F7 = 160,
MIPS_REG_F8 = 161,
MIPS_REG_F9 = 162,
MIPS_REG_F10 = 163,
MIPS_REG_F11 = 164,
MIPS_REG_F12 = 165,
MIPS_REG_F13 = 166,
MIPS_REG_F14 = 167,
MIPS_REG_F15 = 168,
MIPS_REG_F16 = 169,
MIPS_REG_F17 = 170,
MIPS_REG_F18 = 171,
MIPS_REG_F19 = 172,
MIPS_REG_F20 = 173,
MIPS_REG_F21 = 174,
MIPS_REG_F22 = 175,
MIPS_REG_F23 = 176,
MIPS_REG_F24 = 177,
MIPS_REG_F25 = 178,
MIPS_REG_F26 = 179,
MIPS_REG_F27 = 180,
MIPS_REG_F28 = 181,
MIPS_REG_F29 = 182,
MIPS_REG_F30 = 183,
MIPS_REG_F31 = 184,
MIPS_REG_FCC0 = 185,
MIPS_REG_FCC1 = 186,
MIPS_REG_FCC2 = 187,
MIPS_REG_FCC3 = 188,
MIPS_REG_FCC4 = 189,
MIPS_REG_FCC5 = 190,
MIPS_REG_FCC6 = 191,
MIPS_REG_FCC7 = 192,
MIPS_REG_FCR0 = 193,
MIPS_REG_FCR1 = 194,
MIPS_REG_FCR2 = 195,
MIPS_REG_FCR3 = 196,
MIPS_REG_FCR4 = 197,
MIPS_REG_FCR5 = 198,
MIPS_REG_FCR6 = 199,
MIPS_REG_FCR7 = 200,
MIPS_REG_FCR8 = 201,
MIPS_REG_FCR9 = 202,
MIPS_REG_FCR10 = 203,
MIPS_REG_FCR11 = 204,
MIPS_REG_FCR12 = 205,
MIPS_REG_FCR13 = 206,
MIPS_REG_FCR14 = 207,
MIPS_REG_FCR15 = 208,
MIPS_REG_FCR16 = 209,
MIPS_REG_FCR17 = 210,
MIPS_REG_FCR18 = 211,
MIPS_REG_FCR19 = 212,
MIPS_REG_FCR20 = 213,
MIPS_REG_FCR21 = 214,
MIPS_REG_FCR22 = 215,
MIPS_REG_FCR23 = 216,
MIPS_REG_FCR24 = 217,
MIPS_REG_FCR25 = 218,
MIPS_REG_FCR26 = 219,
MIPS_REG_FCR27 = 220,
MIPS_REG_FCR28 = 221,
MIPS_REG_FCR29 = 222,
MIPS_REG_FCR30 = 223,
MIPS_REG_FCR31 = 224,
MIPS_REG_FP_64 = 225,
MIPS_REG_F_HI0 = 226,
MIPS_REG_F_HI1 = 227,
MIPS_REG_F_HI2 = 228,
MIPS_REG_F_HI3 = 229,
MIPS_REG_F_HI4 = 230,
MIPS_REG_F_HI5 = 231,
MIPS_REG_F_HI6 = 232,
MIPS_REG_F_HI7 = 233,
MIPS_REG_F_HI8 = 234,
MIPS_REG_F_HI9 = 235,
MIPS_REG_F_HI10 = 236,
MIPS_REG_F_HI11 = 237,
MIPS_REG_F_HI12 = 238,
MIPS_REG_F_HI13 = 239,
MIPS_REG_F_HI14 = 240,
MIPS_REG_F_HI15 = 241,
MIPS_REG_F_HI16 = 242,
MIPS_REG_F_HI17 = 243,
MIPS_REG_F_HI18 = 244,
MIPS_REG_F_HI19 = 245,
MIPS_REG_F_HI20 = 246,
MIPS_REG_F_HI21 = 247,
MIPS_REG_F_HI22 = 248,
MIPS_REG_F_HI23 = 249,
MIPS_REG_F_HI24 = 250,
MIPS_REG_F_HI25 = 251,
MIPS_REG_F_HI26 = 252,
MIPS_REG_F_HI27 = 253,
MIPS_REG_F_HI28 = 254,
MIPS_REG_F_HI29 = 255,
MIPS_REG_F_HI30 = 256,
MIPS_REG_F_HI31 = 257,
MIPS_REG_GP_64 = 258,
MIPS_REG_HI0 = 259,
MIPS_REG_HI1 = 260,
MIPS_REG_HI2 = 261,
MIPS_REG_HI3 = 262,
MIPS_REG_HWR0 = 263,
MIPS_REG_HWR1 = 264,
MIPS_REG_HWR2 = 265,
MIPS_REG_HWR3 = 266,
MIPS_REG_HWR4 = 267,
MIPS_REG_HWR5 = 268,
MIPS_REG_HWR6 = 269,
MIPS_REG_HWR7 = 270,
MIPS_REG_HWR8 = 271,
MIPS_REG_HWR9 = 272,
MIPS_REG_HWR10 = 273,
MIPS_REG_HWR11 = 274,
MIPS_REG_HWR12 = 275,
MIPS_REG_HWR13 = 276,
MIPS_REG_HWR14 = 277,
MIPS_REG_HWR15 = 278,
MIPS_REG_HWR16 = 279,
MIPS_REG_HWR17 = 280,
MIPS_REG_HWR18 = 281,
MIPS_REG_HWR19 = 282,
MIPS_REG_HWR20 = 283,
MIPS_REG_HWR21 = 284,
MIPS_REG_HWR22 = 285,
MIPS_REG_HWR23 = 286,
MIPS_REG_HWR24 = 287,
MIPS_REG_HWR25 = 288,
MIPS_REG_HWR26 = 289,
MIPS_REG_HWR27 = 290,
MIPS_REG_HWR28 = 291,
MIPS_REG_HWR29 = 292,
MIPS_REG_HWR30 = 293,
MIPS_REG_HWR31 = 294,
MIPS_REG_K0 = 295,
MIPS_REG_K1 = 296,
MIPS_REG_LO0 = 297,
MIPS_REG_LO1 = 298,
MIPS_REG_LO2 = 299,
MIPS_REG_LO3 = 300,
MIPS_REG_MPL0 = 301,
MIPS_REG_MPL1 = 302,
MIPS_REG_MPL2 = 303,
MIPS_REG_MSA8 = 304,
MIPS_REG_MSA9 = 305,
MIPS_REG_MSA10 = 306,
MIPS_REG_MSA11 = 307,
MIPS_REG_MSA12 = 308,
MIPS_REG_MSA13 = 309,
MIPS_REG_MSA14 = 310,
MIPS_REG_MSA15 = 311,
MIPS_REG_MSA16 = 312,
MIPS_REG_MSA17 = 313,
MIPS_REG_MSA18 = 314,
MIPS_REG_MSA19 = 315,
MIPS_REG_MSA20 = 316,
MIPS_REG_MSA21 = 317,
MIPS_REG_MSA22 = 318,
MIPS_REG_MSA23 = 319,
MIPS_REG_MSA24 = 320,
MIPS_REG_MSA25 = 321,
MIPS_REG_MSA26 = 322,
MIPS_REG_MSA27 = 323,
MIPS_REG_MSA28 = 324,
MIPS_REG_MSA29 = 325,
MIPS_REG_MSA30 = 326,
MIPS_REG_MSA31 = 327,
MIPS_REG_P0 = 328,
MIPS_REG_P1 = 329,
MIPS_REG_P2 = 330,
MIPS_REG_RA_64 = 331,
MIPS_REG_S0 = 332,
MIPS_REG_S1 = 333,
MIPS_REG_S2 = 334,
MIPS_REG_S3 = 335,
MIPS_REG_S4 = 336,
MIPS_REG_S5 = 337,
MIPS_REG_S6 = 338,
MIPS_REG_S7 = 339,
MIPS_REG_SP_64 = 340,
MIPS_REG_T0 = 341,
MIPS_REG_T1 = 342,
MIPS_REG_T2 = 343,
MIPS_REG_T3 = 344,
MIPS_REG_T4 = 345,
MIPS_REG_T5 = 346,
MIPS_REG_T6 = 347,
MIPS_REG_T7 = 348,
MIPS_REG_T8 = 349,
MIPS_REG_T9 = 350,
MIPS_REG_V0 = 351,
MIPS_REG_V1 = 352,
MIPS_REG_W0 = 353,
MIPS_REG_W1 = 354,
MIPS_REG_W2 = 355,
MIPS_REG_W3 = 356,
MIPS_REG_W4 = 357,
MIPS_REG_W5 = 358,
MIPS_REG_W6 = 359,
MIPS_REG_W7 = 360,
MIPS_REG_W8 = 361,
MIPS_REG_W9 = 362,
MIPS_REG_W10 = 363,
MIPS_REG_W11 = 364,
MIPS_REG_W12 = 365,
MIPS_REG_W13 = 366,
MIPS_REG_W14 = 367,
MIPS_REG_W15 = 368,
MIPS_REG_W16 = 369,
MIPS_REG_W17 = 370,
MIPS_REG_W18 = 371,
MIPS_REG_W19 = 372,
MIPS_REG_W20 = 373,
MIPS_REG_W21 = 374,
MIPS_REG_W22 = 375,
MIPS_REG_W23 = 376,
MIPS_REG_W24 = 377,
MIPS_REG_W25 = 378,
MIPS_REG_W26 = 379,
MIPS_REG_W27 = 380,
MIPS_REG_W28 = 381,
MIPS_REG_W29 = 382,
MIPS_REG_W30 = 383,
MIPS_REG_W31 = 384,
MIPS_REG_ZERO_64 = 385,
MIPS_REG_A0_NM = 386,
MIPS_REG_A1_NM = 387,
MIPS_REG_A2_NM = 388,
MIPS_REG_A3_NM = 389,
MIPS_REG_A4_NM = 390,
MIPS_REG_A5_NM = 391,
MIPS_REG_A6_NM = 392,
MIPS_REG_A7_NM = 393,
MIPS_REG_COP0SEL_BADINST = 394,
MIPS_REG_COP0SEL_BADINSTRP = 395,
MIPS_REG_COP0SEL_BADINSTRX = 396,
MIPS_REG_COP0SEL_BADVADDR = 397,
MIPS_REG_COP0SEL_BEVVA = 398,
MIPS_REG_COP0SEL_CACHEERR = 399,
MIPS_REG_COP0SEL_CAUSE = 400,
MIPS_REG_COP0SEL_CDMMBASE = 401,
MIPS_REG_COP0SEL_CMGCRBASE = 402,
MIPS_REG_COP0SEL_COMPARE = 403,
MIPS_REG_COP0SEL_CONFIG = 404,
MIPS_REG_COP0SEL_CONTEXT = 405,
MIPS_REG_COP0SEL_CONTEXTCONFIG = 406,
MIPS_REG_COP0SEL_COUNT = 407,
MIPS_REG_COP0SEL_DDATAHI = 408,
MIPS_REG_COP0SEL_DDATALO = 409,
MIPS_REG_COP0SEL_DEBUG = 410,
MIPS_REG_COP0SEL_DEBUGCONTEXTID = 411,
MIPS_REG_COP0SEL_DEPC = 412,
MIPS_REG_COP0SEL_DESAVE = 413,
MIPS_REG_COP0SEL_DTAGHI = 414,
MIPS_REG_COP0SEL_DTAGLO = 415,
MIPS_REG_COP0SEL_EBASE = 416,
MIPS_REG_COP0SEL_ENTRYHI = 417,
MIPS_REG_COP0SEL_EPC = 418,
MIPS_REG_COP0SEL_ERRCTL = 419,
MIPS_REG_COP0SEL_ERROREPC = 420,
MIPS_REG_COP0SEL_GLOBALNUMBER = 421,
MIPS_REG_COP0SEL_GTOFFSET = 422,
MIPS_REG_COP0SEL_HWRENA = 423,
MIPS_REG_COP0SEL_IDATAHI = 424,
MIPS_REG_COP0SEL_IDATALO = 425,
MIPS_REG_COP0SEL_INDEX = 426,
MIPS_REG_COP0SEL_INTCTL = 427,
MIPS_REG_COP0SEL_ITAGHI = 428,
MIPS_REG_COP0SEL_ITAGLO = 429,
MIPS_REG_COP0SEL_LLADDR = 430,
MIPS_REG_COP0SEL_MAAR = 431,
MIPS_REG_COP0SEL_MAARI = 432,
MIPS_REG_COP0SEL_MEMORYMAPID = 433,
MIPS_REG_COP0SEL_MVPCONTROL = 434,
MIPS_REG_COP0SEL_NESTEDEPC = 435,
MIPS_REG_COP0SEL_NESTEDEXC = 436,
MIPS_REG_COP0SEL_PAGEGRAIN = 437,
MIPS_REG_COP0SEL_PAGEMASK = 438,
MIPS_REG_COP0SEL_PRID = 439,
MIPS_REG_COP0SEL_PWBASE = 440,
MIPS_REG_COP0SEL_PWCTL = 441,
MIPS_REG_COP0SEL_PWFIELD = 442,
MIPS_REG_COP0SEL_PWSIZE = 443,
MIPS_REG_COP0SEL_RANDOM = 444,
MIPS_REG_COP0SEL_SRSCTL = 445,
MIPS_REG_COP0SEL_SRSMAP = 446,
MIPS_REG_COP0SEL_STATUS = 447,
MIPS_REG_COP0SEL_TCBIND = 448,
MIPS_REG_COP0SEL_TCCONTEXT = 449,
MIPS_REG_COP0SEL_TCHALT = 450,
MIPS_REG_COP0SEL_TCOPT = 451,
MIPS_REG_COP0SEL_TCRESTART = 452,
MIPS_REG_COP0SEL_TCSCHEDULE = 453,
MIPS_REG_COP0SEL_TCSCHEFBACK = 454,
MIPS_REG_COP0SEL_TCSTATUS = 455,
MIPS_REG_COP0SEL_TRACECONTROL = 456,
MIPS_REG_COP0SEL_TRACEDBPC = 457,
MIPS_REG_COP0SEL_TRACEIBPC = 458,
MIPS_REG_COP0SEL_USERLOCAL = 459,
MIPS_REG_COP0SEL_VIEW_IPL = 460,
MIPS_REG_COP0SEL_VIEW_RIPL = 461,
MIPS_REG_COP0SEL_VPCONTROL = 462,
MIPS_REG_COP0SEL_VPECONTROL = 463,
MIPS_REG_COP0SEL_VPEOPT = 464,
MIPS_REG_COP0SEL_VPESCHEDULE = 465,
MIPS_REG_COP0SEL_VPESCHEFBACK = 466,
MIPS_REG_COP0SEL_WIRED = 467,
MIPS_REG_COP0SEL_XCONTEXT = 468,
MIPS_REG_COP0SEL_XCONTEXTCONFIG = 469,
MIPS_REG_COP0SEL_YQMASK = 470,
MIPS_REG_K0_NM = 471,
MIPS_REG_K1_NM = 472,
MIPS_REG_S0_NM = 473,
MIPS_REG_S1_NM = 474,
MIPS_REG_S2_NM = 475,
MIPS_REG_S3_NM = 476,
MIPS_REG_S4_NM = 477,
MIPS_REG_S5_NM = 478,
MIPS_REG_S6_NM = 479,
MIPS_REG_S7_NM = 480,
MIPS_REG_T0_NM = 481,
MIPS_REG_T1_NM = 482,
MIPS_REG_T2_NM = 483,
MIPS_REG_T3_NM = 484,
MIPS_REG_T4_NM = 485,
MIPS_REG_T5_NM = 486,
MIPS_REG_T8_NM = 487,
MIPS_REG_T9_NM = 488,
MIPS_REG_A0_64 = 489,
MIPS_REG_A1_64 = 490,
MIPS_REG_A2_64 = 491,
MIPS_REG_A3_64 = 492,
MIPS_REG_AC0_64 = 493,
MIPS_REG_COP0SEL_CONFIG1 = 494,
MIPS_REG_COP0SEL_CONFIG2 = 495,
MIPS_REG_COP0SEL_CONFIG3 = 496,
MIPS_REG_COP0SEL_CONFIG4 = 497,
MIPS_REG_COP0SEL_CONFIG5 = 498,
MIPS_REG_COP0SEL_DEBUG2 = 499,
MIPS_REG_COP0SEL_ENTRYLO0 = 500,
MIPS_REG_COP0SEL_ENTRYLO1 = 501,
MIPS_REG_COP0SEL_GUESTCTL0 = 502,
MIPS_REG_COP0SEL_GUESTCTL1 = 503,
MIPS_REG_COP0SEL_GUESTCTL2 = 504,
MIPS_REG_COP0SEL_GUESTCTL3 = 505,
MIPS_REG_COP0SEL_KSCRATCH1 = 506,
MIPS_REG_COP0SEL_KSCRATCH2 = 507,
MIPS_REG_COP0SEL_KSCRATCH3 = 508,
MIPS_REG_COP0SEL_KSCRATCH4 = 509,
MIPS_REG_COP0SEL_KSCRATCH5 = 510,
MIPS_REG_COP0SEL_KSCRATCH6 = 511,
MIPS_REG_COP0SEL_MVPCONF0 = 512,
MIPS_REG_COP0SEL_MVPCONF1 = 513,
MIPS_REG_COP0SEL_PERFCNT0 = 514,
MIPS_REG_COP0SEL_PERFCNT1 = 515,
MIPS_REG_COP0SEL_PERFCNT2 = 516,
MIPS_REG_COP0SEL_PERFCNT3 = 517,
MIPS_REG_COP0SEL_PERFCNT4 = 518,
MIPS_REG_COP0SEL_PERFCNT5 = 519,
MIPS_REG_COP0SEL_PERFCNT6 = 520,
MIPS_REG_COP0SEL_PERFCNT7 = 521,
MIPS_REG_COP0SEL_PERFCTL0 = 522,
MIPS_REG_COP0SEL_PERFCTL1 = 523,
MIPS_REG_COP0SEL_PERFCTL2 = 524,
MIPS_REG_COP0SEL_PERFCTL3 = 525,
MIPS_REG_COP0SEL_PERFCTL4 = 526,
MIPS_REG_COP0SEL_PERFCTL5 = 527,
MIPS_REG_COP0SEL_PERFCTL6 = 528,
MIPS_REG_COP0SEL_PERFCTL7 = 529,
MIPS_REG_COP0SEL_SEGCTL0 = 530,
MIPS_REG_COP0SEL_SEGCTL1 = 531,
MIPS_REG_COP0SEL_SEGCTL2 = 532,
MIPS_REG_COP0SEL_SRSCONF0 = 533,
MIPS_REG_COP0SEL_SRSCONF1 = 534,
MIPS_REG_COP0SEL_SRSCONF2 = 535,
MIPS_REG_COP0SEL_SRSCONF3 = 536,
MIPS_REG_COP0SEL_SRSCONF4 = 537,
MIPS_REG_COP0SEL_SRSMAP2 = 538,
MIPS_REG_COP0SEL_TRACECONTROL2 = 539,
MIPS_REG_COP0SEL_TRACECONTROL3 = 540,
MIPS_REG_COP0SEL_USERTRACEDATA1 = 541,
MIPS_REG_COP0SEL_USERTRACEDATA2 = 542,
MIPS_REG_COP0SEL_VPECONF0 = 543,
MIPS_REG_COP0SEL_VPECONF1 = 544,
MIPS_REG_COP0SEL_WATCHHI0 = 545,
MIPS_REG_COP0SEL_WATCHHI1 = 546,
MIPS_REG_COP0SEL_WATCHHI2 = 547,
MIPS_REG_COP0SEL_WATCHHI3 = 548,
MIPS_REG_COP0SEL_WATCHHI4 = 549,
MIPS_REG_COP0SEL_WATCHHI5 = 550,
MIPS_REG_COP0SEL_WATCHHI6 = 551,
MIPS_REG_COP0SEL_WATCHHI7 = 552,
MIPS_REG_COP0SEL_WATCHHI8 = 553,
MIPS_REG_COP0SEL_WATCHHI9 = 554,
MIPS_REG_COP0SEL_WATCHHI10 = 555,
MIPS_REG_COP0SEL_WATCHHI11 = 556,
MIPS_REG_COP0SEL_WATCHHI12 = 557,
MIPS_REG_COP0SEL_WATCHHI13 = 558,
MIPS_REG_COP0SEL_WATCHHI14 = 559,
MIPS_REG_COP0SEL_WATCHHI15 = 560,
MIPS_REG_COP0SEL_WATCHLO0 = 561,
MIPS_REG_COP0SEL_WATCHLO1 = 562,
MIPS_REG_COP0SEL_WATCHLO2 = 563,
MIPS_REG_COP0SEL_WATCHLO3 = 564,
MIPS_REG_COP0SEL_WATCHLO4 = 565,
MIPS_REG_COP0SEL_WATCHLO5 = 566,
MIPS_REG_COP0SEL_WATCHLO6 = 567,
MIPS_REG_COP0SEL_WATCHLO7 = 568,
MIPS_REG_COP0SEL_WATCHLO8 = 569,
MIPS_REG_COP0SEL_WATCHLO9 = 570,
MIPS_REG_COP0SEL_WATCHLO10 = 571,
MIPS_REG_COP0SEL_WATCHLO11 = 572,
MIPS_REG_COP0SEL_WATCHLO12 = 573,
MIPS_REG_COP0SEL_WATCHLO13 = 574,
MIPS_REG_COP0SEL_WATCHLO14 = 575,
MIPS_REG_COP0SEL_WATCHLO15 = 576,
MIPS_REG_D0_64 = 577,
MIPS_REG_D1_64 = 578,
MIPS_REG_D2_64 = 579,
MIPS_REG_D3_64 = 580,
MIPS_REG_D4_64 = 581,
MIPS_REG_D5_64 = 582,
MIPS_REG_D6_64 = 583,
MIPS_REG_D7_64 = 584,
MIPS_REG_D8_64 = 585,
MIPS_REG_D9_64 = 586,
MIPS_REG_D10_64 = 587,
MIPS_REG_D11_64 = 588,
MIPS_REG_D12_64 = 589,
MIPS_REG_D13_64 = 590,
MIPS_REG_D14_64 = 591,
MIPS_REG_D15_64 = 592,
MIPS_REG_D16_64 = 593,
MIPS_REG_D17_64 = 594,
MIPS_REG_D18_64 = 595,
MIPS_REG_D19_64 = 596,
MIPS_REG_D20_64 = 597,
MIPS_REG_D21_64 = 598,
MIPS_REG_D22_64 = 599,
MIPS_REG_D23_64 = 600,
MIPS_REG_D24_64 = 601,
MIPS_REG_D25_64 = 602,
MIPS_REG_D26_64 = 603,
MIPS_REG_D27_64 = 604,
MIPS_REG_D28_64 = 605,
MIPS_REG_D29_64 = 606,
MIPS_REG_D30_64 = 607,
MIPS_REG_D31_64 = 608,
MIPS_REG_DSPOUTFLAG16_19 = 609,
MIPS_REG_HI0_64 = 610,
MIPS_REG_K0_64 = 611,
MIPS_REG_K1_64 = 612,
MIPS_REG_LO0_64 = 613,
MIPS_REG_S0_64 = 614,
MIPS_REG_S1_64 = 615,
MIPS_REG_S2_64 = 616,
MIPS_REG_S3_64 = 617,
MIPS_REG_S4_64 = 618,
MIPS_REG_S5_64 = 619,
MIPS_REG_S6_64 = 620,
MIPS_REG_S7_64 = 621,
MIPS_REG_T0_64 = 622,
MIPS_REG_T1_64 = 623,
MIPS_REG_T2_64 = 624,
MIPS_REG_T3_64 = 625,
MIPS_REG_T4_64 = 626,
MIPS_REG_T5_64 = 627,
MIPS_REG_T6_64 = 628,
MIPS_REG_T7_64 = 629,
MIPS_REG_T8_64 = 630,
MIPS_REG_T9_64 = 631,
MIPS_REG_V0_64 = 632,
MIPS_REG_V1_64 = 633,
MIPS_REG_COP0SEL_GUESTCTL0EXT = 634,
MIPS_REG_ENDING, // 635
external/capstone/arch/Mips/MipsGenDisassemblerTables.inc
Vendored
+12133
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenInstrInfo.inc
Vendored
+7478
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenRegisterInfo.inc
Vendored
+3122
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsGenSubtargetInfo.inc
Vendored
+83
View File
@@ -0,0 +1,83 @@
/* Capstone Disassembly Engine, https://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2024 */
/* Automatically generated file by Capstone's LLVM TableGen Disassembler Backend. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Do not edit. */
/* Capstone's LLVM TableGen Backends: */
/* https://github.com/capstone-engine/llvm-capstone */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
enum {
Mips_FeatureAbs2008 = 0,
Mips_FeatureCRC = 1,
Mips_FeatureCnMips = 2,
Mips_FeatureCnMipsP = 3,
Mips_FeatureDSP = 4,
Mips_FeatureDSPR2 = 5,
Mips_FeatureDSPR3 = 6,
Mips_FeatureEVA = 7,
Mips_FeatureFP64Bit = 8,
Mips_FeatureFPXX = 9,
Mips_FeatureGINV = 10,
Mips_FeatureGP64Bit = 11,
Mips_FeatureI7200 = 12,
Mips_FeatureLongCalls = 13,
Mips_FeatureMSA = 14,
Mips_FeatureMT = 15,
Mips_FeatureMicroMips = 16,
Mips_FeatureMips1 = 17,
Mips_FeatureMips2 = 18,
Mips_FeatureMips3 = 19,
Mips_FeatureMips3D = 20,
Mips_FeatureMips3_32 = 21,
Mips_FeatureMips3_32r2 = 22,
Mips_FeatureMips4 = 23,
Mips_FeatureMips4_32 = 24,
Mips_FeatureMips4_32r2 = 25,
Mips_FeatureMips5 = 26,
Mips_FeatureMips5_32r2 = 27,
Mips_FeatureMips16 = 28,
Mips_FeatureMips32 = 29,
Mips_FeatureMips32r2 = 30,
Mips_FeatureMips32r3 = 31,
Mips_FeatureMips32r5 = 32,
Mips_FeatureMips32r6 = 33,
Mips_FeatureMips64 = 34,
Mips_FeatureMips64r2 = 35,
Mips_FeatureMips64r3 = 36,
Mips_FeatureMips64r5 = 37,
Mips_FeatureMips64r6 = 38,
Mips_FeatureNMS1 = 39,
Mips_FeatureNaN2008 = 40,
Mips_FeatureNanoMips = 41,
Mips_FeatureNoABICalls = 42,
Mips_FeatureNoMadd4 = 43,
Mips_FeatureNoOddSPReg = 44,
Mips_FeaturePCRel = 45,
Mips_FeaturePTR64Bit = 46,
Mips_FeatureRelax = 47,
Mips_FeatureSingleFloat = 48,
Mips_FeatureSoftFloat = 49,
Mips_FeatureSym32 = 50,
Mips_FeatureTLB = 51,
Mips_FeatureUseAbsoluteJumpTables = 52,
Mips_FeatureUseIndirectJumpsHazard = 53,
Mips_FeatureUseTCCInDIV = 54,
Mips_FeatureVFPU = 55,
Mips_FeatureVirt = 56,
Mips_FeatureXGOT = 57,
Mips_FeatureXformHw110880 = 58,
Mips_ImplP5600 = 59,
Mips_NumSubtargetFeatures = 60
};
#endif // GET_SUBTARGETINFO_ENUM
external/capstone/arch/Mips/MipsInstPrinter.c
Vendored
+741
View File
@@ -0,0 +1,741 @@
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints an Mips MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "MipsMapping.h"
#include "MipsInstPrinter.h"
#define GET_SUBTARGETINFO_ENUM
#include "MipsGenSubtargetInfo.inc"
#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"
#define GET_REGINFO_ENUM
#include "MipsGenRegisterInfo.inc"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
#define DEBUG_TYPE "asm-printer"
#define PRINT_ALIAS_INSTR
#include "MipsGenAsmWriter.inc"
static bool isReg(const MCInst *MI, unsigned OpNo, unsigned R)
{
return MCOperand_getReg(MCInst_getOperand((MCInst *)MI, (OpNo))) == R;
}
static const char *MipsFCCToString(Mips_CondCode CC)
{
switch (CC) {
case Mips_FCOND_F:
case Mips_FCOND_T:
return "f";
case Mips_FCOND_UN:
case Mips_FCOND_OR:
return "un";
case Mips_FCOND_OEQ:
case Mips_FCOND_UNE:
return "eq";
case Mips_FCOND_UEQ:
case Mips_FCOND_ONE:
return "ueq";
case Mips_FCOND_OLT:
case Mips_FCOND_UGE:
return "olt";
case Mips_FCOND_ULT:
case Mips_FCOND_OGE:
return "ult";
case Mips_FCOND_OLE:
case Mips_FCOND_UGT:
return "ole";
case Mips_FCOND_ULE:
case Mips_FCOND_OGT:
return "ule";
case Mips_FCOND_SF:
case Mips_FCOND_ST:
return "sf";
case Mips_FCOND_NGLE:
case Mips_FCOND_GLE:
return "ngle";
case Mips_FCOND_SEQ:
case Mips_FCOND_SNE:
return "seq";
case Mips_FCOND_NGL:
case Mips_FCOND_GL:
return "ngl";
case Mips_FCOND_LT:
case Mips_FCOND_NLT:
return "lt";
case Mips_FCOND_NGE:
case Mips_FCOND_GE:
return "nge";
case Mips_FCOND_LE:
case Mips_FCOND_NLE:
return "le";
case Mips_FCOND_NGT:
case Mips_FCOND_GT:
return "ngt";
}
CS_ASSERT_RET_VAL(0 && "Impossible condition code!", NULL);
return "";
}
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName);
static void printRegName(MCInst *MI, SStream *OS, MCRegister Reg)
{
int syntax_opt = MI->csh->syntax;
if (!(syntax_opt & CS_OPT_SYNTAX_NO_DOLLAR)) {
SStream_concat1(OS, '$');
}
SStream_concat0(OS, Mips_LLVM_getRegisterName(Reg, syntax_opt & CS_OPT_SYNTAX_NOREGNAME));
}
static void patch_cs_printer(MCInst *MI, SStream *O) {
// replace '# 16 bit inst' to empty.
SStream_replc(O, '#', 0);
SStream_trimls(O);
if (MI->csh->syntax & CS_OPT_SYNTAX_NO_DOLLAR) {
char *dollar = strchr(O->buffer, '$');
if (!dollar) {
return;
}
size_t dollar_len = strlen(dollar + 1);
// to include `\0`
memmove(dollar, dollar + 1, dollar_len + 1);
}
}
static void patch_cs_detail_operand_reg(cs_mips_op *op, unsigned reg, unsigned access) {
op->type = MIPS_OP_REG;
op->reg = reg;
op->is_reglist = false;
op->access = access;
}
static void patch_cs_details(MCInst *MI) {
if (!detail_is_set(MI))
return;
cs_mips_op *op0 = NULL, *op1 = NULL, *op2 = NULL;
unsigned opcode = MCInst_getOpcode(MI);
unsigned n_ops = MCInst_getNumOperands(MI);
switch(opcode) {
/* mips r2 to r5 only 64bit */
case Mips_DSDIV: /// ddiv $$zero, $rs, $rt
/* fall-thru */
case Mips_DUDIV: /// ddivu $$zero, $rs, $rt
if (n_ops != 2) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -3);
op1 = Mips_get_detail_op(MI, -2);
op2 = Mips_get_detail_op(MI, -1);
// move all details by one and add $zero reg
*op2 = *op1;
*op1 = *op0;
patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO_64, CS_AC_WRITE);
return;
/* mips r2 to r5 only */
case Mips_SDIV: /// div $$zero, $rs, $rt
/* fall-thru */
case Mips_UDIV: /// divu $$zero, $rs, $rt
/* fall-thru */
/* microMIPS only */
case Mips_SDIV_MM: /// div $$zero, $rs, $rt
/* fall-thru */
case Mips_UDIV_MM: /// divu $$zero, $rs, $rt
/* fall-thru */
/* MIPS16 only */
case Mips_DivRxRy16: /// div $$zero, $rx, $ry
/* fall-thru */
case Mips_DivuRxRy16: /// divu $$zero, $rx, $ry
if (n_ops != 2) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -3);
op1 = Mips_get_detail_op(MI, -2);
op2 = Mips_get_detail_op(MI, -1);
// move all details by one and add $zero reg
*op2 = *op1;
*op1 = *op0;
patch_cs_detail_operand_reg(op0, MIPS_REG_ZERO, CS_AC_WRITE);
return;
case Mips_AddiuSpImm16: /// addiu $$sp, imm8
/* fall-thru */
case Mips_AddiuSpImmX16: /// addiu $$sp, imm8
if (n_ops != 1) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -2);
op1 = Mips_get_detail_op(MI, -1);
// move all details by one and add $sp reg
*op1 = *op0;
patch_cs_detail_operand_reg(op0, MIPS_REG_SP, CS_AC_READ_WRITE);
return;
case Mips_JrcRa16: /// jrc $ra
/* fall-thru */
case Mips_JrRa16: /// jr $ra
if (n_ops > 0) {
return;
}
Mips_inc_op_count(MI);
op0 = Mips_get_detail_op(MI, -1);
patch_cs_detail_operand_reg(op0, MIPS_REG_RA, CS_AC_READ);
return;
default:
return;
}
}
void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O) {
bool useAliasDetails = map_use_alias_details(MI);
if (!useAliasDetails) {
SStream_Close(O);
printInstruction(MI, Address, O);
SStream_Open(O);
map_set_fill_detail_ops(MI, false);
}
if (printAliasInstr(MI, Address, O) ||
printAlias4(MI, Address, O)) {
MCInst_setIsAlias(MI, true);
} else {
printInstruction(MI, Address, O);
}
patch_cs_printer(MI, O);
patch_cs_details(MI);
if (!useAliasDetails) {
map_set_fill_detail_ops(MI, true);
}
}
void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
switch (MCInst_getOpcode(MI)) {
default:
break;
case Mips_AND16_NM:
case Mips_XOR16_NM:
case Mips_OR16_NM:
if (MCInst_getNumOperands(MI) == 2 && OpNo == 2)
OpNo = 0; // rt, rs -> rt, rs, rt
break;
case Mips_ADDu4x4_NM:
case Mips_MUL4x4_NM:
if (MCInst_getNumOperands(MI) == 2 && OpNo > 0)
OpNo = OpNo - 1; // rt, rs -> rt, rt, rs
break;
}
MCOperand *Op = MCInst_getOperand(MI, (OpNo));
if (MCOperand_isReg(Op)) {
add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo);
printRegName(MI, O, MCOperand_getReg(Op));
return;
}
if (MCOperand_isImm(Op)) {
switch (MCInst_getOpcode(MI)) {
case Mips_LI48_NM:
case Mips_ANDI16_NM:
case Mips_ANDI_NM:
case Mips_ORI_NM:
case Mips_XORI_NM:
case Mips_TEQ_NM:
case Mips_TNE_NM:
case Mips_SIGRIE_NM:
case Mips_SDBBP_NM:
case Mips_SDBBP16_NM:
case Mips_BREAK_NM:
case Mips_BREAK16_NM:
case Mips_SYSCALL_NM:
case Mips_SYSCALL16_NM:
case Mips_WAIT_NM:
CONCAT(printUImm, CONCAT(32, 0))
(MI, OpNo, O);
break;
default:
add_cs_detail(MI, Mips_OP_GROUP_Operand, OpNo);
printInt64(O, MCOperand_getImm(Op));
break;
}
return;
}
}
static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
add_cs_detail(MI, Mips_OP_GROUP_JumpOperand, OpNo);
MCOperand *Op = MCInst_getOperand(MI, (OpNo));
if (MCOperand_isReg(Op))
return printRegName(MI, O, MCOperand_getReg(Op));
// only the upper bits are needed.
uint64_t Base = MI->address & ~0x0fffffffull;
uint64_t Target = MCOperand_getImm(Op);
printInt64(O, Base | Target);
}
static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo, SStream *O)
{
add_cs_detail(MI, Mips_OP_GROUP_BranchOperand, OpNo);
MCOperand *Op = MCInst_getOperand(MI, (OpNo));
if (MCOperand_isReg(Op))
return printRegName(MI, O, MCOperand_getReg(Op));
uint64_t Target = Address + MCOperand_getImm(Op);
printInt64(O, Target);
}
#define DEFINE_printUImm(Bits) \
static void CONCAT(printUImm, CONCAT(Bits, 0))(MCInst * MI, int opNum, \
SStream *O) \
{ \
add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, 0)), opNum); \
MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
if (MCOperand_isImm(MO)) { \
uint64_t Imm = MCOperand_getImm(MO); \
Imm &= (((uint64_t)1) << Bits) - 1; \
printUInt64(O, Imm); \
return; \
} \
MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
printRegName(MI, O, MCOperand_getReg(Op)); \
}
#define DEFINE_printUImm_2(Bits, Offset) \
static void CONCAT(printUImm, CONCAT(Bits, Offset))(MCInst * MI, int opNum, \
SStream *O) \
{ \
add_cs_detail(MI, CONCAT(Mips_OP_GROUP_UImm, CONCAT(Bits, Offset)), \
opNum); \
MCOperand *MO = MCInst_getOperand(MI, (opNum)); \
if (MCOperand_isImm(MO)) { \
uint64_t Imm = MCOperand_getImm(MO); \
Imm -= Offset; \
Imm &= (1 << Bits) - 1; \
Imm += Offset; \
printUInt64(O, Imm); \
return; \
} \
MCOperand *Op = MCInst_getOperand(MI, (opNum)); \
printRegName(MI, O, MCOperand_getReg(Op)); \
}
DEFINE_printUImm(0);
DEFINE_printUImm(1);
DEFINE_printUImm(10);
DEFINE_printUImm(12);
DEFINE_printUImm(16);
DEFINE_printUImm(2);
DEFINE_printUImm(20);
DEFINE_printUImm(26);
DEFINE_printUImm(3);
DEFINE_printUImm(32);
DEFINE_printUImm(4);
DEFINE_printUImm(5);
DEFINE_printUImm(6);
DEFINE_printUImm(7);
DEFINE_printUImm(8);
DEFINE_printUImm_2(2, 1);
DEFINE_printUImm_2(5, 1);
DEFINE_printUImm_2(5, 32);
DEFINE_printUImm_2(5, 33);
DEFINE_printUImm_2(6, 1);
DEFINE_printUImm_2(6, 2);
static void printMemOperand(MCInst *MI, int opNum, SStream *O)
{
// Load/Store memory operands -- imm($reg)
// If PIC target the target is loaded as the
// pattern lw $25,%call16($28)
// opNum can be invalid if instruction had reglist as operand.
// MemOperand is always last operand of instruction (base + offset).
switch (MCInst_getOpcode(MI)) {
default:
break;
case Mips_SWM32_MM:
case Mips_LWM32_MM:
case Mips_SWM16_MM:
case Mips_SWM16_MMR6:
case Mips_LWM16_MM:
case Mips_LWM16_MMR6:
opNum = MCInst_getNumOperands(MI) - 2;
break;
}
set_mem_access(MI, true);
// Index register is encoded as immediate value
// in case of nanoMIPS indexed instructions
switch (MCInst_getOpcode(MI)) {
// No offset needed for paired LL/SC
case Mips_LLWP_NM:
case Mips_SCWP_NM:
break;
case Mips_LWX_NM:
case Mips_LWXS_NM:
case Mips_LWXS16_NM:
case Mips_LBX_NM:
case Mips_LBUX_NM:
case Mips_LHX_NM:
case Mips_LHUX_NM:
case Mips_LHXS_NM:
case Mips_LHUXS_NM:
case Mips_SWX_NM:
case Mips_SWXS_NM:
case Mips_SBX_NM:
case Mips_SHX_NM:
case Mips_SHXS_NM:
if (!MCOperand_isReg(MCInst_getOperand(MI, (opNum + 1)))) {
add_cs_detail(MI, Mips_OP_GROUP_MemOperand, (opNum + 1));
printRegName(MI, O, MCOperand_getImm(MCInst_getOperand(
MI, (opNum + 1))));
break;
}
// Fall through
default:
printOperand((MCInst *)MI, opNum + 1, O);
break;
}
SStream_concat0(O, "(");
printOperand((MCInst *)MI, opNum, O);
SStream_concat0(O, ")");
set_mem_access(MI, false);
}
static void printMemOperandEA(MCInst *MI, int opNum, SStream *O)
{
// when using stack locations for not load/store instructions
// print the same way as all normal 3 operand instructions.
printOperand((MCInst *)MI, opNum, O);
SStream_concat0(O, ", ");
printOperand((MCInst *)MI, opNum + 1, O);
}
static void printFCCOperand(MCInst *MI, int opNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (opNum));
SStream_concat0(O,
MipsFCCToString((Mips_CondCode)MCOperand_getImm(MO)));
}
static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo, SStream *OS, bool IsBranch)
{
SStream_concat(OS, "%s%s", "\t", Str);
SStream_concat0(OS, "\t");
if (IsBranch)
printBranchOperand((MCInst *)MI, Address, OpNo, OS);
else
printOperand((MCInst *)MI, OpNo, OS);
return true;
}
static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, SStream *OS, bool IsBranch)
{
printAlias(Str, MI, Address, OpNo0, OS, IsBranch);
SStream_concat0(OS, ", ");
if (IsBranch)
printBranchOperand((MCInst *)MI, Address, OpNo1, OS);
else
printOperand((MCInst *)MI, OpNo1, OS);
return true;
}
static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS)
{
printAlias(Str, MI, Address, OpNo0, OS, false);
SStream_concat0(OS, ", ");
printOperand((MCInst *)MI, OpNo1, OS);
SStream_concat0(OS, ", ");
printOperand((MCInst *)MI, OpNo2, OS);
return true;
}
static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS)
{
switch (MCInst_getOpcode(MI)) {
case Mips_BEQ:
case Mips_BEQ_MM:
// beq $zero, $zero, $L2 => b $L2
// beq $r0, $zero, $L2 => beqz $r0, $L2
return (isReg(MI, 0, Mips_ZERO) &&
isReg(MI, 1, Mips_ZERO) &&
printAlias("b", MI, Address, 2, OS, true)) ||
(isReg(MI, 1, Mips_ZERO) &&
printAlias2("beqz", MI, Address, 0, 2, OS, true));
case Mips_BEQ64:
// beq $r0, $zero, $L2 => beqz $r0, $L2
return isReg(MI, 1, Mips_ZERO_64) &&
printAlias2("beqz", MI, Address, 0, 2, OS, true);
case Mips_BNE:
case Mips_BNE_MM:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg(MI, 1, Mips_ZERO) &&
printAlias2("bnez", MI, Address, 0, 2, OS, true);
case Mips_BNE64:
// bne $r0, $zero, $L2 => bnez $r0, $L2
return isReg(MI, 1, Mips_ZERO_64) &&
printAlias2("bnez", MI, Address, 0, 2, OS, true);
case Mips_BGEZAL:
// bgezal $zero, $L1 => bal $L1
return isReg(MI, 0, Mips_ZERO) &&
printAlias("bal", MI, Address, 1, OS, true);
case Mips_BC1T:
// bc1t $fcc0, $L1 => bc1t $L1
return isReg(MI, 0, Mips_FCC0) &&
printAlias("bc1t", MI, Address, 1, OS, true);
case Mips_BC1F:
// bc1f $fcc0, $L1 => bc1f $L1
return isReg(MI, 0, Mips_FCC0) &&
printAlias("bc1f", MI, Address, 1, OS, true);
case Mips_JALR:
// jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
return (isReg(MI, 0, Mips_ZERO) &&
printAlias("jr", MI, Address, 1, OS, false)) ||
(isReg(MI, 0, Mips_RA) &&
printAlias("jalr", MI, Address, 1, OS, false));
case Mips_JALR64:
// jalr $zero, $r1 => jr $r1
// jalr $ra, $r1 => jalr $r1
return (isReg(MI, 0, Mips_ZERO_64) &&
printAlias("jr", MI, Address, 1, OS, false)) ||
(isReg(MI, 0, Mips_RA_64) &&
printAlias("jalr", MI, Address, 1, OS, false));
case Mips_NOR:
case Mips_NOR_MM:
case Mips_NOR_MMR6:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg(MI, 2, Mips_ZERO) &&
printAlias2("not", MI, Address, 0, 1, OS, false);
case Mips_NOR64:
// nor $r0, $r1, $zero => not $r0, $r1
return isReg(MI, 2, Mips_ZERO_64) &&
printAlias2("not", MI, Address, 0, 1, OS, false);
case Mips_OR:
case Mips_ADDu:
// or $r0, $r1, $zero => move $r0, $r1
// addu $r0, $r1, $zero => move $r0, $r1
return isReg(MI, 2, Mips_ZERO) &&
printAlias2("move", MI, Address, 0, 1, OS, false);
case Mips_LI48_NM:
case Mips_LI16_NM:
// li[16/48] $r0, imm => li $r0, imm
return printAlias2("li", MI, Address, 0, 1, OS, false);
case Mips_ADDIU_NM:
case Mips_ADDIUNEG_NM:
if (isReg(MI, 1, Mips_ZERO_NM))
return printAlias2("li", MI, Address, 0, 2, OS, false);
else
return printAlias3("addiu", MI, Address, 0, 1, 2, OS);
case Mips_ADDIU48_NM:
case Mips_ADDIURS5_NM:
case Mips_ADDIUR1SP_NM:
case Mips_ADDIUR2_NM:
case Mips_ADDIUGPB_NM:
case Mips_ADDIUGPW_NM:
return printAlias3("addiu", MI, Address, 0, 1, 2, OS);
case Mips_ANDI16_NM:
case Mips_ANDI_NM:
// andi[16/32] $r0, $r1, imm => andi $r0, $r1, imm
return printAlias3("andi", MI, Address, 0, 1, 2, OS);
default:
return false;
}
}
static void printRegisterList(MCInst *MI, int opNum, SStream *O)
{
// - 2 because register List is always first operand of instruction and it is
// always followed by memory operand (base + offset).
add_cs_detail(MI, Mips_OP_GROUP_RegisterList, opNum);
for (int i = opNum, e = MCInst_getNumOperands(MI) - 2; i != e; ++i) {
if (i != opNum)
SStream_concat0(O, ", ");
printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (i))));
}
}
static void printNanoMipsRegisterList(MCInst *MI, int OpNum, SStream *O)
{
add_cs_detail(MI, Mips_OP_GROUP_NanoMipsRegisterList, OpNum);
for (unsigned I = OpNum; I < MCInst_getNumOperands(MI); I++) {
SStream_concat0(O, ", ");
printRegName(MI, O, MCOperand_getReg(MCInst_getOperand(MI, (I))));
}
}
static void printHi20(MCInst *MI, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
add_cs_detail(MI, Mips_OP_GROUP_Hi20, OpNum);
SStream_concat0(O, "%hi(");
printUInt64(O, MCOperand_getImm(MO));
SStream_concat0(O, ")");
} else
printOperand(MI, OpNum, O);
}
static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
add_cs_detail(MI, Mips_OP_GROUP_Hi20PCRel, OpNum);
SStream_concat0(O, "%pcrel_hi(");
printUInt64(O, MCOperand_getImm(MO) + Address);
SStream_concat0(O, ")");
} else
printOperand(MI, OpNum, O);
}
static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O)
{
MCOperand *MO = MCInst_getOperand(MI, (OpNum));
if (MCOperand_isImm(MO)) {
add_cs_detail(MI, Mips_OP_GROUP_PCRel, OpNum);
printUInt64(O, MCOperand_getImm(MO) + Address);
}
else
printOperand(MI, OpNum, O);
}
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName)
{
if (!RegNo || RegNo >= MIPS_REG_ENDING) {
return NULL;
}
if (noRegName) {
return getRegisterName(RegNo);
}
switch(RegNo) {
case MIPS_REG_AT:
case MIPS_REG_AT_64:
return "at";
case MIPS_REG_A0:
case MIPS_REG_A0_64:
return "a0";
case MIPS_REG_A1:
case MIPS_REG_A1_64:
return "a1";
case MIPS_REG_A2:
case MIPS_REG_A2_64:
return "a2";
case MIPS_REG_A3:
case MIPS_REG_A3_64:
return "a3";
case MIPS_REG_K0:
case MIPS_REG_K0_64:
return "k0";
case MIPS_REG_K1:
case MIPS_REG_K1_64:
return "k1";
case MIPS_REG_S0:
case MIPS_REG_S0_64:
return "s0";
case MIPS_REG_S1:
case MIPS_REG_S1_64:
return "s1";
case MIPS_REG_S2:
case MIPS_REG_S2_64:
return "s2";
case MIPS_REG_S3:
case MIPS_REG_S3_64:
return "s3";
case MIPS_REG_S4:
case MIPS_REG_S4_64:
return "s4";
case MIPS_REG_S5:
case MIPS_REG_S5_64:
return "s5";
case MIPS_REG_S6:
case MIPS_REG_S6_64:
return "s6";
case MIPS_REG_S7:
case MIPS_REG_S7_64:
return "s7";
case MIPS_REG_T0:
case MIPS_REG_T0_64:
return "t0";
case MIPS_REG_T1:
case MIPS_REG_T1_64:
return "t1";
case MIPS_REG_T2:
case MIPS_REG_T2_64:
return "t2";
case MIPS_REG_T3:
case MIPS_REG_T3_64:
return "t3";
case MIPS_REG_T4:
case MIPS_REG_T4_64:
return "t4";
case MIPS_REG_T5:
case MIPS_REG_T5_64:
return "t5";
case MIPS_REG_T6:
case MIPS_REG_T6_64:
return "t6";
case MIPS_REG_T7:
case MIPS_REG_T7_64:
return "t7";
case MIPS_REG_T8:
case MIPS_REG_T8_64:
return "t8";
case MIPS_REG_T9:
case MIPS_REG_T9_64:
return "t9";
case MIPS_REG_V0:
case MIPS_REG_V0_64:
return "v0";
case MIPS_REG_V1:
case MIPS_REG_V1_64:
return "v1";
default:
return getRegisterName(RegNo);
}
}
external/capstone/arch/Mips/MipsInstPrinter.h
Vendored
+158
View File
@@ -0,0 +1,158 @@
#include "../../SStream.h"
#include "../../MCInst.h"
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
/* Rot127 <unisono@quyllur.org> 2022-2023 */
/* Automatically translated source file from LLVM. */
/* LLVM-commit: <commit> */
/* LLVM-tag: <tag> */
/* Only small edits allowed. */
/* For multiple similar edits, please create a Patch for the translator. */
/* Capstone's C++ file translator: */
/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
//=== MipsInstPrinter.h - Convert Mips MCInst to assembly syntax -*- C++ -*-==//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This class prints a Mips MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H
#define LLVM_LIB_TARGET_MIPS_MCTARGETDESC_MIPSINSTPRINTER_H
#include <stdio.h>
#include <string.h>
#include <stdlib.h>
#include <capstone/platform.h>
#include "../../MCInstPrinter.h"
#include "../../cs_priv.h"
#define CONCAT(a, b) CONCAT_(a, b)
#define CONCAT_(a, b) a##_##b
// These enumeration declarations were originally in MipsInstrInfo.h but
// had to be moved here to avoid circular dependencies between
// LLVMMipsCodeGen and LLVMMipsAsmPrinter.
// CS namespace begin: Mips
// Mips Branch Codes
typedef enum MipsFPBranchCode {
Mips_BRANCH_F,
Mips_BRANCH_T,
Mips_BRANCH_FL,
Mips_BRANCH_TL,
Mips_BRANCH_INVALID
} Mips_FPBranchCode;
// Mips Condition Codes
typedef enum MipsCondCode {
// To be used with float branch True
Mips_FCOND_F,
Mips_FCOND_UN,
Mips_FCOND_OEQ,
Mips_FCOND_UEQ,
Mips_FCOND_OLT,
Mips_FCOND_ULT,
Mips_FCOND_OLE,
Mips_FCOND_ULE,
Mips_FCOND_SF,
Mips_FCOND_NGLE,
Mips_FCOND_SEQ,
Mips_FCOND_NGL,
Mips_FCOND_LT,
Mips_FCOND_NGE,
Mips_FCOND_LE,
Mips_FCOND_NGT,
// To be used with float branch False
// This conditions have the same mnemonic as the
// above ones, but are used with a branch False;
Mips_FCOND_T,
Mips_FCOND_OR,
Mips_FCOND_UNE,
Mips_FCOND_ONE,
Mips_FCOND_UGE,
Mips_FCOND_OGE,
Mips_FCOND_UGT,
Mips_FCOND_OGT,
Mips_FCOND_ST,
Mips_FCOND_GLE,
Mips_FCOND_SNE,
Mips_FCOND_GL,
Mips_FCOND_NLT,
Mips_FCOND_GE,
Mips_FCOND_NLE,
Mips_FCOND_GT
} Mips_CondCode;
static const char *MipsFCCToString(Mips_CondCode CC);
// CS namespace end: Mips
// end namespace Mips
// Autogenerated by tblgen.
static const char *getRegisterName(unsigned RegNo);
static void printInstruction(MCInst *MI, uint64_t Address, SStream *O);
static bool printAliasInstr(MCInst *MI, uint64_t Address, SStream *OS);
static void printCustomAliasOperand(MCInst *MI, uint64_t Address, unsigned OpIdx,
unsigned PrintMethodIdx, SStream *O);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printJumpOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printBranchOperand(MCInst *MI, uint64_t Address, unsigned OpNo,
SStream *O);
#define DECLARE_printUImm_2(Bits, Offset) \
static void CONCAT(printUImm, CONCAT(Bits, Offset))( \
MCInst *MI, int opNum, SStream *O)
#define DECLARE_printUImm(Bits) \
static void CONCAT(printUImm, CONCAT(Bits, 0))( \
MCInst *MI, int opNum, SStream *O)
DECLARE_printUImm(0);
DECLARE_printUImm(1);
DECLARE_printUImm(10);
DECLARE_printUImm(12);
DECLARE_printUImm(16);
DECLARE_printUImm(2);
DECLARE_printUImm(20);
DECLARE_printUImm(26);
DECLARE_printUImm(3);
DECLARE_printUImm(32);
DECLARE_printUImm(4);
DECLARE_printUImm(5);
DECLARE_printUImm(6);
DECLARE_printUImm(7);
DECLARE_printUImm(8);
DECLARE_printUImm_2(2, 1);
DECLARE_printUImm_2(5, 1);
DECLARE_printUImm_2(5, 32);
DECLARE_printUImm_2(5, 33);
DECLARE_printUImm_2(6, 1);
DECLARE_printUImm_2(6, 2);
static void printMemOperand(MCInst *MI, int opNum, SStream *O);
static void printMemOperandEA(MCInst *MI, int opNum, SStream *O);
static void printFCCOperand(MCInst *MI, int opNum, SStream *O);
static bool printAlias(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo, SStream *OS, bool IsBranch);
static bool printAlias2(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, SStream *OS,
bool IsBranch);
static bool printAlias3(const char *Str, const MCInst *MI, uint64_t Address,
unsigned OpNo0, unsigned OpNo1, unsigned OpNo2, SStream *OS);
static bool printAlias4(const MCInst *MI, uint64_t Address, SStream *OS);
static void printRegisterList(MCInst *MI, int opNum, SStream *O);
static void printNanoMipsRegisterList(MCInst *MI, int opNum, SStream *O);
static void printHi20(MCInst *MI, int OpNum, SStream *O);
static void printHi20PCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
static void printPCRel(MCInst *MI, uint64_t Address, int OpNum, SStream *O);
#endif
external/capstone/arch/Mips/MipsLinkage.h
Vendored
+21
View File
@@ -0,0 +1,21 @@
/* Capstone Disassembly Engine */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifndef CS_MIPS_LINKAGE_H
#define CS_MIPS_LINKAGE_H
// Function definitions to call static LLVM functions.
#include "../../MCDisassembler.h"
#include "../../MCInst.h"
#include "../../MCRegisterInfo.h"
#include "../../SStream.h"
#include "capstone/capstone.h"
const char *Mips_LLVM_getRegisterName(unsigned RegNo, bool noRegName);
void Mips_LLVM_printInst(MCInst *MI, uint64_t Address, SStream *O);
DecodeStatus Mips_LLVM_getInstruction(MCInst *Instr, uint64_t *Size,
const uint8_t *Bytes, size_t BytesLen,
uint64_t Address, SStream *CStream);
#endif // CS_MIPS_LINKAGE_H
external/capstone/arch/Mips/MipsMapping.c
Vendored
+508
View File
@@ -0,0 +1,508 @@
/* Capstone Disassembly Engine */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifdef CAPSTONE_HAS_MIPS
#include <stdio.h>
#include <string.h>
#include <capstone/capstone.h>
#include <capstone/mips.h>
#include "../../Mapping.h"
#include "../../MCDisassembler.h"
#include "../../cs_priv.h"
#include "../../cs_simple_types.h"
#include "MipsMapping.h"
#include "MipsLinkage.h"
#include "MipsDisassembler.h"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "MipsGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "MipsGenInstrInfo.inc"
void Mips_init_mri(MCRegisterInfo *MRI)
{
MCRegisterInfo_InitMCRegisterInfo(MRI, MipsRegDesc, sizeof(MipsRegDesc),
0, 0, MipsMCRegisterClasses,
ARR_SIZE(MipsMCRegisterClasses), 0, 0,
MipsRegDiffLists, 0,
MipsSubRegIdxLists,
ARR_SIZE(MipsSubRegIdxLists), 0);
}
const char *Mips_reg_name(csh handle, unsigned int reg)
{
int syntax_opt = ((cs_struct *)(uintptr_t)handle)->syntax;
return Mips_LLVM_getRegisterName(reg,
syntax_opt & CS_OPT_SYNTAX_NOREGNAME);
}
void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id)
{
// Not used by Mips. Information is set after disassembly.
}
static const char *const insn_name_maps[] = {
#include "MipsGenCSMappingInsnName.inc"
};
#ifndef CAPSTONE_DIET
static const name_map insn_alias_mnem_map[] = {
#include "MipsGenCSAliasMnemMap.inc"
// The followings aliases are not generated by LLVM table gen.
{ MIPS_INS_ALIAS_B, "b" }, // beq
{ MIPS_INS_ALIAS_BEQZ, "beqz" }, // beq
{ MIPS_INS_ALIAS_BNEZ, "bnez" }, // bne
{ MIPS_INS_ALIAS_LI, "li" }, // addiu
{ MIPS_INS_ALIAS_END, NULL },
};
#endif
const char *Mips_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id < MIPS_INS_ALIAS_END && id > MIPS_INS_ALIAS_BEGIN) {
if (id - MIPS_INS_ALIAS_BEGIN >= ARR_SIZE(insn_alias_mnem_map))
return NULL;
return insn_alias_mnem_map[id - MIPS_INS_ALIAS_BEGIN - 1].name;
}
if (id >= MIPS_INS_ENDING)
return NULL;
if (id < ARR_SIZE(insn_name_maps))
return insn_name_maps[id];
// not found
return NULL;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
{ MIPS_GRP_INVALID, NULL },
{ MIPS_GRP_JUMP, "jump" },
{ MIPS_GRP_CALL, "call" },
{ MIPS_GRP_RET, "return" },
{ MIPS_GRP_INT, "int" },
{ MIPS_GRP_IRET, "iret" },
{ MIPS_GRP_PRIVILEGE, "privilege" },
{ MIPS_GRP_BRANCH_RELATIVE, "branch_relative" },
// architecture-specific groups
#include "MipsGenCSFeatureName.inc"
};
#endif
const char *Mips_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
const insn_map mips_insns[] = {
#include "MipsGenCSMappingInsn.inc"
};
void Mips_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count)
{
uint8_t i;
uint8_t read_count, write_count;
cs_mips *mips = &(insn->detail->mips);
read_count = insn->detail->regs_read_count;
write_count = insn->detail->regs_write_count;
// implicit registers
memcpy(regs_read, insn->detail->regs_read,
read_count * sizeof(insn->detail->regs_read[0]));
memcpy(regs_write, insn->detail->regs_write,
write_count * sizeof(insn->detail->regs_write[0]));
// explicit registers
for (i = 0; i < mips->op_count; i++) {
cs_mips_op *op = &(mips->operands[i]);
switch ((int)op->type) {
case MIPS_OP_REG:
if ((op->access & CS_AC_READ) &&
!arr_exist(regs_read, read_count, op->reg)) {
regs_read[read_count] = (uint16_t)op->reg;
read_count++;
}
if ((op->access & CS_AC_WRITE) &&
!arr_exist(regs_write, write_count, op->reg)) {
regs_write[write_count] = (uint16_t)op->reg;
write_count++;
}
break;
case MIPS_OP_MEM:
// registers appeared in memory references always being read
if ((op->mem.base != MIPS_REG_INVALID) &&
!arr_exist(regs_read, read_count, op->mem.base)) {
regs_read[read_count] = (uint16_t)op->mem.base;
read_count++;
}
if ((insn->detail->writeback) &&
(op->mem.base != MIPS_REG_INVALID) &&
!arr_exist(regs_write, write_count, op->mem.base)) {
regs_write[write_count] =
(uint16_t)op->mem.base;
write_count++;
}
default:
break;
}
}
*regs_read_count = read_count;
*regs_write_count = write_count;
}
void Mips_set_instr_map_data(MCInst *MI)
{
// Fixes for missing groups.
if (MCInst_getOpcode(MI) == Mips_JR) {
unsigned Reg = MCInst_getOpVal(MI, 0);
switch (Reg) {
case MIPS_REG_RA:
case MIPS_REG_RA_64:
add_group(MI, MIPS_GRP_RET);
break;
}
}
map_cs_id(MI, mips_insns, ARR_SIZE(mips_insns));
map_implicit_reads(MI, mips_insns);
map_implicit_writes(MI, mips_insns);
map_groups(MI, mips_insns);
}
bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info)
{
uint64_t size64;
Mips_init_cs_detail(instr);
instr->MRI = (MCRegisterInfo *)info;
map_set_fill_detail_ops(instr, true);
DecodeStatus Result = Mips_LLVM_getInstruction(instr, &size64, code, code_len,
address,
info);
*size = size64;
if (Result != MCDisassembler_Fail) {
Mips_set_instr_map_data(instr);
}
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
void Mips_printer(MCInst *MI, SStream *O, void * /* MCRegisterInfo* */ info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *)info;
MI->MRI = MRI;
Mips_LLVM_printInst(MI, MI->address, O);
#ifndef CAPSTONE_DIET
map_set_alias_id(MI, O, insn_alias_mnem_map,
ARR_SIZE(insn_alias_mnem_map));
#endif
}
static void Mips_setup_op(cs_mips_op *op)
{
memset(op, 0, sizeof(cs_mips_op));
op->type = MIPS_OP_INVALID;
}
void Mips_init_cs_detail(MCInst *MI)
{
if (detail_is_set(MI)) {
unsigned int i;
memset(get_detail(MI), 0,
offsetof(cs_detail, mips) + sizeof(cs_mips));
for (i = 0; i < ARR_SIZE(Mips_get_detail(MI)->operands); i++)
Mips_setup_op(&Mips_get_detail(MI)->operands[i]);
}
}
static const map_insn_ops insn_operands[] = {
#include "MipsGenCSMappingInsnOp.inc"
};
static void Mips_set_detail_op_mem_reg(MCInst *MI, unsigned OpNum, mips_reg Reg)
{
Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
Mips_get_detail_op(MI, 0)->mem.base = Reg;
Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
}
static void Mips_set_detail_op_mem_disp(MCInst *MI, unsigned OpNum, int64_t Imm)
{
Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
Mips_get_detail_op(MI, 0)->mem.disp = Imm;
Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
}
static void Mips_set_detail_op_imm(MCInst *MI, unsigned OpNum, int64_t Imm)
{
if (!detail_is_set(MI))
return;
if (doing_mem(MI)) {
Mips_set_detail_op_mem_disp(MI, OpNum, Imm);
return;
}
Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM;
Mips_get_detail_op(MI, 0)->imm = Imm;
Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
Mips_inc_op_count(MI);
}
static void Mips_set_detail_op_uimm(MCInst *MI, unsigned OpNum, uint64_t Imm)
{
if (!detail_is_set(MI))
return;
if (doing_mem(MI)) {
Mips_set_detail_op_mem_disp(MI, OpNum, Imm);
return;
}
Mips_get_detail_op(MI, 0)->type = MIPS_OP_IMM;
Mips_get_detail_op(MI, 0)->uimm = Imm;
Mips_get_detail_op(MI, 0)->is_unsigned = true;
Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
Mips_inc_op_count(MI);
}
static void Mips_set_detail_op_reg(MCInst *MI, unsigned OpNum, mips_reg Reg,
bool is_reglist)
{
if (!detail_is_set(MI))
return;
if (doing_mem(MI)) {
Mips_set_detail_op_mem_reg(MI, OpNum, Reg);
return;
}
CS_ASSERT((map_get_op_type(MI, OpNum) & ~CS_OP_MEM) == CS_OP_REG);
Mips_get_detail_op(MI, 0)->type = MIPS_OP_REG;
Mips_get_detail_op(MI, 0)->reg = Reg;
Mips_get_detail_op(MI, 0)->is_reglist = is_reglist;
Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
Mips_inc_op_count(MI);
}
static void Mips_set_detail_op_operand(MCInst *MI, unsigned OpNum)
{
cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
int64_t value = MCInst_getOpVal(MI, OpNum);
if (op_type == CS_OP_IMM) {
Mips_set_detail_op_imm(MI, OpNum, value);
} else if (op_type == CS_OP_REG) {
Mips_set_detail_op_reg(MI, OpNum, value, false);
} else
printf("Operand type %d not handled!\n", op_type);
}
static void Mips_set_detail_op_jump(MCInst *MI, unsigned OpNum)
{
cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
if (op_type == CS_OP_IMM) {
uint64_t Base = MI->address & ~0x0fffffffull;
uint64_t Target = Base | (uint64_t)MCInst_getOpVal(MI, OpNum);
Mips_set_detail_op_uimm(MI, OpNum, Target);
} else if (op_type == CS_OP_REG) {
Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum),
false);
} else
printf("Operand type %d not handled!\n", op_type);
}
static void Mips_set_detail_op_branch(MCInst *MI, unsigned OpNum)
{
cs_op_type op_type = map_get_op_type(MI, OpNum) & ~CS_OP_MEM;
if (op_type == CS_OP_IMM) {
uint64_t Target = MI->address + MCInst_getOpVal(MI, OpNum);
Mips_set_detail_op_uimm(MI, OpNum, Target);
} else if (op_type == CS_OP_REG) {
Mips_set_detail_op_reg(MI, OpNum, MCInst_getOpVal(MI, OpNum),
false);
} else
printf("Operand type %d not handled!\n", op_type);
}
static void Mips_set_detail_op_unsigned(MCInst *MI, unsigned OpNum)
{
Mips_set_detail_op_uimm(MI, OpNum, MCInst_getOpVal(MI, OpNum));
}
static void Mips_set_detail_op_unsigned_offset(MCInst *MI, unsigned OpNum,
unsigned Bits, uint64_t Offset)
{
uint64_t Imm = MCInst_getOpVal(MI, OpNum);
Imm -= Offset;
Imm &= (((uint64_t)1) << Bits) - 1;
Imm += Offset;
Mips_set_detail_op_uimm(MI, OpNum, Imm);
}
static void Mips_set_detail_op_mem_nanomips(MCInst *MI, unsigned OpNum)
{
CS_ASSERT(doing_mem(MI));
MCOperand *Op = MCInst_getOperand(MI, OpNum);
Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
// Base is a register, but nanoMips uses the Imm value as register.
Mips_get_detail_op(MI, 0)->mem.base = MCOperand_getImm(Op);
Mips_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
}
static void Mips_set_detail_op_reglist(MCInst *MI, unsigned OpNum,
bool isNanoMips)
{
if (isNanoMips) {
for (unsigned i = OpNum; i < MCInst_getNumOperands(MI); i++) {
Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i),
true);
}
return;
}
// -2 because register List is always first operand of instruction
// and it is always followed by memory operand (base + offset).
for (unsigned i = OpNum, e = MCInst_getNumOperands(MI) - 2; i != e;
++i) {
Mips_set_detail_op_reg(MI, i, MCInst_getOpVal(MI, i), true);
}
}
static void Mips_set_detail_op_unsigned_address(MCInst *MI, unsigned OpNum)
{
uint64_t Target = MI->address + (uint64_t)MCInst_getOpVal(MI, OpNum);
Mips_set_detail_op_imm(MI, OpNum, Target);
}
void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args)
{
if (!detail_is_set(MI) || !map_fill_detail_ops(MI))
return;
unsigned OpNum = va_arg(args, unsigned);
switch (op_group) {
default:
printf("Operand group %d not handled!\n", op_group);
return;
case Mips_OP_GROUP_MemOperand:
// this is only used by nanoMips.
return Mips_set_detail_op_mem_nanomips(MI, OpNum);
case Mips_OP_GROUP_BranchOperand:
return Mips_set_detail_op_branch(MI, OpNum);
case Mips_OP_GROUP_JumpOperand:
return Mips_set_detail_op_jump(MI, OpNum);
case Mips_OP_GROUP_Operand:
return Mips_set_detail_op_operand(MI, OpNum);
case Mips_OP_GROUP_UImm_1_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 1, 0);
case Mips_OP_GROUP_UImm_2_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 0);
case Mips_OP_GROUP_UImm_3_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 3, 0);
case Mips_OP_GROUP_UImm_32_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 32, 0);
case Mips_OP_GROUP_UImm_16_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 16, 0);
case Mips_OP_GROUP_UImm_8_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 8, 0);
case Mips_OP_GROUP_UImm_5_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 0);
case Mips_OP_GROUP_UImm_6_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 0);
case Mips_OP_GROUP_UImm_4_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 4, 0);
case Mips_OP_GROUP_UImm_7_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 7, 0);
case Mips_OP_GROUP_UImm_10_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 10, 0);
case Mips_OP_GROUP_UImm_6_1:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 1);
case Mips_OP_GROUP_UImm_5_1:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 1);
case Mips_OP_GROUP_UImm_5_33:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 33);
case Mips_OP_GROUP_UImm_5_32:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 5, 32);
case Mips_OP_GROUP_UImm_6_2:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 6, 2);
case Mips_OP_GROUP_UImm_2_1:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 2, 1);
case Mips_OP_GROUP_UImm_0_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 0, 0);
case Mips_OP_GROUP_UImm_26_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 26, 0);
case Mips_OP_GROUP_UImm_12_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 12, 0);
case Mips_OP_GROUP_UImm_20_0:
return Mips_set_detail_op_unsigned_offset(MI, OpNum, 20, 0);
case Mips_OP_GROUP_RegisterList:
return Mips_set_detail_op_reglist(MI, OpNum, false);
case Mips_OP_GROUP_NanoMipsRegisterList:
return Mips_set_detail_op_reglist(MI, OpNum, true);
case Mips_OP_GROUP_PCRel:
/* fall-thru */
case Mips_OP_GROUP_Hi20PCRel:
return Mips_set_detail_op_unsigned_address(MI, OpNum);
case Mips_OP_GROUP_Hi20:
return Mips_set_detail_op_unsigned(MI, OpNum);
}
}
void Mips_set_mem_access(MCInst *MI, bool status)
{
if (!detail_is_set(MI))
return;
set_doing_mem(MI, status);
if (status) {
if (Mips_get_detail(MI)->op_count > 0 &&
Mips_get_detail_op(MI, -1)->type == MIPS_OP_MEM &&
Mips_get_detail_op(MI, -1)->mem.disp == 0) {
// Previous memory operand not done yet. Select it.
Mips_dec_op_count(MI);
return;
}
// Init a new one.
Mips_get_detail_op(MI, 0)->type = MIPS_OP_MEM;
Mips_get_detail_op(MI, 0)->mem.base = MIPS_REG_INVALID;
Mips_get_detail_op(MI, 0)->mem.disp = 0;
#ifndef CAPSTONE_DIET
uint8_t access =
map_get_op_access(MI, Mips_get_detail(MI)->op_count);
Mips_get_detail_op(MI, 0)->access = access;
#endif
} else {
// done, select the next operand slot
Mips_inc_op_count(MI);
}
}
#endif
external/capstone/arch/Mips/MipsMapping.h
Vendored
+62
View File
@@ -0,0 +1,62 @@
/* Capstone Disassembly Engine */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifndef CS_MIPS_MAPPING_H
#define CS_MIPS_MAPPING_H
#include "../../include/capstone/capstone.h"
#include "../../utils.h"
#include "../../Mapping.h"
typedef enum {
#include "MipsGenCSOpGroup.inc"
} mips_op_group;
void Mips_init_mri(MCRegisterInfo *MRI);
// return name of register in friendly string
const char *Mips_reg_name(csh handle, unsigned int reg);
void Mips_printer(MCInst *MI, SStream *O,
void * /* MCRegisterInfo* */ info);
// given internal insn id, return public instruction ID
void Mips_get_insn_id(cs_struct *h, cs_insn *insn, unsigned int id);
const char *Mips_insn_name(csh handle, unsigned int id);
const char *Mips_group_name(csh handle, unsigned int id);
bool Mips_getInstruction(csh handle, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
void Mips_reg_access(const cs_insn *insn, cs_regs regs_read,
uint8_t *regs_read_count, cs_regs regs_write,
uint8_t *regs_write_count);
// cs_detail related functions
void Mips_init_cs_detail(MCInst *MI);
void Mips_set_mem_access(MCInst *MI, bool status);
void Mips_add_cs_detail(MCInst *MI, mips_op_group op_group, va_list args);
static inline void add_cs_detail(MCInst *MI, mips_op_group op_group, ...)
{
if (!detail_is_set(MI))
return;
va_list args;
va_start(args, op_group);
Mips_add_cs_detail(MI, op_group, args);
va_end(args);
}
static inline void set_mem_access(MCInst *MI, bool status)
{
if (!detail_is_set(MI))
return;
Mips_set_mem_access(MI, status);
}
#endif // CS_MIPS_MAPPING_H
external/capstone/arch/Mips/MipsMappingInsn.inc
Vendored
+9315
View File
File diff suppressed because it is too large Load Diff
external/capstone/arch/Mips/MipsModule.c
Vendored
+52
View File
@@ -0,0 +1,52 @@
/* Capstone Disassembly Engine */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifdef CAPSTONE_HAS_MIPS
#include <capstone/capstone.h>
#include "MipsModule.h"
#include "../../MCRegisterInfo.h"
#include "../../cs_priv.h"
#include "MipsMapping.h"
cs_err Mips_global_init(cs_struct *ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
Mips_init_mri(mri);
ud->printer = Mips_printer;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->reg_name = Mips_reg_name;
ud->insn_id = Mips_get_insn_id;
ud->insn_name = Mips_insn_name;
ud->group_name = Mips_group_name;
ud->disasm = Mips_getInstruction;
ud->post_printer = NULL;
#ifndef CAPSTONE_DIET
ud->reg_access = Mips_reg_access;
#endif
return CS_ERR_OK;
}
cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value)
{
switch (type) {
case CS_OPT_MODE:
handle->mode = (cs_mode)value;
break;
case CS_OPT_SYNTAX:
handle->syntax |= (int)value;
break;
default:
break;
}
return CS_ERR_OK;
}
#endif
external/capstone/arch/Mips/MipsModule.h
Vendored
+12
View File
@@ -0,0 +1,12 @@
/* Capstone Disassembly Engine */
/* By Giovanni Dante Grazioli, deroad <wargio@libero.it>, 2024 */
#ifndef CS_MIPS_MODULE_H
#define CS_MIPS_MODULE_H
#include "../../utils.h"
cs_err Mips_global_init(cs_struct *ud);
cs_err Mips_option(cs_struct *handle, cs_opt_type type, size_t value);
#endif // CS_MIPS_MODULE_H