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Squashed 'external/ircolib/' changes from ce3cd726c..de6e324bd

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de6e324bd separate emu thread
10d3daf86 Roms List improvements
95d202f37 Let's make the rom list process on a separate thread so the emulator doesnt take ages to load.
fc306967f Wow the ROM Header was just completely busted. Game list view works now
bad1691ee fuck this shit
2b59e5f46 game list in progress
d26417b83 remappable inputs in progress
ac4af8106 input
e72abc240 update readme
430139dc9 Qt6 frontend
3080d4d45 Fix this small bug too
08cd13b85 Cop0 unused functions do not actually pose a threat (as per manual). They don't do anything, so shall we.
61bb4fb44 make idle loop detection a little more specific with where the load goes
b037de4c3 SAZDFsdff
12e81e73e need to figure out why n64-systemtest loops indefinitely at some address that appears to be valid (i think it's me not invalidating the cache properly)
204f0e13b idle skipping seems to work!
cb8bb634a sdkfjlasdf
58e5c89c1 Fix compilation issue on my machine (no idea)
24fb2898e attempting more serious idle skipping
214719577 Place rsp.Step inside cached interpreter. Gains about 3 more fps
bb97dcc23 mmmmm
920b77d38 wjkhasdfjhkasdf
430ccdab4 it's a start...
4f42a673a Cached interpreter plays Mario 64. Start looking into RSP as well
c9a030787 idle skipping works!
5fbda03ce new idea
366637aba Idle skipping... maybe?
609fa2fb0 Cache instructions implemented but broken lmao. Commented out for now
e140a6d12 - Stop using inheritance for CPU, instead use composition. - Introduce KAIZEN_JIT_ENABLED optional define instead of relying on __aarch64__ and the like. - More cache work
68e613057 prep cache impl
811b4d809 fix clang format
fda755f7d idk
d5024ebbf small MI refactor in preparation of (eventually) implementing the RDRAM interface properly
694b45341 Merge commit '206dcdedf195fb320913584180edb12c7731e396' as 'external/SDL'
206dcdedf Squashed 'external/SDL/' content from commit 4d17b99d0a
4d16e1cb4 need to update sdl
848b19920 Fix compilation error
db61b5299 Merge commit 'e94a94559f28e49678fbcf72199a5258137b0fe9' as 'external/imgui'
e94a94559 Squashed 'external/imgui/' content from commit 02e9b8cac
52edb3757 need to update imgui
c1a705e86 Emulate weird JALR behaviour
4b4c32f4b Fix exception for "unusable COP1" in 4 instructions i missed accidentally (again)
df5828142 Bug putting 0s in the log everywhere
f8b580048 Make isviewer a sink to file
8241e9735 Fix exception for "unusable COP1" in 4 instructions i missed accidentally
b29715f20 small changes
d9a620bc1 make use of my new small utility library
0d1aa938e Add 'external/ircolib/' from commit 'ce3cd726c8df8388d554abf8bb55d55020eb4450'
e64eb40b3 Fuck git

git-subtree-dir: external/ircolib
git-subtree-split: de6e324bde
This commit is contained in:
iris
2026-06-15 11:56:38 +02:00
parent ce3cd726c8
commit 00cc9309cb
4479 changed files with 2943227 additions and 7 deletions
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external/capstone/arch/RISCV/RISCVBaseInfo.h
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//===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains small standalone enum definitions for the RISCV target
// useful for the compiler back-end and the MC libraries.
//
//===----------------------------------------------------------------------===//
#ifndef CS_RISCVBASEINFO_H
#define CS_RISCVBASEINFO_H
#include "../../cs_priv.h"
//#include "RISCVMCTargetDesc.h"
// RISCVII - This namespace holds all of the target specific flags that
// instruction info tracks. All definitions must match RISCVInstrFormats.td.
enum {
IRISCVII_InstFormatPseudo = 0,
IRISCVII_InstFormatR = 1,
IRISCVII_InstFormatR4 = 2,
IRISCVII_InstFormatI = 3,
IRISCVII_InstFormatS = 4,
IRISCVII_InstFormatB = 5,
IRISCVII_InstFormatU = 6,
IRISCVII_InstFormatJ = 7,
IRISCVII_InstFormatCR = 8,
IRISCVII_InstFormatCI = 9,
IRISCVII_InstFormatCSS = 10,
IRISCVII_InstFormatCIW = 11,
IRISCVII_InstFormatCL = 12,
IRISCVII_InstFormatCS = 13,
IRISCVII_InstFormatCA = 14,
IRISCVII_InstFormatCB = 15,
IRISCVII_InstFormatCJ = 16,
IRISCVII_InstFormatOther = 17,
IRISCVII_InstFormatMask = 31
};
enum {
RISCVII_MO_None,
RISCVII_MO_LO,
RISCVII_MO_HI,
RISCVII_MO_PCREL_HI,
};
// Describes the predecessor/successor bits used in the FENCE instruction.
enum FenceField {
RISCVFenceField_I = 8,
RISCVFenceField_O = 4,
RISCVFenceField_R = 2,
RISCVFenceField_W = 1
};
// Describes the supported floating point rounding mode encodings.
enum RoundingMode {
RISCVFPRndMode_RNE = 0,
RISCVFPRndMode_RTZ = 1,
RISCVFPRndMode_RDN = 2,
RISCVFPRndMode_RUP = 3,
RISCVFPRndMode_RMM = 4,
RISCVFPRndMode_DYN = 7,
RISCVFPRndMode_Invalid
};
inline static const char *roundingModeToString(enum RoundingMode RndMode)
{
switch (RndMode) {
default:
CS_ASSERT(0 && "Unknown floating point rounding mode");
case RISCVFPRndMode_RNE:
return "rne";
case RISCVFPRndMode_RTZ:
return "rtz";
case RISCVFPRndMode_RDN:
return "rdn";
case RISCVFPRndMode_RUP:
return "rup";
case RISCVFPRndMode_RMM:
return "rmm";
case RISCVFPRndMode_DYN:
return "dyn";
}
}
inline static bool RISCVFPRndMode_isValidRoundingMode(unsigned Mode)
{
switch (Mode) {
default:
return false;
case RISCVFPRndMode_RNE:
case RISCVFPRndMode_RTZ:
case RISCVFPRndMode_RDN:
case RISCVFPRndMode_RUP:
case RISCVFPRndMode_RMM:
case RISCVFPRndMode_DYN:
return true;
}
}
#endif
external/capstone/arch/RISCV/RISCVDisassembler.c
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//===-- RISCVDisassembler.cpp - Disassembler for RISCV --------------------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
/* Capstone Disassembly Engine */
/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
#ifdef CAPSTONE_HAS_RISCV
#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <string.h>
#include "../../cs_priv.h"
#include "../../utils.h"
#include "../../MCInst.h"
#include "../../MCInstrDesc.h"
#include "../../MCFixedLenDisassembler.h"
#include "../../MCRegisterInfo.h"
#include "../../MCDisassembler.h"
#include "../../MathExtras.h"
#include "../../Mapping.h"
#include "RISCVBaseInfo.h"
#include "RISCVDisassembler.h"
/* Need the feature infos define in
RISCVGenSubtargetInfo.inc. */
#define GET_SUBTARGETINFO_ENUM
#include "RISCVGenSubtargetInfo.inc"
/* When we specify the RISCV64 mode, It means It is RV64IMAFD.
Similar, RISCV32 means RV32IMAFD.
*/
static uint64_t getFeatureBits(int mode)
{
uint64_t ret = RISCV_FeatureStdExtM | RISCV_FeatureStdExtA |
RISCV_FeatureStdExtF | RISCV_FeatureStdExtD ;
if (mode & CS_MODE_RISCV64)
ret |= RISCV_Feature64Bit;
if (mode & CS_MODE_RISCVC)
ret |= RISCV_FeatureStdExtC;
return ret;
}
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "RISCVGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "RISCVGenInstrInfo.inc"
static const unsigned GPRDecoderTable[] = {
RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3,
RISCV_X4, RISCV_X5, RISCV_X6, RISCV_X7,
RISCV_X8, RISCV_X9, RISCV_X10, RISCV_X11,
RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15,
RISCV_X16, RISCV_X17, RISCV_X18, RISCV_X19,
RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23,
RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27,
RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31
};
static DecodeStatus DecodeGPRRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
unsigned Reg = 0;
if (RegNo >= ARR_SIZE(GPRDecoderTable))
return MCDisassembler_Fail;
// We must define our own mapping from RegNo to register identifier.
// Accessing index RegNo in the register class will work in the case that
// registers were added in ascending order, but not in general.
Reg = GPRDecoderTable[RegNo];
//Inst.addOperand(MCOperand::createReg(Reg));
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
static const unsigned FPR32DecoderTable[] = {
RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32,
RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32,
RISCV_F8_32, RISCV_F9_32, RISCV_F10_32, RISCV_F11_32,
RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32,
RISCV_F16_32, RISCV_F17_32, RISCV_F18_32, RISCV_F19_32,
RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32,
RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32,
RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32
};
static DecodeStatus DecodeFPR32RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
unsigned Reg = 0;
if (RegNo >= ARR_SIZE(FPR32DecoderTable))
return MCDisassembler_Fail;
// We must define our own mapping from RegNo to register identifier.
// Accessing index RegNo in the register class will work in the case that
// registers were added in ascending order, but not in general.
Reg = FPR32DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
static DecodeStatus DecodeFPR32CRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
unsigned Reg = 0;
if (RegNo > 8)
return MCDisassembler_Fail;
Reg = FPR32DecoderTable[RegNo + 8];
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
static const unsigned FPR64DecoderTable[] = {
RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64,
RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64,
RISCV_F8_64, RISCV_F9_64, RISCV_F10_64, RISCV_F11_64,
RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64,
RISCV_F16_64, RISCV_F17_64, RISCV_F18_64, RISCV_F19_64,
RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64,
RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64,
RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64
};
static DecodeStatus DecodeFPR64RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address, const void *Decoder)
{
unsigned Reg = 0;
if (RegNo >= ARR_SIZE(FPR64DecoderTable))
return MCDisassembler_Fail;
// We must define our own mapping from RegNo to register identifier.
// Accessing index RegNo in the register class will work in the case that
// registers were added in ascending order, but not in general.
Reg = FPR64DecoderTable[RegNo];
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
static DecodeStatus DecodeFPR64CRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
unsigned Reg = 0;
if (RegNo > 8)
return MCDisassembler_Fail;
Reg = FPR64DecoderTable[RegNo + 8];
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo == 0)
return MCDisassembler_Fail;
return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeGPRNoX0X2RegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
if (RegNo == 2)
return MCDisassembler_Fail;
return DecodeGPRNoX0RegisterClass(Inst, RegNo, Address, Decoder);
}
static DecodeStatus DecodeGPRCRegisterClass(MCInst *Inst, uint64_t RegNo,
uint64_t Address,
const void *Decoder)
{
unsigned Reg = 0;
if (RegNo > 8)
return MCDisassembler_Fail;
Reg = GPRDecoderTable[RegNo + 8];
MCOperand_CreateReg0(Inst, Reg);
return MCDisassembler_Success;
}
// Add implied SP operand for instructions *SP compressed instructions. The SP
// operand isn't explicitly encoded in the instruction.
static void addImplySP(MCInst *Inst, int64_t Address, const void *Decoder)
{
if (MCInst_getOpcode(Inst) == RISCV_C_LWSP ||
MCInst_getOpcode(Inst) == RISCV_C_SWSP ||
MCInst_getOpcode(Inst) == RISCV_C_LDSP ||
MCInst_getOpcode(Inst) == RISCV_C_SDSP ||
MCInst_getOpcode(Inst) == RISCV_C_FLWSP ||
MCInst_getOpcode(Inst) == RISCV_C_FSWSP ||
MCInst_getOpcode(Inst) == RISCV_C_FLDSP ||
MCInst_getOpcode(Inst) == RISCV_C_FSDSP ||
MCInst_getOpcode(Inst) == RISCV_C_ADDI4SPN) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
}
if (MCInst_getOpcode(Inst) == RISCV_C_ADDI16SP) {
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
}
}
static DecodeStatus decodeUImmOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder,
unsigned N)
{
//CS_ASSERT(isUInt<N>(Imm) && "Invalid immediate");
addImplySP(Inst, Address, Decoder);
//Inst.addOperand(MCOperand::createImm(Imm));
MCOperand_CreateImm0(Inst, Imm);
return MCDisassembler_Success;
}
static DecodeStatus decodeUImmNonZeroOperand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder,
unsigned N)
{
if (Imm == 0)
return MCDisassembler_Fail;
return decodeUImmOperand(Inst, Imm, Address, Decoder, N);
}
static DecodeStatus decodeSImmOperand(MCInst *Inst, uint64_t Imm,
int64_t Address, const void *Decoder,
unsigned N)
{
//CS_ASSERT(isUInt<N>(Imm) && "Invalid immediate");
addImplySP(Inst, Address, Decoder);
// Sign-extend the number in the bottom N bits of Imm
//Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
MCOperand_CreateImm0(Inst, SignExtend64(Imm, N));
return MCDisassembler_Success;
}
static DecodeStatus decodeSImmNonZeroOperand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder,
unsigned N)
{
if (Imm == 0)
return MCDisassembler_Fail;
return decodeSImmOperand(Inst, Imm, Address, Decoder, N);
}
static DecodeStatus decodeSImmOperandAndLsl1(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder,
unsigned N)
{
//CS_ASSERT(isUInt<N>(Imm) && "Invalid immediate");
// Sign-extend the number in the bottom N bits of Imm after accounting for
// the fact that the N bit immediate is stored in N-1 bits (the LSB is
// always zero)
//Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
MCOperand_CreateImm0(Inst, SignExtend64(Imm << 1, N));
return MCDisassembler_Success;
}
static DecodeStatus decodeCLUIImmOperand(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
//CS_ASSERT(isUInt<6>(Imm) && "Invalid immediate");
if (Imm > 31) {
Imm = (SignExtend64(Imm, 6) & 0xfffff);
}
//Inst.addOperand(MCOperand::createImm(Imm));
MCOperand_CreateImm0(Inst, Imm);
return MCDisassembler_Success;
}
static DecodeStatus decodeFRMArg(MCInst *Inst, uint64_t Imm,
int64_t Address,
const void *Decoder)
{
//CS_ASSERT(isUInt<3>(Imm) && "Invalid immediate");
if (!RISCVFPRndMode_isValidRoundingMode(Imm))
return MCDisassembler_Fail;
//Inst.addOperand(MCOperand::createImm(Imm));
MCOperand_CreateImm0(Inst, Imm);
return MCDisassembler_Success;
}
#include "RISCVGenDisassemblerTables.inc"
static void init_MI_insn_detail(MCInst *MI)
{
if (MI->flat_insn->detail) {
memset(MI->flat_insn->detail, 0, sizeof(cs_detail));
}
return;
}
// mark the load/store instructions through the opcode.
static void markLSInsn(MCInst *MI, uint32_t in)
{
/*
I ld 0000011 = 0x03
st 0100011 = 0x23
F/D ld 0000111 = 0x07
st 0100111 = 0x27
st 0101111 = 0x2f
*/
#define MASK_LS_INSN 0x0000007f
uint32_t opcode = in & MASK_LS_INSN;
if (0 == (opcode ^ 0x03) || 0 == (opcode ^ 0x07) ||
0 == (opcode ^ 0x23) || 0 == (opcode ^ 0x27) ||
0 == (opcode ^ 0x2f))
MI->flat_insn->detail->riscv.need_effective_addr = true;
#undef MASK_LS_INSN
return;
}
static void markCLSInsn(MCInst *MI, uint32_t in)
{
// Unfortunately there is no obvious pattern in terms of RISC-V C instructions
// Thus, we compare the instruction IDs to see if it is a load/store instruction
unsigned id = MCInst_getOpcode(MI);
if (id == RISCV_C_FLD || id == RISCV_C_LW ||
id == RISCV_C_FLW || id == RISCV_C_LD ||
id == RISCV_C_FSD || id == RISCV_C_SW ||
id == RISCV_C_FSW || id == RISCV_C_SD ||
id == RISCV_C_FLDSP || id == RISCV_C_LWSP ||
id == RISCV_C_FLWSP || id == RISCV_C_LDSP ||
id == RISCV_C_FSDSP || id == RISCV_C_SWSP ||
id == RISCV_C_FSWSP || id == RISCV_C_SDSP) {
RISCV_get_detail(MI)->need_effective_addr = true;
}
return;
}
static DecodeStatus RISCVDisassembler_getInstruction(int mode, MCInst *MI,
const uint8_t *code, size_t code_len,
uint16_t *Size, uint64_t Address,
MCRegisterInfo *MRI)
{
// TODO: This will need modification when supporting instruction set
// extensions with instructions > 32-bits (up to 176 bits wide).
uint32_t Inst = 0;
DecodeStatus Result;
// It's a 32 bit instruction if bit 0 and 1 are 1.
if ((code[0] & 0x3) == 0x3) {
if (code_len < 4) {
*Size = 0;
return MCDisassembler_Fail;
}
*Size = 4;
// Get the four bytes of the instruction.
//Encoded as little endian 32 bits.
Inst = code[0] | (code[1] << 8) | (code[2] << 16) | ((uint32_t)code[3] << 24);
init_MI_insn_detail(MI);
// Now we need mark what instruction need fix effective address output.
if (MI->csh->detail_opt)
markLSInsn(MI, Inst);
Result = decodeInstruction(DecoderTable32, MI, Inst, Address, MRI, mode);
} else {
if (code_len < 2) {
*Size = 0;
return MCDisassembler_Fail;
}
// If not b4bit.
if (! (getFeatureBits(mode) & ((uint64_t)RISCV_Feature64Bit))) {
// Trying RISCV32Only_16 table (16-bit Instruction)
Inst = code[0] | (code[1] << 8);
init_MI_insn_detail(MI);
Result = decodeInstruction(DecoderTableRISCV32Only_16, MI, Inst, Address,
MRI, mode);
if (Result != MCDisassembler_Fail) {
*Size = 2;
return Result;
}
}
// Trying RISCV_C table (16-bit Instruction)
Inst = code[0] | (code[1] << 8);
init_MI_insn_detail(MI);
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTable16, MI, Inst, Address, MRI, mode);
// Now we need mark what instruction need fix effective address output.
// Note that we mark it AFTER the instruction is decoded
// This is because there is no obvious pattern in terms of RISC-V C instructions
// So we compare the instruction IDs one by one
if (detail_is_set(MI))
markCLSInsn(MI, Inst);
*Size = 2;
}
return Result;
}
bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info)
{
cs_struct *handle = (cs_struct *)(uintptr_t)ud;
DecodeStatus Result =
RISCVDisassembler_getInstruction(handle->mode, instr,
code, code_len,
size, address,
(MCRegisterInfo *)info);
if (Result == MCDisassembler_SoftFail) {
MCInst_setSoftFail(instr);
}
return Result != MCDisassembler_Fail;
}
void RISCV_init(MCRegisterInfo * MRI)
{
/*
InitMCRegisterInfo(RISCVRegDesc, 97, RA, PC,
RISCVMCRegisterClasses, 11,
RISCVRegUnitRoots,
64,
RISCVRegDiffLists,
RISCVLaneMaskLists,
RISCVRegStrings,
RISCVRegClassStrings,
RISCVSubRegIdxLists,
2,
RISCVSubRegIdxRanges,
RISCVRegEncodingTable);
*/
MCRegisterInfo_InitMCRegisterInfo(MRI, RISCVRegDesc, 97, 0, 0,
RISCVMCRegisterClasses, 11,
0,
0,
RISCVRegDiffLists,
0,
RISCVSubRegIdxLists,
2,
0);
}
#endif
external/capstone/arch/RISCV/RISCVDisassembler.h
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/* Capstone Disassembly Engine */
/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
#ifndef CS_RISCVDISASSEMBLER_H
#define CS_RISCVDISASSEMBLER_H
#include "../../include/capstone/capstone.h"
#include "../../MCRegisterInfo.h"
#include "../../MCInst.h"
void RISCV_init(MCRegisterInfo *MRI);
bool RISCV_getInstruction(csh ud, const uint8_t *code, size_t code_len,
MCInst *instr, uint16_t *size, uint64_t address,
void *info);
#endif
external/capstone/arch/RISCV/RISCVGenAsmWriter.inc
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external/capstone/arch/RISCV/RISCVGenDisassemblerTables.inc
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external/capstone/arch/RISCV/RISCVGenInsnNameMaps.inc
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@@ -0,0 +1,275 @@
// This is auto-gen data for Capstone engine (www.capstone-engine.org)
// By Nguyen Anh Quynh <aquynh@gmail.com>
{ RISCV_INS_ADD, "add" },
{ RISCV_INS_ADDI, "addi" },
{ RISCV_INS_ADDIW, "addiw" },
{ RISCV_INS_ADDW, "addw" },
{ RISCV_INS_AMOADD_D, "amoadd.d" },
{ RISCV_INS_AMOADD_D_AQ, "amoadd.d.aq" },
{ RISCV_INS_AMOADD_D_AQ_RL, "amoadd.d.aqrl" },
{ RISCV_INS_AMOADD_D_RL, "amoadd.d.rl" },
{ RISCV_INS_AMOADD_W, "amoadd.w" },
{ RISCV_INS_AMOADD_W_AQ, "amoadd.w.aq" },
{ RISCV_INS_AMOADD_W_AQ_RL, "amoadd.w.aqrl" },
{ RISCV_INS_AMOADD_W_RL, "amoadd.w.rl" },
{ RISCV_INS_AMOAND_D, "amoand.d" },
{ RISCV_INS_AMOAND_D_AQ, "amoand.d.aq" },
{ RISCV_INS_AMOAND_D_AQ_RL, "amoand.d.aqrl" },
{ RISCV_INS_AMOAND_D_RL, "amoand.d.rl" },
{ RISCV_INS_AMOAND_W, "amoand.w" },
{ RISCV_INS_AMOAND_W_AQ, "amoand.w.aq" },
{ RISCV_INS_AMOAND_W_AQ_RL, "amoand.w.aqrl" },
{ RISCV_INS_AMOAND_W_RL, "amoand.w.rl" },
{ RISCV_INS_AMOMAXU_D, "amomaxu.d" },
{ RISCV_INS_AMOMAXU_D_AQ, "amomaxu.d.aq" },
{ RISCV_INS_AMOMAXU_D_AQ_RL, "amomaxu.d.aqrl" },
{ RISCV_INS_AMOMAXU_D_RL, "amomaxu.d.rl" },
{ RISCV_INS_AMOMAXU_W, "amomaxu.w" },
{ RISCV_INS_AMOMAXU_W_AQ, "amomaxu.w.aq" },
{ RISCV_INS_AMOMAXU_W_AQ_RL, "amomaxu.w.aqrl" },
{ RISCV_INS_AMOMAXU_W_RL, "amomaxu.w.rl" },
{ RISCV_INS_AMOMAX_D, "amomax.d" },
{ RISCV_INS_AMOMAX_D_AQ, "amomax.d.aq" },
{ RISCV_INS_AMOMAX_D_AQ_RL, "amomax.d.aqrl" },
{ RISCV_INS_AMOMAX_D_RL, "amomax.d.rl" },
{ RISCV_INS_AMOMAX_W, "amomax.w" },
{ RISCV_INS_AMOMAX_W_AQ, "amomax.w.aq" },
{ RISCV_INS_AMOMAX_W_AQ_RL, "amomax.w.aqrl" },
{ RISCV_INS_AMOMAX_W_RL, "amomax.w.rl" },
{ RISCV_INS_AMOMINU_D, "amominu.d" },
{ RISCV_INS_AMOMINU_D_AQ, "amominu.d.aq" },
{ RISCV_INS_AMOMINU_D_AQ_RL, "amominu.d.aqrl" },
{ RISCV_INS_AMOMINU_D_RL, "amominu.d.rl" },
{ RISCV_INS_AMOMINU_W, "amominu.w" },
{ RISCV_INS_AMOMINU_W_AQ, "amominu.w.aq" },
{ RISCV_INS_AMOMINU_W_AQ_RL, "amominu.w.aqrl" },
{ RISCV_INS_AMOMINU_W_RL, "amominu.w.rl" },
{ RISCV_INS_AMOMIN_D, "amomin.d" },
{ RISCV_INS_AMOMIN_D_AQ, "amomin.d.aq" },
{ RISCV_INS_AMOMIN_D_AQ_RL, "amomin.d.aqrl" },
{ RISCV_INS_AMOMIN_D_RL, "amomin.d.rl" },
{ RISCV_INS_AMOMIN_W, "amomin.w" },
{ RISCV_INS_AMOMIN_W_AQ, "amomin.w.aq" },
{ RISCV_INS_AMOMIN_W_AQ_RL, "amomin.w.aqrl" },
{ RISCV_INS_AMOMIN_W_RL, "amomin.w.rl" },
{ RISCV_INS_AMOOR_D, "amoor.d" },
{ RISCV_INS_AMOOR_D_AQ, "amoor.d.aq" },
{ RISCV_INS_AMOOR_D_AQ_RL, "amoor.d.aqrl" },
{ RISCV_INS_AMOOR_D_RL, "amoor.d.rl" },
{ RISCV_INS_AMOOR_W, "amoor.w" },
{ RISCV_INS_AMOOR_W_AQ, "amoor.w.aq" },
{ RISCV_INS_AMOOR_W_AQ_RL, "amoor.w.aqrl" },
{ RISCV_INS_AMOOR_W_RL, "amoor.w.rl" },
{ RISCV_INS_AMOSWAP_D, "amoswap.d" },
{ RISCV_INS_AMOSWAP_D_AQ, "amoswap.d.aq" },
{ RISCV_INS_AMOSWAP_D_AQ_RL, "amoswap.d.aqrl" },
{ RISCV_INS_AMOSWAP_D_RL, "amoswap.d.rl" },
{ RISCV_INS_AMOSWAP_W, "amoswap.w" },
{ RISCV_INS_AMOSWAP_W_AQ, "amoswap.w.aq" },
{ RISCV_INS_AMOSWAP_W_AQ_RL, "amoswap.w.aqrl" },
{ RISCV_INS_AMOSWAP_W_RL, "amoswap.w.rl" },
{ RISCV_INS_AMOXOR_D, "amoxor.d" },
{ RISCV_INS_AMOXOR_D_AQ, "amoxor.d.aq" },
{ RISCV_INS_AMOXOR_D_AQ_RL, "amoxor.d.aqrl" },
{ RISCV_INS_AMOXOR_D_RL, "amoxor.d.rl" },
{ RISCV_INS_AMOXOR_W, "amoxor.w" },
{ RISCV_INS_AMOXOR_W_AQ, "amoxor.w.aq" },
{ RISCV_INS_AMOXOR_W_AQ_RL, "amoxor.w.aqrl" },
{ RISCV_INS_AMOXOR_W_RL, "amoxor.w.rl" },
{ RISCV_INS_AND, "and" },
{ RISCV_INS_ANDI, "andi" },
{ RISCV_INS_AUIPC, "auipc" },
{ RISCV_INS_BEQ, "beq" },
{ RISCV_INS_BGE, "bge" },
{ RISCV_INS_BGEU, "bgeu" },
{ RISCV_INS_BLT, "blt" },
{ RISCV_INS_BLTU, "bltu" },
{ RISCV_INS_BNE, "bne" },
{ RISCV_INS_CSRRC, "csrrc" },
{ RISCV_INS_CSRRCI, "csrrci" },
{ RISCV_INS_CSRRS, "csrrs" },
{ RISCV_INS_CSRRSI, "csrrsi" },
{ RISCV_INS_CSRRW, "csrrw" },
{ RISCV_INS_CSRRWI, "csrrwi" },
{ RISCV_INS_C_ADD, "c.add" },
{ RISCV_INS_C_ADDI, "c.addi" },
{ RISCV_INS_C_ADDI16SP, "c.addi16sp" },
{ RISCV_INS_C_ADDI4SPN, "c.addi4spn" },
{ RISCV_INS_C_ADDIW, "c.addiw" },
{ RISCV_INS_C_ADDW, "c.addw" },
{ RISCV_INS_C_AND, "c.and" },
{ RISCV_INS_C_ANDI, "c.andi" },
{ RISCV_INS_C_BEQZ, "c.beqz" },
{ RISCV_INS_C_BNEZ, "c.bnez" },
{ RISCV_INS_C_EBREAK, "c.ebreak" },
{ RISCV_INS_C_FLD, "c.fld" },
{ RISCV_INS_C_FLDSP, "c.fldsp" },
{ RISCV_INS_C_FLW, "c.flw" },
{ RISCV_INS_C_FLWSP, "c.flwsp" },
{ RISCV_INS_C_FSD, "c.fsd" },
{ RISCV_INS_C_FSDSP, "c.fsdsp" },
{ RISCV_INS_C_FSW, "c.fsw" },
{ RISCV_INS_C_FSWSP, "c.fswsp" },
{ RISCV_INS_C_J, "c.j" },
{ RISCV_INS_C_JAL, "c.jal" },
{ RISCV_INS_C_JALR, "c.jalr" },
{ RISCV_INS_C_JR, "c.jr" },
{ RISCV_INS_C_LD, "c.ld" },
{ RISCV_INS_C_LDSP, "c.ldsp" },
{ RISCV_INS_C_LI, "c.li" },
{ RISCV_INS_C_LUI, "c.lui" },
{ RISCV_INS_C_LW, "c.lw" },
{ RISCV_INS_C_LWSP, "c.lwsp" },
{ RISCV_INS_C_MV, "c.mv" },
{ RISCV_INS_C_NOP, "c.nop" },
{ RISCV_INS_C_OR, "c.or" },
{ RISCV_INS_C_SD, "c.sd" },
{ RISCV_INS_C_SDSP, "c.sdsp" },
{ RISCV_INS_C_SLLI, "c.slli" },
{ RISCV_INS_C_SRAI, "c.srai" },
{ RISCV_INS_C_SRLI, "c.srli" },
{ RISCV_INS_C_SUB, "c.sub" },
{ RISCV_INS_C_SUBW, "c.subw" },
{ RISCV_INS_C_SW, "c.sw" },
{ RISCV_INS_C_SWSP, "c.swsp" },
{ RISCV_INS_C_UNIMP, "c.unimp" },
{ RISCV_INS_C_XOR, "c.xor" },
{ RISCV_INS_DIV, "div" },
{ RISCV_INS_DIVU, "divu" },
{ RISCV_INS_DIVUW, "divuw" },
{ RISCV_INS_DIVW, "divw" },
{ RISCV_INS_EBREAK, "ebreak" },
{ RISCV_INS_ECALL, "ecall" },
{ RISCV_INS_FADD_D, "fadd.d" },
{ RISCV_INS_FADD_S, "fadd.s" },
{ RISCV_INS_FCLASS_D, "fclass.d" },
{ RISCV_INS_FCLASS_S, "fclass.s" },
{ RISCV_INS_FCVT_D_L, "fcvt.d.l" },
{ RISCV_INS_FCVT_D_LU, "fcvt.d.lu" },
{ RISCV_INS_FCVT_D_S, "fcvt.d.s" },
{ RISCV_INS_FCVT_D_W, "fcvt.d.w" },
{ RISCV_INS_FCVT_D_WU, "fcvt.d.wu" },
{ RISCV_INS_FCVT_LU_D, "fcvt.lu.d" },
{ RISCV_INS_FCVT_LU_S, "fcvt.lu.s" },
{ RISCV_INS_FCVT_L_D, "fcvt.l.d" },
{ RISCV_INS_FCVT_L_S, "fcvt.l.s" },
{ RISCV_INS_FCVT_S_D, "fcvt.s.d" },
{ RISCV_INS_FCVT_S_L, "fcvt.s.l" },
{ RISCV_INS_FCVT_S_LU, "fcvt.s.lu" },
{ RISCV_INS_FCVT_S_W, "fcvt.s.w" },
{ RISCV_INS_FCVT_S_WU, "fcvt.s.wu" },
{ RISCV_INS_FCVT_WU_D, "fcvt.wu.d" },
{ RISCV_INS_FCVT_WU_S, "fcvt.wu.s" },
{ RISCV_INS_FCVT_W_D, "fcvt.w.d" },
{ RISCV_INS_FCVT_W_S, "fcvt.w.s" },
{ RISCV_INS_FDIV_D, "fdiv.d" },
{ RISCV_INS_FDIV_S, "fdiv.s" },
{ RISCV_INS_FENCE, "fence" },
{ RISCV_INS_FENCE_I, "fence.i" },
{ RISCV_INS_FENCE_TSO, "fence.tso" },
{ RISCV_INS_FEQ_D, "feq.d" },
{ RISCV_INS_FEQ_S, "feq.s" },
{ RISCV_INS_FLD, "fld" },
{ RISCV_INS_FLE_D, "fle.d" },
{ RISCV_INS_FLE_S, "fle.s" },
{ RISCV_INS_FLT_D, "flt.d" },
{ RISCV_INS_FLT_S, "flt.s" },
{ RISCV_INS_FLW, "flw" },
{ RISCV_INS_FMADD_D, "fmadd.d" },
{ RISCV_INS_FMADD_S, "fmadd.s" },
{ RISCV_INS_FMAX_D, "fmax.d" },
{ RISCV_INS_FMAX_S, "fmax.s" },
{ RISCV_INS_FMIN_D, "fmin.d" },
{ RISCV_INS_FMIN_S, "fmin.s" },
{ RISCV_INS_FMSUB_D, "fmsub.d" },
{ RISCV_INS_FMSUB_S, "fmsub.s" },
{ RISCV_INS_FMUL_D, "fmul.d" },
{ RISCV_INS_FMUL_S, "fmul.s" },
{ RISCV_INS_FMV_D_X, "fmv.d.x" },
{ RISCV_INS_FMV_W_X, "fmv.w.x" },
{ RISCV_INS_FMV_X_D, "fmv.x.d" },
{ RISCV_INS_FMV_X_W, "fmv.x.w" },
{ RISCV_INS_FNMADD_D, "fnmadd.d" },
{ RISCV_INS_FNMADD_S, "fnmadd.s" },
{ RISCV_INS_FNMSUB_D, "fnmsub.d" },
{ RISCV_INS_FNMSUB_S, "fnmsub.s" },
{ RISCV_INS_FSD, "fsd" },
{ RISCV_INS_FSGNJN_D, "fsgnjn.d" },
{ RISCV_INS_FSGNJN_S, "fsgnjn.s" },
{ RISCV_INS_FSGNJX_D, "fsgnjx.d" },
{ RISCV_INS_FSGNJX_S, "fsgnjx.s" },
{ RISCV_INS_FSGNJ_D, "fsgnj.d" },
{ RISCV_INS_FSGNJ_S, "fsgnj.s" },
{ RISCV_INS_FSQRT_D, "fsqrt.d" },
{ RISCV_INS_FSQRT_S, "fsqrt.s" },
{ RISCV_INS_FSUB_D, "fsub.d" },
{ RISCV_INS_FSUB_S, "fsub.s" },
{ RISCV_INS_FSW, "fsw" },
{ RISCV_INS_JAL, "jal" },
{ RISCV_INS_JALR, "jalr" },
{ RISCV_INS_LB, "lb" },
{ RISCV_INS_LBU, "lbu" },
{ RISCV_INS_LD, "ld" },
{ RISCV_INS_LH, "lh" },
{ RISCV_INS_LHU, "lhu" },
{ RISCV_INS_LR_D, "lr.d" },
{ RISCV_INS_LR_D_AQ, "lr.d.aq" },
{ RISCV_INS_LR_D_AQ_RL, "lr.d.aqrl" },
{ RISCV_INS_LR_D_RL, "lr.d.rl" },
{ RISCV_INS_LR_W, "lr.w" },
{ RISCV_INS_LR_W_AQ, "lr.w.aq" },
{ RISCV_INS_LR_W_AQ_RL, "lr.w.aqrl" },
{ RISCV_INS_LR_W_RL, "lr.w.rl" },
{ RISCV_INS_LUI, "lui" },
{ RISCV_INS_LW, "lw" },
{ RISCV_INS_LWU, "lwu" },
{ RISCV_INS_MRET, "mret" },
{ RISCV_INS_MUL, "mul" },
{ RISCV_INS_MULH, "mulh" },
{ RISCV_INS_MULHSU, "mulhsu" },
{ RISCV_INS_MULHU, "mulhu" },
{ RISCV_INS_MULW, "mulw" },
{ RISCV_INS_OR, "or" },
{ RISCV_INS_ORI, "ori" },
{ RISCV_INS_REM, "rem" },
{ RISCV_INS_REMU, "remu" },
{ RISCV_INS_REMUW, "remuw" },
{ RISCV_INS_REMW, "remw" },
{ RISCV_INS_SB, "sb" },
{ RISCV_INS_SC_D, "sc.d" },
{ RISCV_INS_SC_D_AQ, "sc.d.aq" },
{ RISCV_INS_SC_D_AQ_RL, "sc.d.aqrl" },
{ RISCV_INS_SC_D_RL, "sc.d.rl" },
{ RISCV_INS_SC_W, "sc.w" },
{ RISCV_INS_SC_W_AQ, "sc.w.aq" },
{ RISCV_INS_SC_W_AQ_RL, "sc.w.aqrl" },
{ RISCV_INS_SC_W_RL, "sc.w.rl" },
{ RISCV_INS_SD, "sd" },
{ RISCV_INS_SFENCE_VMA, "sfence.vma" },
{ RISCV_INS_SH, "sh" },
{ RISCV_INS_SLL, "sll" },
{ RISCV_INS_SLLI, "slli" },
{ RISCV_INS_SLLIW, "slliw" },
{ RISCV_INS_SLLW, "sllw" },
{ RISCV_INS_SLT, "slt" },
{ RISCV_INS_SLTI, "slti" },
{ RISCV_INS_SLTIU, "sltiu" },
{ RISCV_INS_SLTU, "sltu" },
{ RISCV_INS_SRA, "sra" },
{ RISCV_INS_SRAI, "srai" },
{ RISCV_INS_SRAIW, "sraiw" },
{ RISCV_INS_SRAW, "sraw" },
{ RISCV_INS_SRET, "sret" },
{ RISCV_INS_SRL, "srl" },
{ RISCV_INS_SRLI, "srli" },
{ RISCV_INS_SRLIW, "srliw" },
{ RISCV_INS_SRLW, "srlw" },
{ RISCV_INS_SUB, "sub" },
{ RISCV_INS_SUBW, "subw" },
{ RISCV_INS_SW, "sw" },
{ RISCV_INS_UNIMP, "unimp" },
{ RISCV_INS_URET, "uret" },
{ RISCV_INS_WFI, "wfi" },
{ RISCV_INS_XOR, "xor" },
{ RISCV_INS_XORI, "xori" },
external/capstone/arch/RISCV/RISCVGenInstrInfo.inc
Vendored
+470
View File
@@ -0,0 +1,470 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Instruction Enum Values and Descriptors *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef GET_INSTRINFO_ENUM
#undef GET_INSTRINFO_ENUM
enum {
RISCV_PHI = 0,
RISCV_INLINEASM = 1,
RISCV_INLINEASM_BR = 2,
RISCV_CFI_INSTRUCTION = 3,
RISCV_EH_LABEL = 4,
RISCV_GC_LABEL = 5,
RISCV_ANNOTATION_LABEL = 6,
RISCV_KILL = 7,
RISCV_EXTRACT_SUBREG = 8,
RISCV_INSERT_SUBREG = 9,
RISCV_IMPLICIT_DEF = 10,
RISCV_SUBREG_TO_REG = 11,
RISCV_COPY_TO_REGCLASS = 12,
RISCV_DBG_VALUE = 13,
RISCV_DBG_LABEL = 14,
RISCV_REG_SEQUENCE = 15,
RISCV_COPY = 16,
RISCV_BUNDLE = 17,
RISCV_LIFETIME_START = 18,
RISCV_LIFETIME_END = 19,
RISCV_STACKMAP = 20,
RISCV_FENTRY_CALL = 21,
RISCV_PATCHPOINT = 22,
RISCV_LOAD_STACK_GUARD = 23,
RISCV_STATEPOINT = 24,
RISCV_LOCAL_ESCAPE = 25,
RISCV_FAULTING_OP = 26,
RISCV_PATCHABLE_OP = 27,
RISCV_PATCHABLE_FUNCTION_ENTER = 28,
RISCV_PATCHABLE_RET = 29,
RISCV_PATCHABLE_FUNCTION_EXIT = 30,
RISCV_PATCHABLE_TAIL_CALL = 31,
RISCV_PATCHABLE_EVENT_CALL = 32,
RISCV_PATCHABLE_TYPED_EVENT_CALL = 33,
RISCV_ICALL_BRANCH_FUNNEL = 34,
RISCV_G_ADD = 35,
RISCV_G_SUB = 36,
RISCV_G_MUL = 37,
RISCV_G_SDIV = 38,
RISCV_G_UDIV = 39,
RISCV_G_SREM = 40,
RISCV_G_UREM = 41,
RISCV_G_AND = 42,
RISCV_G_OR = 43,
RISCV_G_XOR = 44,
RISCV_G_IMPLICIT_DEF = 45,
RISCV_G_PHI = 46,
RISCV_G_FRAME_INDEX = 47,
RISCV_G_GLOBAL_VALUE = 48,
RISCV_G_EXTRACT = 49,
RISCV_G_UNMERGE_VALUES = 50,
RISCV_G_INSERT = 51,
RISCV_G_MERGE_VALUES = 52,
RISCV_G_BUILD_VECTOR = 53,
RISCV_G_BUILD_VECTOR_TRUNC = 54,
RISCV_G_CONCAT_VECTORS = 55,
RISCV_G_PTRTOINT = 56,
RISCV_G_INTTOPTR = 57,
RISCV_G_BITCAST = 58,
RISCV_G_INTRINSIC_TRUNC = 59,
RISCV_G_INTRINSIC_ROUND = 60,
RISCV_G_LOAD = 61,
RISCV_G_SEXTLOAD = 62,
RISCV_G_ZEXTLOAD = 63,
RISCV_G_STORE = 64,
RISCV_G_ATOMIC_CMPXCHG_WITH_SUCCESS = 65,
RISCV_G_ATOMIC_CMPXCHG = 66,
RISCV_G_ATOMICRMW_XCHG = 67,
RISCV_G_ATOMICRMW_ADD = 68,
RISCV_G_ATOMICRMW_SUB = 69,
RISCV_G_ATOMICRMW_AND = 70,
RISCV_G_ATOMICRMW_NAND = 71,
RISCV_G_ATOMICRMW_OR = 72,
RISCV_G_ATOMICRMW_XOR = 73,
RISCV_G_ATOMICRMW_MAX = 74,
RISCV_G_ATOMICRMW_MIN = 75,
RISCV_G_ATOMICRMW_UMAX = 76,
RISCV_G_ATOMICRMW_UMIN = 77,
RISCV_G_BRCOND = 78,
RISCV_G_BRINDIRECT = 79,
RISCV_G_INTRINSIC = 80,
RISCV_G_INTRINSIC_W_SIDE_EFFECTS = 81,
RISCV_G_ANYEXT = 82,
RISCV_G_TRUNC = 83,
RISCV_G_CONSTANT = 84,
RISCV_G_FCONSTANT = 85,
RISCV_G_VASTART = 86,
RISCV_G_VAARG = 87,
RISCV_G_SEXT = 88,
RISCV_G_ZEXT = 89,
RISCV_G_SHL = 90,
RISCV_G_LSHR = 91,
RISCV_G_ASHR = 92,
RISCV_G_ICMP = 93,
RISCV_G_FCMP = 94,
RISCV_G_SELECT = 95,
RISCV_G_UADDO = 96,
RISCV_G_UADDE = 97,
RISCV_G_USUBO = 98,
RISCV_G_USUBE = 99,
RISCV_G_SADDO = 100,
RISCV_G_SADDE = 101,
RISCV_G_SSUBO = 102,
RISCV_G_SSUBE = 103,
RISCV_G_UMULO = 104,
RISCV_G_SMULO = 105,
RISCV_G_UMULH = 106,
RISCV_G_SMULH = 107,
RISCV_G_FADD = 108,
RISCV_G_FSUB = 109,
RISCV_G_FMUL = 110,
RISCV_G_FMA = 111,
RISCV_G_FDIV = 112,
RISCV_G_FREM = 113,
RISCV_G_FPOW = 114,
RISCV_G_FEXP = 115,
RISCV_G_FEXP2 = 116,
RISCV_G_FLOG = 117,
RISCV_G_FLOG2 = 118,
RISCV_G_FLOG10 = 119,
RISCV_G_FNEG = 120,
RISCV_G_FPEXT = 121,
RISCV_G_FPTRUNC = 122,
RISCV_G_FPTOSI = 123,
RISCV_G_FPTOUI = 124,
RISCV_G_SITOFP = 125,
RISCV_G_UITOFP = 126,
RISCV_G_FABS = 127,
RISCV_G_FCANONICALIZE = 128,
RISCV_G_GEP = 129,
RISCV_G_PTR_MASK = 130,
RISCV_G_BR = 131,
RISCV_G_INSERT_VECTOR_ELT = 132,
RISCV_G_EXTRACT_VECTOR_ELT = 133,
RISCV_G_SHUFFLE_VECTOR = 134,
RISCV_G_CTTZ = 135,
RISCV_G_CTTZ_ZERO_UNDEF = 136,
RISCV_G_CTLZ = 137,
RISCV_G_CTLZ_ZERO_UNDEF = 138,
RISCV_G_CTPOP = 139,
RISCV_G_BSWAP = 140,
RISCV_G_FCEIL = 141,
RISCV_G_FCOS = 142,
RISCV_G_FSIN = 143,
RISCV_G_FSQRT = 144,
RISCV_G_FFLOOR = 145,
RISCV_G_ADDRSPACE_CAST = 146,
RISCV_G_BLOCK_ADDR = 147,
RISCV_ADJCALLSTACKDOWN = 148,
RISCV_ADJCALLSTACKUP = 149,
RISCV_BuildPairF64Pseudo = 150,
RISCV_PseudoAtomicLoadNand32 = 151,
RISCV_PseudoAtomicLoadNand64 = 152,
RISCV_PseudoBR = 153,
RISCV_PseudoBRIND = 154,
RISCV_PseudoCALL = 155,
RISCV_PseudoCALLIndirect = 156,
RISCV_PseudoCmpXchg32 = 157,
RISCV_PseudoCmpXchg64 = 158,
RISCV_PseudoLA = 159,
RISCV_PseudoLI = 160,
RISCV_PseudoLLA = 161,
RISCV_PseudoMaskedAtomicLoadAdd32 = 162,
RISCV_PseudoMaskedAtomicLoadMax32 = 163,
RISCV_PseudoMaskedAtomicLoadMin32 = 164,
RISCV_PseudoMaskedAtomicLoadNand32 = 165,
RISCV_PseudoMaskedAtomicLoadSub32 = 166,
RISCV_PseudoMaskedAtomicLoadUMax32 = 167,
RISCV_PseudoMaskedAtomicLoadUMin32 = 168,
RISCV_PseudoMaskedAtomicSwap32 = 169,
RISCV_PseudoMaskedCmpXchg32 = 170,
RISCV_PseudoRET = 171,
RISCV_PseudoTAIL = 172,
RISCV_PseudoTAILIndirect = 173,
RISCV_Select_FPR32_Using_CC_GPR = 174,
RISCV_Select_FPR64_Using_CC_GPR = 175,
RISCV_Select_GPR_Using_CC_GPR = 176,
RISCV_SplitF64Pseudo = 177,
RISCV_ADD = 178,
RISCV_ADDI = 179,
RISCV_ADDIW = 180,
RISCV_ADDW = 181,
RISCV_AMOADD_D = 182,
RISCV_AMOADD_D_AQ = 183,
RISCV_AMOADD_D_AQ_RL = 184,
RISCV_AMOADD_D_RL = 185,
RISCV_AMOADD_W = 186,
RISCV_AMOADD_W_AQ = 187,
RISCV_AMOADD_W_AQ_RL = 188,
RISCV_AMOADD_W_RL = 189,
RISCV_AMOAND_D = 190,
RISCV_AMOAND_D_AQ = 191,
RISCV_AMOAND_D_AQ_RL = 192,
RISCV_AMOAND_D_RL = 193,
RISCV_AMOAND_W = 194,
RISCV_AMOAND_W_AQ = 195,
RISCV_AMOAND_W_AQ_RL = 196,
RISCV_AMOAND_W_RL = 197,
RISCV_AMOMAXU_D = 198,
RISCV_AMOMAXU_D_AQ = 199,
RISCV_AMOMAXU_D_AQ_RL = 200,
RISCV_AMOMAXU_D_RL = 201,
RISCV_AMOMAXU_W = 202,
RISCV_AMOMAXU_W_AQ = 203,
RISCV_AMOMAXU_W_AQ_RL = 204,
RISCV_AMOMAXU_W_RL = 205,
RISCV_AMOMAX_D = 206,
RISCV_AMOMAX_D_AQ = 207,
RISCV_AMOMAX_D_AQ_RL = 208,
RISCV_AMOMAX_D_RL = 209,
RISCV_AMOMAX_W = 210,
RISCV_AMOMAX_W_AQ = 211,
RISCV_AMOMAX_W_AQ_RL = 212,
RISCV_AMOMAX_W_RL = 213,
RISCV_AMOMINU_D = 214,
RISCV_AMOMINU_D_AQ = 215,
RISCV_AMOMINU_D_AQ_RL = 216,
RISCV_AMOMINU_D_RL = 217,
RISCV_AMOMINU_W = 218,
RISCV_AMOMINU_W_AQ = 219,
RISCV_AMOMINU_W_AQ_RL = 220,
RISCV_AMOMINU_W_RL = 221,
RISCV_AMOMIN_D = 222,
RISCV_AMOMIN_D_AQ = 223,
RISCV_AMOMIN_D_AQ_RL = 224,
RISCV_AMOMIN_D_RL = 225,
RISCV_AMOMIN_W = 226,
RISCV_AMOMIN_W_AQ = 227,
RISCV_AMOMIN_W_AQ_RL = 228,
RISCV_AMOMIN_W_RL = 229,
RISCV_AMOOR_D = 230,
RISCV_AMOOR_D_AQ = 231,
RISCV_AMOOR_D_AQ_RL = 232,
RISCV_AMOOR_D_RL = 233,
RISCV_AMOOR_W = 234,
RISCV_AMOOR_W_AQ = 235,
RISCV_AMOOR_W_AQ_RL = 236,
RISCV_AMOOR_W_RL = 237,
RISCV_AMOSWAP_D = 238,
RISCV_AMOSWAP_D_AQ = 239,
RISCV_AMOSWAP_D_AQ_RL = 240,
RISCV_AMOSWAP_D_RL = 241,
RISCV_AMOSWAP_W = 242,
RISCV_AMOSWAP_W_AQ = 243,
RISCV_AMOSWAP_W_AQ_RL = 244,
RISCV_AMOSWAP_W_RL = 245,
RISCV_AMOXOR_D = 246,
RISCV_AMOXOR_D_AQ = 247,
RISCV_AMOXOR_D_AQ_RL = 248,
RISCV_AMOXOR_D_RL = 249,
RISCV_AMOXOR_W = 250,
RISCV_AMOXOR_W_AQ = 251,
RISCV_AMOXOR_W_AQ_RL = 252,
RISCV_AMOXOR_W_RL = 253,
RISCV_AND = 254,
RISCV_ANDI = 255,
RISCV_AUIPC = 256,
RISCV_BEQ = 257,
RISCV_BGE = 258,
RISCV_BGEU = 259,
RISCV_BLT = 260,
RISCV_BLTU = 261,
RISCV_BNE = 262,
RISCV_CSRRC = 263,
RISCV_CSRRCI = 264,
RISCV_CSRRS = 265,
RISCV_CSRRSI = 266,
RISCV_CSRRW = 267,
RISCV_CSRRWI = 268,
RISCV_C_ADD = 269,
RISCV_C_ADDI = 270,
RISCV_C_ADDI16SP = 271,
RISCV_C_ADDI4SPN = 272,
RISCV_C_ADDIW = 273,
RISCV_C_ADDW = 274,
RISCV_C_AND = 275,
RISCV_C_ANDI = 276,
RISCV_C_BEQZ = 277,
RISCV_C_BNEZ = 278,
RISCV_C_EBREAK = 279,
RISCV_C_FLD = 280,
RISCV_C_FLDSP = 281,
RISCV_C_FLW = 282,
RISCV_C_FLWSP = 283,
RISCV_C_FSD = 284,
RISCV_C_FSDSP = 285,
RISCV_C_FSW = 286,
RISCV_C_FSWSP = 287,
RISCV_C_J = 288,
RISCV_C_JAL = 289,
RISCV_C_JALR = 290,
RISCV_C_JR = 291,
RISCV_C_LD = 292,
RISCV_C_LDSP = 293,
RISCV_C_LI = 294,
RISCV_C_LUI = 295,
RISCV_C_LW = 296,
RISCV_C_LWSP = 297,
RISCV_C_MV = 298,
RISCV_C_NOP = 299,
RISCV_C_OR = 300,
RISCV_C_SD = 301,
RISCV_C_SDSP = 302,
RISCV_C_SLLI = 303,
RISCV_C_SRAI = 304,
RISCV_C_SRLI = 305,
RISCV_C_SUB = 306,
RISCV_C_SUBW = 307,
RISCV_C_SW = 308,
RISCV_C_SWSP = 309,
RISCV_C_UNIMP = 310,
RISCV_C_XOR = 311,
RISCV_DIV = 312,
RISCV_DIVU = 313,
RISCV_DIVUW = 314,
RISCV_DIVW = 315,
RISCV_EBREAK = 316,
RISCV_ECALL = 317,
RISCV_FADD_D = 318,
RISCV_FADD_S = 319,
RISCV_FCLASS_D = 320,
RISCV_FCLASS_S = 321,
RISCV_FCVT_D_L = 322,
RISCV_FCVT_D_LU = 323,
RISCV_FCVT_D_S = 324,
RISCV_FCVT_D_W = 325,
RISCV_FCVT_D_WU = 326,
RISCV_FCVT_LU_D = 327,
RISCV_FCVT_LU_S = 328,
RISCV_FCVT_L_D = 329,
RISCV_FCVT_L_S = 330,
RISCV_FCVT_S_D = 331,
RISCV_FCVT_S_L = 332,
RISCV_FCVT_S_LU = 333,
RISCV_FCVT_S_W = 334,
RISCV_FCVT_S_WU = 335,
RISCV_FCVT_WU_D = 336,
RISCV_FCVT_WU_S = 337,
RISCV_FCVT_W_D = 338,
RISCV_FCVT_W_S = 339,
RISCV_FDIV_D = 340,
RISCV_FDIV_S = 341,
RISCV_FENCE = 342,
RISCV_FENCE_I = 343,
RISCV_FENCE_TSO = 344,
RISCV_FEQ_D = 345,
RISCV_FEQ_S = 346,
RISCV_FLD = 347,
RISCV_FLE_D = 348,
RISCV_FLE_S = 349,
RISCV_FLT_D = 350,
RISCV_FLT_S = 351,
RISCV_FLW = 352,
RISCV_FMADD_D = 353,
RISCV_FMADD_S = 354,
RISCV_FMAX_D = 355,
RISCV_FMAX_S = 356,
RISCV_FMIN_D = 357,
RISCV_FMIN_S = 358,
RISCV_FMSUB_D = 359,
RISCV_FMSUB_S = 360,
RISCV_FMUL_D = 361,
RISCV_FMUL_S = 362,
RISCV_FMV_D_X = 363,
RISCV_FMV_W_X = 364,
RISCV_FMV_X_D = 365,
RISCV_FMV_X_W = 366,
RISCV_FNMADD_D = 367,
RISCV_FNMADD_S = 368,
RISCV_FNMSUB_D = 369,
RISCV_FNMSUB_S = 370,
RISCV_FSD = 371,
RISCV_FSGNJN_D = 372,
RISCV_FSGNJN_S = 373,
RISCV_FSGNJX_D = 374,
RISCV_FSGNJX_S = 375,
RISCV_FSGNJ_D = 376,
RISCV_FSGNJ_S = 377,
RISCV_FSQRT_D = 378,
RISCV_FSQRT_S = 379,
RISCV_FSUB_D = 380,
RISCV_FSUB_S = 381,
RISCV_FSW = 382,
RISCV_JAL = 383,
RISCV_JALR = 384,
RISCV_LB = 385,
RISCV_LBU = 386,
RISCV_LD = 387,
RISCV_LH = 388,
RISCV_LHU = 389,
RISCV_LR_D = 390,
RISCV_LR_D_AQ = 391,
RISCV_LR_D_AQ_RL = 392,
RISCV_LR_D_RL = 393,
RISCV_LR_W = 394,
RISCV_LR_W_AQ = 395,
RISCV_LR_W_AQ_RL = 396,
RISCV_LR_W_RL = 397,
RISCV_LUI = 398,
RISCV_LW = 399,
RISCV_LWU = 400,
RISCV_MRET = 401,
RISCV_MUL = 402,
RISCV_MULH = 403,
RISCV_MULHSU = 404,
RISCV_MULHU = 405,
RISCV_MULW = 406,
RISCV_OR = 407,
RISCV_ORI = 408,
RISCV_REM = 409,
RISCV_REMU = 410,
RISCV_REMUW = 411,
RISCV_REMW = 412,
RISCV_SB = 413,
RISCV_SC_D = 414,
RISCV_SC_D_AQ = 415,
RISCV_SC_D_AQ_RL = 416,
RISCV_SC_D_RL = 417,
RISCV_SC_W = 418,
RISCV_SC_W_AQ = 419,
RISCV_SC_W_AQ_RL = 420,
RISCV_SC_W_RL = 421,
RISCV_SD = 422,
RISCV_SFENCE_VMA = 423,
RISCV_SH = 424,
RISCV_SLL = 425,
RISCV_SLLI = 426,
RISCV_SLLIW = 427,
RISCV_SLLW = 428,
RISCV_SLT = 429,
RISCV_SLTI = 430,
RISCV_SLTIU = 431,
RISCV_SLTU = 432,
RISCV_SRA = 433,
RISCV_SRAI = 434,
RISCV_SRAIW = 435,
RISCV_SRAW = 436,
RISCV_SRET = 437,
RISCV_SRL = 438,
RISCV_SRLI = 439,
RISCV_SRLIW = 440,
RISCV_SRLW = 441,
RISCV_SUB = 442,
RISCV_SUBW = 443,
RISCV_SW = 444,
RISCV_UNIMP = 445,
RISCV_URET = 446,
RISCV_WFI = 447,
RISCV_XOR = 448,
RISCV_XORI = 449,
RISCV_INSTRUCTION_LIST_END = 450
};
#endif // GET_INSTRINFO_ENUM
external/capstone/arch/RISCV/RISCVGenRegisterInfo.inc
Vendored
+426
View File
@@ -0,0 +1,426 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Target Register Enum Values *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef GET_REGINFO_ENUM
#undef GET_REGINFO_ENUM
enum {
RISCV_NoRegister,
RISCV_X0 = 1,
RISCV_X1 = 2,
RISCV_X2 = 3,
RISCV_X3 = 4,
RISCV_X4 = 5,
RISCV_X5 = 6,
RISCV_X6 = 7,
RISCV_X7 = 8,
RISCV_X8 = 9,
RISCV_X9 = 10,
RISCV_X10 = 11,
RISCV_X11 = 12,
RISCV_X12 = 13,
RISCV_X13 = 14,
RISCV_X14 = 15,
RISCV_X15 = 16,
RISCV_X16 = 17,
RISCV_X17 = 18,
RISCV_X18 = 19,
RISCV_X19 = 20,
RISCV_X20 = 21,
RISCV_X21 = 22,
RISCV_X22 = 23,
RISCV_X23 = 24,
RISCV_X24 = 25,
RISCV_X25 = 26,
RISCV_X26 = 27,
RISCV_X27 = 28,
RISCV_X28 = 29,
RISCV_X29 = 30,
RISCV_X30 = 31,
RISCV_X31 = 32,
RISCV_F0_32 = 33,
RISCV_F0_64 = 34,
RISCV_F1_32 = 35,
RISCV_F1_64 = 36,
RISCV_F2_32 = 37,
RISCV_F2_64 = 38,
RISCV_F3_32 = 39,
RISCV_F3_64 = 40,
RISCV_F4_32 = 41,
RISCV_F4_64 = 42,
RISCV_F5_32 = 43,
RISCV_F5_64 = 44,
RISCV_F6_32 = 45,
RISCV_F6_64 = 46,
RISCV_F7_32 = 47,
RISCV_F7_64 = 48,
RISCV_F8_32 = 49,
RISCV_F8_64 = 50,
RISCV_F9_32 = 51,
RISCV_F9_64 = 52,
RISCV_F10_32 = 53,
RISCV_F10_64 = 54,
RISCV_F11_32 = 55,
RISCV_F11_64 = 56,
RISCV_F12_32 = 57,
RISCV_F12_64 = 58,
RISCV_F13_32 = 59,
RISCV_F13_64 = 60,
RISCV_F14_32 = 61,
RISCV_F14_64 = 62,
RISCV_F15_32 = 63,
RISCV_F15_64 = 64,
RISCV_F16_32 = 65,
RISCV_F16_64 = 66,
RISCV_F17_32 = 67,
RISCV_F17_64 = 68,
RISCV_F18_32 = 69,
RISCV_F18_64 = 70,
RISCV_F19_32 = 71,
RISCV_F19_64 = 72,
RISCV_F20_32 = 73,
RISCV_F20_64 = 74,
RISCV_F21_32 = 75,
RISCV_F21_64 = 76,
RISCV_F22_32 = 77,
RISCV_F22_64 = 78,
RISCV_F23_32 = 79,
RISCV_F23_64 = 80,
RISCV_F24_32 = 81,
RISCV_F24_64 = 82,
RISCV_F25_32 = 83,
RISCV_F25_64 = 84,
RISCV_F26_32 = 85,
RISCV_F26_64 = 86,
RISCV_F27_32 = 87,
RISCV_F27_64 = 88,
RISCV_F28_32 = 89,
RISCV_F28_64 = 90,
RISCV_F29_32 = 91,
RISCV_F29_64 = 92,
RISCV_F30_32 = 93,
RISCV_F30_64 = 94,
RISCV_F31_32 = 95,
RISCV_F31_64 = 96,
RISCV_NUM_TARGET_REGS // 97
};
// Register classes
enum {
RISCV_FPR32RegClassID = 0,
RISCV_GPRRegClassID = 1,
RISCV_GPRNoX0RegClassID = 2,
RISCV_GPRNoX0X2RegClassID = 3,
RISCV_GPRTCRegClassID = 4,
RISCV_FPR32CRegClassID = 5,
RISCV_GPRCRegClassID = 6,
RISCV_GPRC_and_GPRTCRegClassID = 7,
RISCV_SPRegClassID = 8,
RISCV_FPR64RegClassID = 9,
RISCV_FPR64CRegClassID = 10,
};
// Register alternate name indices
enum {
RISCV_ABIRegAltName, // 0
RISCV_NoRegAltName, // 1
RISCV_NUM_TARGET_REG_ALT_NAMES = 2
};
// Subregister indices
enum {
RISCV_NoSubRegister,
RISCV_sub_32, // 1
RISCV_NUM_TARGET_SUBREGS
};
#endif // GET_REGINFO_ENUM
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* MC Register Information *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
#ifdef GET_REGINFO_MC_DESC
#undef GET_REGINFO_MC_DESC
static const MCPhysReg RISCVRegDiffLists[] = {
/* 0 */ 1, 0,
/* 2 */ 32, 0,
/* 4 */ 33, 0,
/* 6 */ 34, 0,
/* 8 */ 35, 0,
/* 10 */ 36, 0,
/* 12 */ 37, 0,
/* 14 */ 38, 0,
/* 16 */ 39, 0,
/* 18 */ 40, 0,
/* 20 */ 41, 0,
/* 22 */ 42, 0,
/* 24 */ 43, 0,
/* 26 */ 44, 0,
/* 28 */ 45, 0,
/* 30 */ 46, 0,
/* 32 */ 47, 0,
/* 34 */ 48, 0,
/* 36 */ 49, 0,
/* 38 */ 50, 0,
/* 40 */ 51, 0,
/* 42 */ 52, 0,
/* 44 */ 53, 0,
/* 46 */ 54, 0,
/* 48 */ 55, 0,
/* 50 */ 56, 0,
/* 52 */ 57, 0,
/* 54 */ 58, 0,
/* 56 */ 59, 0,
/* 58 */ 60, 0,
/* 60 */ 61, 0,
/* 62 */ 62, 0,
/* 64 */ 63, 0,
/* 66 */ -1, 0,
};
static const uint16_t RISCVSubRegIdxLists[] = {
/* 0 */ 1, 0,
};
static const MCRegisterDesc RISCVRegDesc[] = { // Descriptors
{ 3, 0, 0, 0, 0, 0 },
{ 12, 1, 1, 1, 1057, 0 },
{ 27, 1, 1, 1, 1057, 0 },
{ 252, 1, 1, 1, 1057, 0 },
{ 263, 1, 1, 1, 1057, 0 },
{ 488, 1, 1, 1, 1057, 0 },
{ 499, 1, 1, 1, 1057, 0 },
{ 510, 1, 1, 1, 1057, 0 },
{ 521, 1, 1, 1, 1057, 0 },
{ 532, 1, 1, 1, 1057, 0 },
{ 543, 1, 1, 1, 1057, 0 },
{ 0, 1, 1, 1, 1057, 0 },
{ 15, 1, 1, 1, 1057, 0 },
{ 30, 1, 1, 1, 1057, 0 },
{ 255, 1, 1, 1, 1057, 0 },
{ 266, 1, 1, 1, 1057, 0 },
{ 491, 1, 1, 1, 1057, 0 },
{ 502, 1, 1, 1, 1057, 0 },
{ 513, 1, 1, 1, 1057, 0 },
{ 524, 1, 1, 1, 1057, 0 },
{ 535, 1, 1, 1, 1057, 0 },
{ 4, 1, 1, 1, 1057, 0 },
{ 19, 1, 1, 1, 1057, 0 },
{ 34, 1, 1, 1, 1057, 0 },
{ 259, 1, 1, 1, 1057, 0 },
{ 270, 1, 1, 1, 1057, 0 },
{ 495, 1, 1, 1, 1057, 0 },
{ 506, 1, 1, 1, 1057, 0 },
{ 517, 1, 1, 1, 1057, 0 },
{ 528, 1, 1, 1, 1057, 0 },
{ 539, 1, 1, 1, 1057, 0 },
{ 8, 1, 1, 1, 1057, 0 },
{ 23, 1, 1, 1, 1057, 0 },
{ 59, 1, 0, 1, 32, 0 },
{ 295, 66, 1, 0, 32, 2 },
{ 86, 1, 0, 1, 64, 0 },
{ 322, 66, 1, 0, 64, 2 },
{ 106, 1, 0, 1, 96, 0 },
{ 342, 66, 1, 0, 96, 2 },
{ 126, 1, 0, 1, 128, 0 },
{ 362, 66, 1, 0, 128, 2 },
{ 146, 1, 0, 1, 160, 0 },
{ 382, 66, 1, 0, 160, 2 },
{ 166, 1, 0, 1, 192, 0 },
{ 402, 66, 1, 0, 192, 2 },
{ 186, 1, 0, 1, 224, 0 },
{ 422, 66, 1, 0, 224, 2 },
{ 206, 1, 0, 1, 256, 0 },
{ 442, 66, 1, 0, 256, 2 },
{ 226, 1, 0, 1, 288, 0 },
{ 462, 66, 1, 0, 288, 2 },
{ 246, 1, 0, 1, 320, 0 },
{ 482, 66, 1, 0, 320, 2 },
{ 38, 1, 0, 1, 352, 0 },
{ 274, 66, 1, 0, 352, 2 },
{ 65, 1, 0, 1, 384, 0 },
{ 301, 66, 1, 0, 384, 2 },
{ 92, 1, 0, 1, 416, 0 },
{ 328, 66, 1, 0, 416, 2 },
{ 112, 1, 0, 1, 448, 0 },
{ 348, 66, 1, 0, 448, 2 },
{ 132, 1, 0, 1, 480, 0 },
{ 368, 66, 1, 0, 480, 2 },
{ 152, 1, 0, 1, 512, 0 },
{ 388, 66, 1, 0, 512, 2 },
{ 172, 1, 0, 1, 544, 0 },
{ 408, 66, 1, 0, 544, 2 },
{ 192, 1, 0, 1, 576, 0 },
{ 428, 66, 1, 0, 576, 2 },
{ 212, 1, 0, 1, 608, 0 },
{ 448, 66, 1, 0, 608, 2 },
{ 232, 1, 0, 1, 640, 0 },
{ 468, 66, 1, 0, 640, 2 },
{ 45, 1, 0, 1, 672, 0 },
{ 281, 66, 1, 0, 672, 2 },
{ 72, 1, 0, 1, 704, 0 },
{ 308, 66, 1, 0, 704, 2 },
{ 99, 1, 0, 1, 736, 0 },
{ 335, 66, 1, 0, 736, 2 },
{ 119, 1, 0, 1, 768, 0 },
{ 355, 66, 1, 0, 768, 2 },
{ 139, 1, 0, 1, 800, 0 },
{ 375, 66, 1, 0, 800, 2 },
{ 159, 1, 0, 1, 832, 0 },
{ 395, 66, 1, 0, 832, 2 },
{ 179, 1, 0, 1, 864, 0 },
{ 415, 66, 1, 0, 864, 2 },
{ 199, 1, 0, 1, 896, 0 },
{ 435, 66, 1, 0, 896, 2 },
{ 219, 1, 0, 1, 928, 0 },
{ 455, 66, 1, 0, 928, 2 },
{ 239, 1, 0, 1, 960, 0 },
{ 475, 66, 1, 0, 960, 2 },
{ 52, 1, 0, 1, 992, 0 },
{ 288, 66, 1, 0, 992, 2 },
{ 79, 1, 0, 1, 1024, 0 },
{ 315, 66, 1, 0, 1024, 2 },
};
// FPR32 Register Class...
static const MCPhysReg FPR32[] = {
RISCV_F0_32, RISCV_F1_32, RISCV_F2_32, RISCV_F3_32, RISCV_F4_32, RISCV_F5_32, RISCV_F6_32, RISCV_F7_32, RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F16_32, RISCV_F17_32, RISCV_F28_32, RISCV_F29_32, RISCV_F30_32, RISCV_F31_32, RISCV_F8_32, RISCV_F9_32, RISCV_F18_32, RISCV_F19_32, RISCV_F20_32, RISCV_F21_32, RISCV_F22_32, RISCV_F23_32, RISCV_F24_32, RISCV_F25_32, RISCV_F26_32, RISCV_F27_32,
};
// FPR32 Bit set.
static const uint8_t FPR32Bits[] = {
0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa, 0xaa,
};
// GPR Register Class...
static const MCPhysReg GPR[] = {
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X0, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
};
// GPR Bit set.
static const uint8_t GPRBits[] = {
0xfe, 0xff, 0xff, 0xff, 0x01,
};
// GPRNoX0 Register Class...
static const MCPhysReg GPRNoX0[] = {
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X2, RISCV_X3, RISCV_X4,
};
// GPRNoX0 Bit set.
static const uint8_t GPRNoX0Bits[] = {
0xfc, 0xff, 0xff, 0xff, 0x01,
};
// GPRNoX0X2 Register Class...
static const MCPhysReg GPRNoX0X2[] = {
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31, RISCV_X8, RISCV_X9, RISCV_X18, RISCV_X19, RISCV_X20, RISCV_X21, RISCV_X22, RISCV_X23, RISCV_X24, RISCV_X25, RISCV_X26, RISCV_X27, RISCV_X1, RISCV_X3, RISCV_X4,
};
// GPRNoX0X2 Bit set.
static const uint8_t GPRNoX0X2Bits[] = {
0xf4, 0xff, 0xff, 0xff, 0x01,
};
// GPRTC Register Class...
static const MCPhysReg GPRTC[] = {
RISCV_X5, RISCV_X6, RISCV_X7, RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X16, RISCV_X17, RISCV_X28, RISCV_X29, RISCV_X30, RISCV_X31,
};
// GPRTC Bit set.
static const uint8_t GPRTCBits[] = {
0xc0, 0xf9, 0x07, 0xe0, 0x01,
};
// FPR32C Register Class...
static const MCPhysReg FPR32C[] = {
RISCV_F10_32, RISCV_F11_32, RISCV_F12_32, RISCV_F13_32, RISCV_F14_32, RISCV_F15_32, RISCV_F8_32, RISCV_F9_32,
};
// FPR32C Bit set.
static const uint8_t FPR32CBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xaa, 0xaa,
};
// GPRC Register Class...
static const MCPhysReg GPRC[] = {
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15, RISCV_X8, RISCV_X9,
};
// GPRC Bit set.
static const uint8_t GPRCBits[] = {
0x00, 0xfe, 0x01,
};
// GPRC_and_GPRTC Register Class...
static const MCPhysReg GPRC_and_GPRTC[] = {
RISCV_X10, RISCV_X11, RISCV_X12, RISCV_X13, RISCV_X14, RISCV_X15,
};
// GPRC_and_GPRTC Bit set.
static const uint8_t GPRC_and_GPRTCBits[] = {
0x00, 0xf8, 0x01,
};
// SP Register Class...
static const MCPhysReg SP[] = {
RISCV_X2,
};
// SP Bit set.
static const uint8_t SPBits[] = {
0x08,
};
// FPR64 Register Class...
static const MCPhysReg FPR64[] = {
RISCV_F0_64, RISCV_F1_64, RISCV_F2_64, RISCV_F3_64, RISCV_F4_64, RISCV_F5_64, RISCV_F6_64, RISCV_F7_64, RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F16_64, RISCV_F17_64, RISCV_F28_64, RISCV_F29_64, RISCV_F30_64, RISCV_F31_64, RISCV_F8_64, RISCV_F9_64, RISCV_F18_64, RISCV_F19_64, RISCV_F20_64, RISCV_F21_64, RISCV_F22_64, RISCV_F23_64, RISCV_F24_64, RISCV_F25_64, RISCV_F26_64, RISCV_F27_64,
};
// FPR64 Bit set.
static const uint8_t FPR64Bits[] = {
0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x55, 0x01,
};
// FPR64C Register Class...
static const MCPhysReg FPR64C[] = {
RISCV_F10_64, RISCV_F11_64, RISCV_F12_64, RISCV_F13_64, RISCV_F14_64, RISCV_F15_64, RISCV_F8_64, RISCV_F9_64,
};
// FPR64C Bit set.
static const uint8_t FPR64CBits[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x55, 0x01,
};
static const MCRegisterClass RISCVMCRegisterClasses[] = {
{ FPR32, FPR32Bits, sizeof(FPR32Bits) },
{ GPR, GPRBits, sizeof(GPRBits) },
{ GPRNoX0, GPRNoX0Bits, sizeof(GPRNoX0Bits) },
{ GPRNoX0X2, GPRNoX0X2Bits, sizeof(GPRNoX0X2Bits) },
{ GPRTC, GPRTCBits, sizeof(GPRTCBits) },
{ FPR32C, FPR32CBits, sizeof(FPR32CBits) },
{ GPRC, GPRCBits, sizeof(GPRCBits) },
{ GPRC_and_GPRTC, GPRC_and_GPRTCBits, sizeof(GPRC_and_GPRTCBits) },
{ SP, SPBits, sizeof(SPBits) },
{ FPR64, FPR64Bits, sizeof(FPR64Bits) },
{ FPR64C, FPR64CBits, sizeof(FPR64CBits) },
};
#endif // GET_REGINFO_MC_DESC
external/capstone/arch/RISCV/RISCVGenSubtargetInfo.inc
Vendored
+33
View File
@@ -0,0 +1,33 @@
/*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
|* *|
|* Subtarget Enumeration Source Fragment *|
|* *|
|* Automatically generated file, do not edit! *|
|* *|
\*===----------------------------------------------------------------------===*/
/* Capstone Disassembly Engine, http://www.capstone-engine.org */
/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
#ifdef GET_SUBTARGETINFO_ENUM
#undef GET_SUBTARGETINFO_ENUM
/*
Make sure:
CS_MODE_RISCV64 = 0b11111
CS_MODE_RISCV32 = 0b11110
*/
enum {
RISCV_Feature64Bit = 1ULL << 0,
RISCV_FeatureStdExtA = 1ULL << 1,
RISCV_FeatureStdExtC = 1ULL << 2,
RISCV_FeatureStdExtD = 1ULL << 3,
RISCV_FeatureStdExtF = 1ULL << 4,
RISCV_FeatureStdExtM = 1ULL << 5,
RISCV_FeatureRelax = 1ULL << 6,
};
#endif // GET_SUBTARGETINFO_ENUM
external/capstone/arch/RISCV/RISCVInstPrinter.c
Vendored
+591
View File
@@ -0,0 +1,591 @@
//===-- RISCVInstPrinter.cpp - Convert RISCV MCInst to asm syntax ---------===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an RISCV MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifdef CAPSTONE_HAS_RISCV
#include <stdio.h> // DEBUG
#include <stdlib.h>
#include <string.h>
#include <capstone/platform.h>
#include "RISCVInstPrinter.h"
#include "RISCVBaseInfo.h"
#include "../../MCInst.h"
#include "../../SStream.h"
#include "../../MCRegisterInfo.h"
#include "../../utils.h"
#include "../../Mapping.h"
#include "RISCVMapping.h"
//#include "RISCVDisassembler.h"
#define GET_REGINFO_ENUM
#define GET_REGINFO_MC_DESC
#include "RISCVGenRegisterInfo.inc"
#define GET_INSTRINFO_ENUM
#include "RISCVGenInstrInfo.inc"
// Autogenerated by tblgen.
static void printInstruction(MCInst *MI, SStream *O, MCRegisterInfo *MRI);
static bool printAliasInstr(MCInst *MI, SStream *OS, void *info);
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O);
static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O);
static void printCSRSystemRegister(MCInst*, unsigned, SStream *);
static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O);
static void printCustomAliasOperand( MCInst *, unsigned, unsigned, SStream *);
/// getRegisterName - This method is automatically generated by tblgen
/// from the register set description. This returns the assembler name
/// for the specified register.
static const char *getRegisterName(unsigned RegNo, unsigned AltIdx);
// Include the auto-generated portion of the assembly writer.
#define PRINT_ALIAS_INSTR
#include "RISCVGenAsmWriter.inc"
static void fixDetailOfEffectiveAddr(MCInst *MI)
{
// Operands for load and store instructions in RISCV vary widely
unsigned id = MI->flat_insn->id;
unsigned reg = 0;
int64_t imm = 0;
uint8_t access = 0;
switch (id) {
case RISCV_INS_C_FLD:
case RISCV_INS_C_LW:
case RISCV_INS_C_FLW:
case RISCV_INS_C_LD:
case RISCV_INS_C_FSD:
case RISCV_INS_C_SW:
case RISCV_INS_C_FSW:
case RISCV_INS_C_SD:
case RISCV_INS_C_FLDSP:
case RISCV_INS_C_LWSP:
case RISCV_INS_C_FLWSP:
case RISCV_INS_C_LDSP:
case RISCV_INS_C_FSDSP:
case RISCV_INS_C_SWSP:
case RISCV_INS_C_FSWSP:
case RISCV_INS_C_SDSP:
case RISCV_INS_FLW:
case RISCV_INS_FSW:
case RISCV_INS_FLD:
case RISCV_INS_FSD:
case RISCV_INS_LB:
case RISCV_INS_LBU:
case RISCV_INS_LD:
case RISCV_INS_LH:
case RISCV_INS_LHU:
case RISCV_INS_LW:
case RISCV_INS_LWU:
case RISCV_INS_SB:
case RISCV_INS_SD:
case RISCV_INS_SH:
case RISCV_INS_SW: {
CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count);
CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type);
CS_ASSERT(RISCV_OP_IMM == RISCV_get_detail_op(MI, -2)->type);
CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type);
imm = RISCV_get_detail_op(MI, -2)->imm;
reg = RISCV_get_detail_op(MI, -1)->reg;
access = RISCV_get_detail_op(MI, -1)->access;
RISCV_get_detail_op(MI, -2)->type = RISCV_OP_MEM;
RISCV_get_detail_op(MI, -2)->mem.base = reg;
RISCV_get_detail_op(MI, -2)->mem.disp = imm;
RISCV_get_detail_op(MI, -2)->access = access;
RISCV_dec_op_count(MI);
break;
}
case RISCV_INS_LR_W:
case RISCV_INS_LR_W_AQ:
case RISCV_INS_LR_W_AQ_RL:
case RISCV_INS_LR_W_RL:
case RISCV_INS_LR_D:
case RISCV_INS_LR_D_AQ:
case RISCV_INS_LR_D_AQ_RL:
case RISCV_INS_LR_D_RL: {
CS_ASSERT(2 == MI->flat_insn->detail->riscv.op_count);
CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type);
CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type);
reg = RISCV_get_detail_op(MI, -1)->reg;
RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM;
RISCV_get_detail_op(MI, -1)->mem.base = reg;
RISCV_get_detail_op(MI, -1)->mem.disp = 0;
break;
}
case RISCV_INS_SC_W:
case RISCV_INS_SC_W_AQ:
case RISCV_INS_SC_W_AQ_RL:
case RISCV_INS_SC_W_RL:
case RISCV_INS_SC_D:
case RISCV_INS_SC_D_AQ:
case RISCV_INS_SC_D_AQ_RL:
case RISCV_INS_SC_D_RL:
case RISCV_INS_AMOADD_D:
case RISCV_INS_AMOADD_D_AQ:
case RISCV_INS_AMOADD_D_AQ_RL:
case RISCV_INS_AMOADD_D_RL:
case RISCV_INS_AMOADD_W:
case RISCV_INS_AMOADD_W_AQ:
case RISCV_INS_AMOADD_W_AQ_RL:
case RISCV_INS_AMOADD_W_RL:
case RISCV_INS_AMOAND_D:
case RISCV_INS_AMOAND_D_AQ:
case RISCV_INS_AMOAND_D_AQ_RL:
case RISCV_INS_AMOAND_D_RL:
case RISCV_INS_AMOAND_W:
case RISCV_INS_AMOAND_W_AQ:
case RISCV_INS_AMOAND_W_AQ_RL:
case RISCV_INS_AMOAND_W_RL:
case RISCV_INS_AMOMAXU_D:
case RISCV_INS_AMOMAXU_D_AQ:
case RISCV_INS_AMOMAXU_D_AQ_RL:
case RISCV_INS_AMOMAXU_D_RL:
case RISCV_INS_AMOMAXU_W:
case RISCV_INS_AMOMAXU_W_AQ:
case RISCV_INS_AMOMAXU_W_AQ_RL:
case RISCV_INS_AMOMAXU_W_RL:
case RISCV_INS_AMOMAX_D:
case RISCV_INS_AMOMAX_D_AQ:
case RISCV_INS_AMOMAX_D_AQ_RL:
case RISCV_INS_AMOMAX_D_RL:
case RISCV_INS_AMOMAX_W:
case RISCV_INS_AMOMAX_W_AQ:
case RISCV_INS_AMOMAX_W_AQ_RL:
case RISCV_INS_AMOMAX_W_RL:
case RISCV_INS_AMOMINU_D:
case RISCV_INS_AMOMINU_D_AQ:
case RISCV_INS_AMOMINU_D_AQ_RL:
case RISCV_INS_AMOMINU_D_RL:
case RISCV_INS_AMOMINU_W:
case RISCV_INS_AMOMINU_W_AQ:
case RISCV_INS_AMOMINU_W_AQ_RL:
case RISCV_INS_AMOMINU_W_RL:
case RISCV_INS_AMOMIN_D:
case RISCV_INS_AMOMIN_D_AQ:
case RISCV_INS_AMOMIN_D_AQ_RL:
case RISCV_INS_AMOMIN_D_RL:
case RISCV_INS_AMOMIN_W:
case RISCV_INS_AMOMIN_W_AQ:
case RISCV_INS_AMOMIN_W_AQ_RL:
case RISCV_INS_AMOMIN_W_RL:
case RISCV_INS_AMOOR_D:
case RISCV_INS_AMOOR_D_AQ:
case RISCV_INS_AMOOR_D_AQ_RL:
case RISCV_INS_AMOOR_D_RL:
case RISCV_INS_AMOOR_W:
case RISCV_INS_AMOOR_W_AQ:
case RISCV_INS_AMOOR_W_AQ_RL:
case RISCV_INS_AMOOR_W_RL:
case RISCV_INS_AMOSWAP_D:
case RISCV_INS_AMOSWAP_D_AQ:
case RISCV_INS_AMOSWAP_D_AQ_RL:
case RISCV_INS_AMOSWAP_D_RL:
case RISCV_INS_AMOSWAP_W:
case RISCV_INS_AMOSWAP_W_AQ:
case RISCV_INS_AMOSWAP_W_AQ_RL:
case RISCV_INS_AMOSWAP_W_RL:
case RISCV_INS_AMOXOR_D:
case RISCV_INS_AMOXOR_D_AQ:
case RISCV_INS_AMOXOR_D_AQ_RL:
case RISCV_INS_AMOXOR_D_RL:
case RISCV_INS_AMOXOR_W:
case RISCV_INS_AMOXOR_W_AQ:
case RISCV_INS_AMOXOR_W_AQ_RL:
case RISCV_INS_AMOXOR_W_RL: {
CS_ASSERT(3 == MI->flat_insn->detail->riscv.op_count);
CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -3)->type);
CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -2)->type);
CS_ASSERT(RISCV_OP_REG == RISCV_get_detail_op(MI, -1)->type);
reg = RISCV_get_detail_op(MI, -1)->reg;
RISCV_get_detail_op(MI, -1)->type = RISCV_OP_MEM;
RISCV_get_detail_op(MI, -1)->mem.base = reg;
RISCV_get_detail_op(MI, -1)->mem.disp = 0;
break;
}
default: {
CS_ASSERT(0 && "id is not a RISC-V memory instruction");
break;
}
}
return;
}
//void RISCVInstPrinter::printInst(const MCInst *MI, raw_ostream &O,
// StringRef Annot, const MCSubtargetInfo &STI)
void RISCV_printInst(MCInst *MI, SStream *O, void *info)
{
MCRegisterInfo *MRI = (MCRegisterInfo *) info;
//bool Res = false;
//MCInst *NewMI = MI;
// TODO: RISCV compressd instructions.
//MCInst UncompressedMI;
//if (!NoAliases)
//Res = uncompressInst(UncompressedMI, *MI, MRI, STI);
//if (Res)
//NewMI = const_cast<MCInst *>(&UncompressedMI);
if (/*NoAliases ||*/ !printAliasInstr(MI, O, info))
printInstruction(MI, O, MRI);
//printAnnotation(O, Annot);
// fix load/store type insttuction
if (MI->csh->detail_opt &&
MI->flat_insn->detail->riscv.need_effective_addr)
fixDetailOfEffectiveAddr(MI);
return;
}
static void printRegName(SStream *OS, unsigned RegNo)
{
SStream_concat0(OS, getRegisterName(RegNo, RISCV_ABIRegAltName));
}
/**
void RISCVInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O, const char *Modifier)
*/
static void printOperand(MCInst *MI, unsigned OpNo, SStream *O)
{
unsigned reg;
int64_t Imm = 0;
RISCV_add_cs_detail(MI, OpNo);
MCOperand *MO = MCInst_getOperand(MI, OpNo);
if (MCOperand_isReg(MO)) {
reg = MCOperand_getReg(MO);
printRegName(O, reg);
} else {
CS_ASSERT(MCOperand_isImm(MO) && "Unknown operand kind in printOperand");
Imm = MCOperand_getImm(MO);
if (Imm >= 0) {
if (Imm > HEX_THRESHOLD)
SStream_concat(O, "0x%" PRIx64, Imm);
else
SStream_concat(O, "%" PRIu64, Imm);
} else {
if (Imm < -HEX_THRESHOLD)
SStream_concat(O, "-0x%" PRIx64, -Imm);
else
SStream_concat(O, "-%" PRIu64, -Imm);
}
}
//CS_ASSERT(MO.isExpr() && "Unknown operand kind in printOperand");
return;
}
static const char *getCSRSystemRegisterName(unsigned CsrNo)
{
switch (CsrNo) {
/*
* From RISC-V Privileged Architecture Version 1.10.
* In the same order as Table 2.5.
*/
case 0x0000: return "ustatus";
case 0x0004: return "uie";
case 0x0005: return "utvec";
case 0x0040: return "uscratch";
case 0x0041: return "uepc";
case 0x0042: return "ucause";
case 0x0043: return "utval";
case 0x0044: return "uip";
case 0x0001: return "fflags";
case 0x0002: return "frm";
case 0x0003: return "fcsr";
case 0x0c00: return "cycle";
case 0x0c01: return "time";
case 0x0c02: return "instret";
case 0x0c03: return "hpmcounter3";
case 0x0c04: return "hpmcounter4";
case 0x0c05: return "hpmcounter5";
case 0x0c06: return "hpmcounter6";
case 0x0c07: return "hpmcounter7";
case 0x0c08: return "hpmcounter8";
case 0x0c09: return "hpmcounter9";
case 0x0c0a: return "hpmcounter10";
case 0x0c0b: return "hpmcounter11";
case 0x0c0c: return "hpmcounter12";
case 0x0c0d: return "hpmcounter13";
case 0x0c0e: return "hpmcounter14";
case 0x0c0f: return "hpmcounter15";
case 0x0c10: return "hpmcounter16";
case 0x0c11: return "hpmcounter17";
case 0x0c12: return "hpmcounter18";
case 0x0c13: return "hpmcounter19";
case 0x0c14: return "hpmcounter20";
case 0x0c15: return "hpmcounter21";
case 0x0c16: return "hpmcounter22";
case 0x0c17: return "hpmcounter23";
case 0x0c18: return "hpmcounter24";
case 0x0c19: return "hpmcounter25";
case 0x0c1a: return "hpmcounter26";
case 0x0c1b: return "hpmcounter27";
case 0x0c1c: return "hpmcounter28";
case 0x0c1d: return "hpmcounter29";
case 0x0c1e: return "hpmcounter30";
case 0x0c1f: return "hpmcounter31";
case 0x0c80: return "cycleh";
case 0x0c81: return "timeh";
case 0x0c82: return "instreth";
case 0x0c83: return "hpmcounter3h";
case 0x0c84: return "hpmcounter4h";
case 0x0c85: return "hpmcounter5h";
case 0x0c86: return "hpmcounter6h";
case 0x0c87: return "hpmcounter7h";
case 0x0c88: return "hpmcounter8h";
case 0x0c89: return "hpmcounter9h";
case 0x0c8a: return "hpmcounter10h";
case 0x0c8b: return "hpmcounter11h";
case 0x0c8c: return "hpmcounter12h";
case 0x0c8d: return "hpmcounter13h";
case 0x0c8e: return "hpmcounter14h";
case 0x0c8f: return "hpmcounter15h";
case 0x0c90: return "hpmcounter16h";
case 0x0c91: return "hpmcounter17h";
case 0x0c92: return "hpmcounter18h";
case 0x0c93: return "hpmcounter19h";
case 0x0c94: return "hpmcounter20h";
case 0x0c95: return "hpmcounter21h";
case 0x0c96: return "hpmcounter22h";
case 0x0c97: return "hpmcounter23h";
case 0x0c98: return "hpmcounter24h";
case 0x0c99: return "hpmcounter25h";
case 0x0c9a: return "hpmcounter26h";
case 0x0c9b: return "hpmcounter27h";
case 0x0c9c: return "hpmcounter28h";
case 0x0c9d: return "hpmcounter29h";
case 0x0c9e: return "hpmcounter30h";
case 0x0c9f: return "hpmcounter31h";
case 0x0100: return "sstatus";
case 0x0102: return "sedeleg";
case 0x0103: return "sideleg";
case 0x0104: return "sie";
case 0x0105: return "stvec";
case 0x0106: return "scounteren";
case 0x0140: return "sscratch";
case 0x0141: return "sepc";
case 0x0142: return "scause";
case 0x0143: return "stval";
case 0x0144: return "sip";
case 0x0180: return "satp";
case 0x0f11: return "mvendorid";
case 0x0f12: return "marchid";
case 0x0f13: return "mimpid";
case 0x0f14: return "mhartid";
case 0x0300: return "mstatus";
case 0x0301: return "misa";
case 0x0302: return "medeleg";
case 0x0303: return "mideleg";
case 0x0304: return "mie";
case 0x0305: return "mtvec";
case 0x0306: return "mcounteren";
case 0x0340: return "mscratch";
case 0x0341: return "mepc";
case 0x0342: return "mcause";
case 0x0343: return "mtval";
case 0x0344: return "mip";
case 0x03a0: return "pmpcfg0";
case 0x03a1: return "pmpcfg1";
case 0x03a2: return "pmpcfg2";
case 0x03a3: return "pmpcfg3";
case 0x03b0: return "pmpaddr0";
case 0x03b1: return "pmpaddr1";
case 0x03b2: return "pmpaddr2";
case 0x03b3: return "pmpaddr3";
case 0x03b4: return "pmpaddr4";
case 0x03b5: return "pmpaddr5";
case 0x03b6: return "pmpaddr6";
case 0x03b7: return "pmpaddr7";
case 0x03b8: return "pmpaddr8";
case 0x03b9: return "pmpaddr9";
case 0x03ba: return "pmpaddr10";
case 0x03bb: return "pmpaddr11";
case 0x03bc: return "pmpaddr12";
case 0x03bd: return "pmpaddr13";
case 0x03be: return "pmpaddr14";
case 0x03bf: return "pmpaddr15";
case 0x0b00: return "mcycle";
case 0x0b02: return "minstret";
case 0x0b03: return "mhpmcounter3";
case 0x0b04: return "mhpmcounter4";
case 0x0b05: return "mhpmcounter5";
case 0x0b06: return "mhpmcounter6";
case 0x0b07: return "mhpmcounter7";
case 0x0b08: return "mhpmcounter8";
case 0x0b09: return "mhpmcounter9";
case 0x0b0a: return "mhpmcounter10";
case 0x0b0b: return "mhpmcounter11";
case 0x0b0c: return "mhpmcounter12";
case 0x0b0d: return "mhpmcounter13";
case 0x0b0e: return "mhpmcounter14";
case 0x0b0f: return "mhpmcounter15";
case 0x0b10: return "mhpmcounter16";
case 0x0b11: return "mhpmcounter17";
case 0x0b12: return "mhpmcounter18";
case 0x0b13: return "mhpmcounter19";
case 0x0b14: return "mhpmcounter20";
case 0x0b15: return "mhpmcounter21";
case 0x0b16: return "mhpmcounter22";
case 0x0b17: return "mhpmcounter23";
case 0x0b18: return "mhpmcounter24";
case 0x0b19: return "mhpmcounter25";
case 0x0b1a: return "mhpmcounter26";
case 0x0b1b: return "mhpmcounter27";
case 0x0b1c: return "mhpmcounter28";
case 0x0b1d: return "mhpmcounter29";
case 0x0b1e: return "mhpmcounter30";
case 0x0b1f: return "mhpmcounter31";
case 0x0b80: return "mcycleh";
case 0x0b82: return "minstreth";
case 0x0b83: return "mhpmcounter3h";
case 0x0b84: return "mhpmcounter4h";
case 0x0b85: return "mhpmcounter5h";
case 0x0b86: return "mhpmcounter6h";
case 0x0b87: return "mhpmcounter7h";
case 0x0b88: return "mhpmcounter8h";
case 0x0b89: return "mhpmcounter9h";
case 0x0b8a: return "mhpmcounter10h";
case 0x0b8b: return "mhpmcounter11h";
case 0x0b8c: return "mhpmcounter12h";
case 0x0b8d: return "mhpmcounter13h";
case 0x0b8e: return "mhpmcounter14h";
case 0x0b8f: return "mhpmcounter15h";
case 0x0b90: return "mhpmcounter16h";
case 0x0b91: return "mhpmcounter17h";
case 0x0b92: return "mhpmcounter18h";
case 0x0b93: return "mhpmcounter19h";
case 0x0b94: return "mhpmcounter20h";
case 0x0b95: return "mhpmcounter21h";
case 0x0b96: return "mhpmcounter22h";
case 0x0b97: return "mhpmcounter23h";
case 0x0b98: return "mhpmcounter24h";
case 0x0b99: return "mhpmcounter25h";
case 0x0b9a: return "mhpmcounter26h";
case 0x0b9b: return "mhpmcounter27h";
case 0x0b9c: return "mhpmcounter28h";
case 0x0b9d: return "mhpmcounter29h";
case 0x0b9e: return "mhpmcounter30h";
case 0x0b9f: return "mhpmcounter31h";
case 0x0323: return "mhpmevent3";
case 0x0324: return "mhpmevent4";
case 0x0325: return "mhpmevent5";
case 0x0326: return "mhpmevent6";
case 0x0327: return "mhpmevent7";
case 0x0328: return "mhpmevent8";
case 0x0329: return "mhpmevent9";
case 0x032a: return "mhpmevent10";
case 0x032b: return "mhpmevent11";
case 0x032c: return "mhpmevent12";
case 0x032d: return "mhpmevent13";
case 0x032e: return "mhpmevent14";
case 0x032f: return "mhpmevent15";
case 0x0330: return "mhpmevent16";
case 0x0331: return "mhpmevent17";
case 0x0332: return "mhpmevent18";
case 0x0333: return "mhpmevent19";
case 0x0334: return "mhpmevent20";
case 0x0335: return "mhpmevent21";
case 0x0336: return "mhpmevent22";
case 0x0337: return "mhpmevent23";
case 0x0338: return "mhpmevent24";
case 0x0339: return "mhpmevent25";
case 0x033a: return "mhpmevent26";
case 0x033b: return "mhpmevent27";
case 0x033c: return "mhpmevent28";
case 0x033d: return "mhpmevent29";
case 0x033e: return "mhpmevent30";
case 0x033f: return "mhpmevent31";
case 0x07a0: return "tselect";
case 0x07a1: return "tdata1";
case 0x07a2: return "tdata2";
case 0x07a3: return "tdata3";
case 0x07b0: return "dcsr";
case 0x07b1: return "dpc";
case 0x07b2: return "dscratch";
}
return NULL;
}
static void printCSRSystemRegister(MCInst *MI, unsigned OpNo,
//const MCSubtargetInfo &STI,
SStream *O)
{
unsigned Imm = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
const char *Name = getCSRSystemRegisterName(Imm);
if (Name) {
SStream_concat0(O, Name);
} else {
SStream_concat(O, "%u", Imm);
}
}
static void printFenceArg(MCInst *MI, unsigned OpNo, SStream *O)
{
unsigned FenceArg = MCOperand_getImm(MCInst_getOperand(MI, OpNo));
//CS_ASSERT (((FenceArg >> 4) == 0) && "Invalid immediate in printFenceArg");
if ((FenceArg & RISCVFenceField_I) != 0)
SStream_concat0(O, "i");
if ((FenceArg & RISCVFenceField_O) != 0)
SStream_concat0(O, "o");
if ((FenceArg & RISCVFenceField_R) != 0)
SStream_concat0(O, "r");
if ((FenceArg & RISCVFenceField_W) != 0)
SStream_concat0(O, "w");
if (FenceArg == 0)
SStream_concat0(O, "unknown");
}
static void printFRMArg(MCInst *MI, unsigned OpNo, SStream *O)
{
enum RoundingMode FRMArg =
(enum RoundingMode)MCOperand_getImm(MCInst_getOperand(MI, OpNo));
#if 0
auto FRMArg =
static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm());
O << RISCVFPRndMode::roundingModeToString(FRMArg);
#endif
SStream_concat0(O, roundingModeToString(FRMArg));
}
#endif // CAPSTONE_HAS_RISCV
external/capstone/arch/RISCV/RISCVInstPrinter.h
Vendored
+24
View File
@@ -0,0 +1,24 @@
//===-- RISCVInstPrinter.h - Convert RISCV MCInst to asm syntax ---*- C++ -*--//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints a RISCV MCInst to a .s file.
//
//===----------------------------------------------------------------------===//
#ifndef CS_RISCVINSTPRINTER_H
#define CS_RISCVINSTPRINTER_H
#include "../../MCInst.h"
#include "../../SStream.h"
void RISCV_printInst(MCInst * MI, SStream * O, void *info);
void RISCV_post_printer(csh ud, cs_insn * insn, char *insn_asm, MCInst * mci);
#endif
external/capstone/arch/RISCV/RISCVMapping.c
Vendored
+399
View File
@@ -0,0 +1,399 @@
#ifdef CAPSTONE_HAS_RISCV
#include <stdio.h> // debug
#include <string.h>
#include "../../Mapping.h"
#include "../../utils.h"
#include "../../cs_simple_types.h"
#include "RISCVMapping.h"
#include "RISCVInstPrinter.h"
#define GET_INSTRINFO_ENUM
#include "RISCVGenInstrInfo.inc"
#ifndef CAPSTONE_DIET
static const name_map reg_name_maps[] = {
{ RISCV_REG_INVALID, NULL },
{ RISCV_REG_X0, "zero" },
{ RISCV_REG_X1, "ra" },
{ RISCV_REG_X2, "sp" },
{ RISCV_REG_X3, "gp" },
{ RISCV_REG_X4, "tp" },
{ RISCV_REG_X5, "t0" },
{ RISCV_REG_X6, "t1" },
{ RISCV_REG_X7, "t2" },
{ RISCV_REG_X8, "s0" },
{ RISCV_REG_X9, "s1" },
{ RISCV_REG_X10, "a0" },
{ RISCV_REG_X11, "a1" },
{ RISCV_REG_X12, "a2" },
{ RISCV_REG_X13, "a3" },
{ RISCV_REG_X14, "a4" },
{ RISCV_REG_X15, "a5" },
{ RISCV_REG_X16, "a6" },
{ RISCV_REG_X17, "a7" },
{ RISCV_REG_X18, "s2" },
{ RISCV_REG_X19, "s3" },
{ RISCV_REG_X20, "s4" },
{ RISCV_REG_X21, "s5" },
{ RISCV_REG_X22, "s6" },
{ RISCV_REG_X23, "s7" },
{ RISCV_REG_X24, "s8" },
{ RISCV_REG_X25, "s9" },
{ RISCV_REG_X26, "s10" },
{ RISCV_REG_X27, "s11" },
{ RISCV_REG_X28, "t3" },
{ RISCV_REG_X29, "t4" },
{ RISCV_REG_X30, "t5" },
{ RISCV_REG_X31, "t6" },
{ RISCV_REG_F0_32, "ft0" },
{ RISCV_REG_F0_64, "ft0" },
{ RISCV_REG_F1_32, "ft1" },
{ RISCV_REG_F1_64, "ft1" },
{ RISCV_REG_F2_32, "ft2" },
{ RISCV_REG_F2_64, "ft2" },
{ RISCV_REG_F3_32, "ft3" },
{ RISCV_REG_F3_64, "ft3" },
{ RISCV_REG_F4_32, "ft4" },
{ RISCV_REG_F4_64, "ft4" },
{ RISCV_REG_F5_32, "ft5" },
{ RISCV_REG_F5_64, "ft5" },
{ RISCV_REG_F6_32, "ft6" },
{ RISCV_REG_F6_64, "ft6" },
{ RISCV_REG_F7_32, "ft7" },
{ RISCV_REG_F7_64, "ft7" },
{ RISCV_REG_F8_32, "fs0" },
{ RISCV_REG_F8_64, "fs0" },
{ RISCV_REG_F9_32, "fs1" },
{ RISCV_REG_F9_64, "fs1" },
{ RISCV_REG_F10_32, "fa0" },
{ RISCV_REG_F10_64, "fa0" },
{ RISCV_REG_F11_32, "fa1" },
{ RISCV_REG_F11_64, "fa1" },
{ RISCV_REG_F12_32, "fa2" },
{ RISCV_REG_F12_64, "fa2" },
{ RISCV_REG_F13_32, "fa3" },
{ RISCV_REG_F13_64, "fa3" },
{ RISCV_REG_F14_32, "fa4" },
{ RISCV_REG_F14_64, "fa4" },
{ RISCV_REG_F15_32, "fa5" },
{ RISCV_REG_F15_64, "fa5" },
{ RISCV_REG_F16_32, "fa6" },
{ RISCV_REG_F16_64, "fa6" },
{ RISCV_REG_F17_32, "fa7" },
{ RISCV_REG_F17_64, "fa7" },
{ RISCV_REG_F18_32, "fs2" },
{ RISCV_REG_F18_64, "fs2" },
{ RISCV_REG_F19_32, "fs3" },
{ RISCV_REG_F19_64, "fs3" },
{ RISCV_REG_F20_32, "fs4" },
{ RISCV_REG_F20_64, "fs4" },
{ RISCV_REG_F21_32, "fs5" },
{ RISCV_REG_F21_64, "fs5" },
{ RISCV_REG_F22_32, "fs6" },
{ RISCV_REG_F22_64, "fs6" },
{ RISCV_REG_F23_32, "fs7" },
{ RISCV_REG_F23_64, "fs7" },
{ RISCV_REG_F24_32, "fs8" },
{ RISCV_REG_F24_64, "fs8" },
{ RISCV_REG_F25_32, "fs9" },
{ RISCV_REG_F25_64, "fs9" },
{ RISCV_REG_F26_32, "fs10" },
{ RISCV_REG_F26_64, "fs10" },
{ RISCV_REG_F27_32, "fs11" },
{ RISCV_REG_F27_64, "fs11" },
{ RISCV_REG_F28_32, "ft8" },
{ RISCV_REG_F28_64, "ft8" },
{ RISCV_REG_F29_32, "ft9" },
{ RISCV_REG_F29_64, "ft9" },
{ RISCV_REG_F30_32, "ft10" },
{ RISCV_REG_F30_64, "ft10" },
{ RISCV_REG_F31_32, "ft11" },
{ RISCV_REG_F31_64, "ft11" },
};
#endif
const char *RISCV_reg_name(csh handle, unsigned int reg)
{
#ifndef CAPSTONE_DIET
if (reg >= RISCV_REG_ENDING)
return NULL;
return reg_name_maps[reg].name;
#else
return NULL;
#endif
}
static const insn_map insns[] = {
// dummy item
{
0, 0,
#ifndef CAPSTONE_DIET
{0}, {0}, {0}, 0, 0
#endif
},
#include "RISCVMappingInsn.inc"
};
#ifndef CAPSTONE_DIET
static const map_insn_ops insn_operands[] = {
#include "RISCVMappingInsnOp.inc"
};
#endif
void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum) {
if (!detail_is_set(MI))
return;
cs_op_type op_type = map_get_op_type(MI, OpNum);
if (op_type == CS_OP_IMM) {
RISCV_get_detail_op(MI, 0)->type = RISCV_OP_IMM;
RISCV_get_detail_op(MI, 0)->imm = MCInst_getOpVal(MI, OpNum);
RISCV_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
RISCV_inc_op_count(MI);
}
else if (op_type == CS_OP_REG) {
RISCV_get_detail_op(MI, 0)->type = RISCV_OP_REG;
RISCV_get_detail_op(MI, 0)->reg = MCInst_getOpVal(MI, OpNum);
RISCV_get_detail_op(MI, 0)->access = map_get_op_access(MI, OpNum);
RISCV_inc_op_count(MI);
}
else {
CS_ASSERT(0 && "Op type not handled.");
}
}
// given internal insn id, return public instruction info
void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id)
{
unsigned int i;
i = insn_find(insns, ARR_SIZE(insns), id, &h->insn_cache);
if (i != 0) {
insn->id = insns[i].mapid;
if (h->detail_opt) {
#ifndef CAPSTONE_DIET
memcpy(insn->detail->regs_read,
insns[i].regs_use, sizeof(insns[i].regs_use));
insn->detail->regs_read_count = (uint8_t)count_positive(insns[i].regs_use);
memcpy(insn->detail->regs_write, insns[i].regs_mod, sizeof(insns[i].regs_mod));
insn->detail->regs_write_count = (uint8_t)count_positive(insns[i].regs_mod);
memcpy(insn->detail->groups, insns[i].groups, sizeof(insns[i].groups));
insn->detail->groups_count = (uint8_t)count_positive8(insns[i].groups);
if (insns[i].branch || insns[i].indirect_branch) {
// this insn also belongs to JUMP group. add JUMP group
insn->detail->groups[insn->detail->groups_count] = RISCV_GRP_JUMP;
insn->detail->groups_count++;
}
#endif
}
}
}
static const name_map insn_name_maps[] = {
{RISCV_INS_INVALID, NULL},
#include "RISCVGenInsnNameMaps.inc"
};
const char *RISCV_insn_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
if (id >= RISCV_INS_ENDING)
return NULL;
return insn_name_maps[id].name;
#else
return NULL;
#endif
}
#ifndef CAPSTONE_DIET
static const name_map group_name_maps[] = {
// generic groups
{ RISCV_GRP_INVALID, NULL },
{ RISCV_GRP_JUMP, "jump" },
{ RISCV_GRP_CALL, "call" },
{ RISCV_GRP_RET, "ret" },
{ RISCV_GRP_INT, "int" },
{ RISCV_GRP_IRET, "iret" },
{ RISCV_GRP_PRIVILEGE, "privileged" },
{ RISCV_GRP_BRANCH_RELATIVE, "branch_relative" },
// architecture specific
{ RISCV_GRP_ISRV32, "isrv32" },
{ RISCV_GRP_ISRV64, "isrv64" },
{ RISCV_GRP_HASSTDEXTA, "hasStdExtA" },
{ RISCV_GRP_HASSTDEXTC, "hasStdExtC" },
{ RISCV_GRP_HASSTDEXTD, "hasStdExtD" },
{ RISCV_GRP_HASSTDEXTF, "hasStdExtF" },
{ RISCV_GRP_HASSTDEXTM, "hasStdExtM" },
/*
{ RISCV_GRP_ISRVA, "isrva" },
{ RISCV_GRP_ISRVC, "isrvc" },
{ RISCV_GRP_ISRVD, "isrvd" },
{ RISCV_GRP_ISRVCD, "isrvcd" },
{ RISCV_GRP_ISRVF, "isrvf" },
{ RISCV_GRP_ISRV32C, "isrv32c" },
{ RISCV_GRP_ISRV32CF, "isrv32cf" },
{ RISCV_GRP_ISRVM, "isrvm" },
{ RISCV_GRP_ISRV64A, "isrv64a" },
{ RISCV_GRP_ISRV64C, "isrv64c" },
{ RISCV_GRP_ISRV64D, "isrv64d" },
{ RISCV_GRP_ISRV64F, "isrv64f" },
{ RISCV_GRP_ISRV64M, "isrv64m" }
*/
{ RISCV_GRP_ENDING, NULL }
};
#endif
const char *RISCV_group_name(csh handle, unsigned int id)
{
#ifndef CAPSTONE_DIET
// verify group id
if (id >= RISCV_GRP_ENDING ||
(id > RISCV_GRP_BRANCH_RELATIVE && id < RISCV_GRP_ISRV32))
return NULL;
return id2name(group_name_maps, ARR_SIZE(group_name_maps), id);
#else
return NULL;
#endif
}
// map instruction name to public instruction ID
riscv_reg RISCV_map_insn(const char *name)
{
// handle special alias first
unsigned int i;
// NOTE: skip first NULL name in insn_name_maps
i = name2id(&insn_name_maps[1], ARR_SIZE(insn_name_maps) - 1, name);
return (i != -1) ? i : RISCV_REG_INVALID;
}
// map internal raw register to 'public' register
riscv_reg RISCV_map_register(unsigned int r)
{
static const unsigned int map[] = { 0,
RISCV_REG_X0,
RISCV_REG_X1,
RISCV_REG_X2,
RISCV_REG_X3,
RISCV_REG_X4,
RISCV_REG_X5,
RISCV_REG_X6,
RISCV_REG_X7,
RISCV_REG_X8,
RISCV_REG_X9,
RISCV_REG_X10,
RISCV_REG_X11,
RISCV_REG_X12,
RISCV_REG_X13,
RISCV_REG_X14,
RISCV_REG_X15,
RISCV_REG_X16,
RISCV_REG_X17,
RISCV_REG_X18,
RISCV_REG_X19,
RISCV_REG_X20,
RISCV_REG_X21,
RISCV_REG_X22,
RISCV_REG_X23,
RISCV_REG_X24,
RISCV_REG_X25,
RISCV_REG_X26,
RISCV_REG_X27,
RISCV_REG_X28,
RISCV_REG_X29,
RISCV_REG_X30,
RISCV_REG_X31,
RISCV_REG_F0_32,
RISCV_REG_F0_64,
RISCV_REG_F1_32,
RISCV_REG_F1_64,
RISCV_REG_F2_32,
RISCV_REG_F2_64,
RISCV_REG_F3_32,
RISCV_REG_F3_64,
RISCV_REG_F4_32,
RISCV_REG_F4_64,
RISCV_REG_F5_32,
RISCV_REG_F5_64,
RISCV_REG_F6_32,
RISCV_REG_F6_64,
RISCV_REG_F7_32,
RISCV_REG_F7_64,
RISCV_REG_F8_32,
RISCV_REG_F8_64,
RISCV_REG_F9_32,
RISCV_REG_F9_64,
RISCV_REG_F10_32,
RISCV_REG_F10_64,
RISCV_REG_F11_32,
RISCV_REG_F11_64,
RISCV_REG_F12_32,
RISCV_REG_F12_64,
RISCV_REG_F13_32,
RISCV_REG_F13_64,
RISCV_REG_F14_32,
RISCV_REG_F14_64,
RISCV_REG_F15_32,
RISCV_REG_F15_64,
RISCV_REG_F16_32,
RISCV_REG_F16_64,
RISCV_REG_F17_32,
RISCV_REG_F17_64,
RISCV_REG_F18_32,
RISCV_REG_F18_64,
RISCV_REG_F19_32,
RISCV_REG_F19_64,
RISCV_REG_F20_32,
RISCV_REG_F20_64,
RISCV_REG_F21_32,
RISCV_REG_F21_64,
RISCV_REG_F22_32,
RISCV_REG_F22_64,
RISCV_REG_F23_32,
RISCV_REG_F23_64,
RISCV_REG_F24_32,
RISCV_REG_F24_64,
RISCV_REG_F25_32,
RISCV_REG_F25_64,
RISCV_REG_F26_32,
RISCV_REG_F26_64,
RISCV_REG_F27_32,
RISCV_REG_F27_64,
RISCV_REG_F28_32,
RISCV_REG_F28_64,
RISCV_REG_F29_32,
RISCV_REG_F29_64,
RISCV_REG_F30_32,
RISCV_REG_F30_64,
RISCV_REG_F31_32,
RISCV_REG_F31_64,
};
if (r < ARR_SIZE(map))
return map[r];
// cannot find this register
return 0;
}
#endif
external/capstone/arch/RISCV/RISCVMapping.h
Vendored
+24
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@@ -0,0 +1,24 @@
#ifndef CS_RISCV_MAP_H
#define CS_RISCV_MAP_H
#include "../../include/capstone/capstone.h"
// given internal insn id, return public instruction info
void RISCV_get_insn_id(cs_struct * h, cs_insn * insn, unsigned int id);
const char *RISCV_insn_name(csh handle, unsigned int id);
const char *RISCV_group_name(csh handle, unsigned int id);
const char *RISCV_reg_name(csh handle, unsigned int reg);
void RISCV_add_cs_detail(MCInst *MI, unsigned OpNum);
// map instruction name to instruction ID
riscv_reg RISCV_map_insn(const char *name);
// map internal raw register to 'public' register
riscv_reg RISCV_map_register(unsigned int r);
#endif
external/capstone/arch/RISCV/RISCVMappingInsn.inc
Vendored
+1635
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File diff suppressed because it is too large Load Diff
external/capstone/arch/RISCV/RISCVMappingInsnOp.inc
Vendored
+2438
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File diff suppressed because it is too large Load Diff
external/capstone/arch/RISCV/RISCVModule.c
Vendored
+45
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@@ -0,0 +1,45 @@
/* Capstone Disassembly Engine */
/* RISC-V Backend By Rodrigo Cortes Porto <porto703@gmail.com> &
Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
#ifdef CAPSTONE_HAS_RISCV
#include "../../utils.h"
#include "../../MCRegisterInfo.h"
#include "RISCVDisassembler.h"
#include "RISCVInstPrinter.h"
#include "RISCVMapping.h"
#include "RISCVModule.h"
cs_err RISCV_global_init(cs_struct * ud)
{
MCRegisterInfo *mri;
mri = cs_mem_malloc(sizeof(*mri));
RISCV_init(mri);
ud->printer = RISCV_printInst;
ud->printer_info = mri;
ud->getinsn_info = mri;
ud->disasm = RISCV_getInstruction;
ud->post_printer = NULL;
ud->reg_name = RISCV_reg_name;
ud->insn_id = RISCV_get_insn_id;
ud->insn_name = RISCV_insn_name;
ud->group_name = RISCV_group_name;
return CS_ERR_OK;
}
cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value)
{
if (type == CS_OPT_SYNTAX) {
handle->syntax = (int)value;
} else if (type == CS_OPT_MODE) {
handle->mode = (cs_mode)value;
}
return CS_ERR_OK;
}
#endif
external/capstone/arch/RISCV/RISCVModule.h
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+12
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/* Capstone Disassembly Engine */
/* By Shawn Chang <citypw@gmail.com>, HardenedLinux@2018 */
#ifndef CS_RISCV_MODULE_H
#define CS_RISCV_MODULE_H
#include "../../utils.h"
cs_err RISCV_global_init(cs_struct * ud);
cs_err RISCV_option(cs_struct * handle, cs_opt_type type, size_t value);
#endif